Emulation Architecture Research Articles

A novel and compact MOSFET-C only based grounded meminductor emulator and its application

This article presents a grounded meminductor emulator architecture based on only MOSFETs and two capacitors. Proposed models do not use any extra components like a resistor, multiplier, or buffer. The simulation and verification of the proposed emulator are performed using Cadence Virtuoso with a 180 nm CMOS process parameter. The offered emulator requires ±0.9 V DC power supply and its static power consumption is 0.421 mW. The maximum operating frequency of the meminductor is 32 MHz. The usefulness and reliability of the offered design are tested by performing various types of simulation including Monte Carlo and temperature variation. The chaotic oscillator is designed that demonstrate the viability of the suggested meminductor emulator.

Emulation of Cloud Microphysics in a Climate Model

AbstractWe present a machine learning based emulator of a microphysics scheme for condensation and precipitation processes (Zhao‐Carr) used operationally in a global atmospheric forecast model (FV3GFS). Our tailored emulator architecture achieves high skill (≥94%) in predicting condensate and precipitation amounts and maintains low global‐average bias (≤4%) for 1 year of continuous simulation when replacing the Fortran scheme. The stability and success of this emulator stems from key design decisions. By separating the emulation of condensation and precipitation processes, we can better enforce physical priors such as mass conservation and locality of condensation, and the vertical dependence of precipitation falling downward, using specific network architectures. An activity classifier for condensation imitates the discrete‐continuous nature of the Fortran microphysics outputs (i.e., tendencies are identically zero where the scheme is inactive, and condensate is zero where clouds are fully evaporated). A temperature‐scaled conditional loss function ensures accurate condensate adjustments for a high dynamic range of cloud types (e.g., cold, low‐condensate cirrus clouds or warm, condensate‐rich clouds). Despite excellent overall performance, the emulator exhibits some deficiencies in the uppermost model levels, leading to biases in the stratosphere. The emulator also has short episodic skill dropouts in isolated grid columns and is computationally slower than the original Fortran scheme. Nonetheless, our challenges and strategies should be applicable to the emulation of other microphysical schemes. More broadly, our work demonstrates that with suitable physically motivated architectural choices, ML techniques can accurately emulate complex human‐designed parameterizations of fast physical processes central to weather and climate models.

Integrable emulation of a floating incremental/decremental inverse memristor for memristor bandwidth extension

Abstract The article explores the compact emulation of the inverse memristor through a circuit-based approach. It introduces a floating emulator architecture that incorporates a dual output OTA (Operation Transconductance Amplifier) and DVCC (Differential Voltage Current Conveyor), along with two grounded passive elements, to achieve the emulation of an inverse memristor. The utilization of grounded resistance allows for tunability over the realized behaviour. A key contribution of this research is the novel application of the inverse memristor to extend the operating frequency range of any memristor emulator circuit. Validation of the proposed emulator circuit, in both incremental and decremental modes, along with its application, is conducted using PSPICE-generated simulation results in the 0.18 µm TSMC CMOS technology. Additionally, an inverse memristor emulator configuration employing the IC LM13700 is presented, and its functionality is tested through a breadboard implementation.

Overlay-Based Android Malware Detection at Market Scales: Systematically Adapting to the New Technological Landscape

Android <i>overlay</i> enables one app to draw over other apps by creating an extra <monospace>View</monospace> layer atop the host <monospace>View</monospace> , which nevertheless can be exploited by malicious apps (malware) to attack users. To combat this threat, prior countermeasures concentrate on restricting the capabilities of overlays at the OS level while sacrificing overlays’ usability; recently, the overlay mechanism has been substantially updated to prevent a variety of attacks, which however can still be evaded by considerable adversaries. To address these shortcomings, a more pragmatic approach is to enable <i>early detection</i> of overlay-based malware during the app market review process, so that all the capabilities of overlays can stay unchanged. For this purpose, in this paper we first conduct a large-scale comparative study of overlay characteristics in benign and malicious apps, and then implement the OverlayChecker system to automatically detect overlay-based malware for one of the world’s largest Android app stores. In particular, we have made systematic efforts in feature engineering, UI exploration, emulation architecture, and run-time environment, thus maintaining high detection accuracy (97 percent precision and 97 percent recall) and short per-app scan time ( <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 1.7 minutes) with only two commodity servers, under an intensive workload of <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 10K newly submitted apps per day.

A compact floating and grounded memristor model using single active element

Memristor with defined operational specifications is a challenging task that promotes innovation in emulation circuit modelling. This article presents a single active block based compact memristor emulator architecture which is suitable for both floating and grounded circuit topologies. It effectively operates in incremental/decremental modes in both the configurations. The proposed model utilizes only one Differential Voltage Current Conveyor Transconductance Amplifier (DVCCTA) as an active block along with a few passive components. It discourages the use of extra sub-circuit components like multiple active blocks, summers and multipliers. The circuit is intended to work at ±1 V of dc power supply and has a power consumption of 8.74 mW. The proposed emulator model exhibits all the characteristics of an ideal memristor with an operating frequency of 12.8 MHz. It has wide working voltage range of 50–500 mV. The memristor model is built and simulated using the TSMC 0.18 μm CMOS process parameter. The reliability and effectiveness of the proposed model is verified through non-ideal, Monte-Carlo, process corner, non-volatility and temperature variation analysis. Furthermore, the memristor prototype is constructed on the breadboard using discrete ICs AD844AN and CA3080. The experimental outcome is found in accordance with the simulation. The applicability of the proposed memristor model is verified by implementing a memristor based Schmitt trigger circuit.

VDTA and DO-CCII based incremental/decremental floating memductance/meminductance simulator: A novel realization

The meminductor element is useful just like the memristor element due to the similar kind of hysteresis property found in its transient characteristics. This study presents a floating memelement emulator to realize the dual memelement function (memristor and meminductor) using a VDTA (Voltage Differencing Transconductance Amplifier) and a DO-CCII (Dual Output Second Generation Current Conveyor) based compact circuit configuration. The developed emulator architecture requires only three passive elements (all in the grounded state) with just two active elements to realize the floating meminductor and memristor suitable for both incremental as well as decremental modes of operation. The tuning of the proposed circuit to provide desired memelement behavior realization (memristor or meminductor) can be obtained by selecting an employed grounded impedance as a capacitor and resistor respectively. No use of any floating passive element and external memristor emulator is a remarkable design feature along with the feature of tunability found in the proposed emulator circuit enriching the superiority of its design. The circuit analysis also shows that the selection of the grounded impedance as an inductor can also lead to the realization of a non-linear capacitor, which is the dual of a memcapacitor element. The workability of the presented emulator circuit is validated through the simulations generated for the 0.18μm CMOS technology in the PSPICE environment. The application examples of both the realized floating elements have been presented and verified through the presented simulation results. Also, the reported memelement emulator has been implemented and verified by using commercially available ICs; AD844 and LM13700.

Cloud-Based User Behavior Emulation Approach for Space-Ground Integrated Networks.

Cyber-physical systems (CPSs) based on space-ground integrated networks (SGINs) enable CPSs to break through geographical restrictions in space. Therefore, providing a test platform is necessary for new technical verification and network security strategy evaluations of SGINs. User behavior emulation technology can effectively support the construction of a test platform. Given the inherent dynamic changes, diverse behaviors, and large-scale characteristics of SGIN users, we propose user behavior emulation technology based on a cloud platform. First, the dynamic emulation architecture for user behavior for SGINs is designed. Then, normal user behavior emulation strategy driven by the group user behavior model in real time is proposed, which can improve the fidelity of emulation. Moreover, rogue user behavior emulation technology is adopted, based on traffic replay, to perform the security evaluation. Specifically, virtual Internet Protocol (IP) technology and the epoll model are effectively integrated in this investigation to resolve the contradiction between large-scale emulation and computational overhead. The experimental results demonstrate that the strategy meets the requirement of a diverse and high-fidelity dynamic user behavior emulation and reaches the emulation scale of 100,000-level concurrent communication for normal users and 100,000-level concurrent attacks for rogue users.

High-Performance Routing Emulation Technologies Based on a Cloud Platform

Currently, the emergence of edge computing provides low-latency and high-efficiency computing for the Internet of Things (IoT). However, new architectures, protocols, and security technologies of edge computing need to be verified and evaluated before use. Since network emulation based on a cloud platform has advantages in scalability and fidelity, it can provide an effective network environment for verifying and evaluating new edge computing technologies. Therefore, we propose a high-performance emulation technology supporting the routing protocol based on a cloud platform. First, we take OpenStack as a basic network environment. To improve the performance and scalability of routing emulation, we then design the routing emulation architecture according to the software-defined network (SDN) and design the cluster scheduling mechanism. Finally, the design of the Open Shortest Path First (OSPF) protocol can support communication with physical routers. Through extensive experiments, we demonstrate that this technology not only can provide a realistic OSPF protocol but also has obvious advantages in the overhead and performance of routing nodes compared with those of other network emulation technologies. Furthermore, the realization of the controller cluster improves the scalability in the emulation scale.

On the Application of a Diffusive Memristor Compact Model to Neuromorphic Circuits.

Memristive devices have found application in both random access memory and neuromorphic circuits. In particular, it is known that their behavior resembles that of neuronal synapses. However, it is not simple to come by samples of memristors and adjusting their parameters to change their response requires a laborious fabrication process. Moreover, sample to sample variability makes experimentation with memristor-based synapses even harder. The usual alternatives are to either simulate or emulate the memristive systems under study. Both methodologies require the use of accurate modeling equations. In this paper, we present a diffusive compact model of memristive behavior that has already been experimentally validated. Furthermore, we implement an emulation architecture that enables us to freely explore the synapse-like characteristics of memristors. The main advantage of emulation over simulation is that the former allows us to work with real-world circuits. Our results can give some insight into the desirable characteristics of the memristors for neuromorphic applications.

An FPGA-based real quantum computer emulator

While we cannot efficiently emulate quantum algorithms on classical architectures, we can move the weight of complexity from time to hardware resources. This paper describes a proposition of a universal and scalable quantum computer emulator, in which the FPGA hardware emulates the behavior of a real quantum system, capable of running quantum algorithms while maintaining their natural time complexity. The article also shows the proposed quantum emulator architecture, exposing a standard programming interface, and working results of an implementation of an exemplary quantum algorithm.

Emulation of an Electric Naval Propulsion System Based on a Multiphase Machine Under Healthy and Faulty Operating Conditions

The main objective of this paper is the design of an Electric Naval Propulsion System (ENPS) emulator based on a low power multiphase machine. The whole drive system (control, power electronics, and electric machine) is tested and the mechanical part is emulated based on a Hardware-in-the-Loop principle. First, the modeling of all system components including mechanical and electrical parts are reviewed, and the total hull resistance forces are also developed. Then, a pure software simulation of the ENPS is carried out. After that, the designed emulator architecture is presented, and for adaption purpose, a scaling factor is introduced. The developed emulation tool allows to validate optimal control strategies for the propulsion system under a realistic navigation cycle under healthy and faulty operating conditions. Finally, simulation and experimental results are compared to investigate the accuracy and the performance of the developed emulator, and the effectiveness of the proposed control strategies.

Real‐Time Emulation of Nonstationary Channels in Safety‐Relevant Vehicular Scenarios

This paper proposes and discusses the architecture for a real‐time vehicular channel emulator capable of reproducing the input/output behavior of nonstationary time‐variant radio propagation channels in safety‐relevant vehicular scenarios. The vehicular channel emulator architecture aims at a hardware implementation which requires minimal hardware complexity for emulating channels with the varying delay‐Doppler characteristics of safety‐relevant vehicular scenarios. The varying delay‐Doppler characteristics require real‐time updates to the multipath propagation model for each local stationarity region. The vehicular channel emulator is used for benchmarking the packet error performance of commercial off‐the‐shelf (COTS) vehicular IEEE 802.11p modems and a fully software‐defined radio‐based IEEE 802.11p modem stack. The packet error ratio (PER) estimated from temporal averaging over a single virtual drive and the packet error probability (PEP) estimated from ensemble averaging over repeated virtual drives are evaluated and compared for the same vehicular scenario. The proposed architecture is realized as a virtual instrument on National Instruments™ LabVIEW. The National Instrument universal software radio peripheral with reconfigurable input‐output (USRP‐Rio) 2953R is used as the software‐defined radio platform for implementation; however, the results and considerations reported are of general purpose and can be applied to other platforms. Finally, we discuss the PER performance of the modem for two categories of vehicular channel models: a vehicular nonstationary channel model derived for urban single lane street crossing scenario of the DRIVEWAY’09 measurement campaign and the stationary ETSI models.

An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.

Virtualization Technology for TCP/IP Offload Engine

Network I/O virtualization plays an important role in cloud computing. This paper addresses the system-wide virtualization issues of TCP/IP Offload Engine (TOE) and presents the architectural designs. We identify three critical factors that affect the performance of a TOE: I/O virtualization architectures, quality of service (QoS), and virtual machine monitor (VMM) scheduler. In our device emulation based TOE, the VMM manages the socket connections in the TOE directly and thus can eliminate packet copy and demultiplexing overheads as appeared in the virtualization of a layer 2 network card. To further reduce hypervisor intervention, the direct I/O access architecture provides the per VM-based physical control interface that helps removing most of the VMM interventions. The direct I/O access architecture out-performs the device emulation architecture as large as 30 percent, or achieves 80 percent of the native 10 Gbit/s TOE system. To continue serving the TOE commands for a VM, no matter the VM is idle or switched out by the VMM, we decouple the TOE I/O command dispatcher from the VMM scheduler. We found that a VMM scheduler with preemptive I/O scheduling and a programmable I/O command dispatcher with deficit weighted round robin (DWRR) policy are able to ensure service fairness and at the same time maximize the TOE utilization.

Scalable Network Emulation - The NET Approach

Network emulation is an efficient method for evaluating distributed applications and communication protocols bycombining the benefits of real world experiments and networksimulation. The process of network emulation involves the executionof connected virtual nodes running the software under test ina controlled environment. Our Network Emulation Testbed (NET) achieves high scalability by combining efficient node virtualization and adaptive virtual time. In this paper, we provide an overview of our system. First, we introduce our efficient emulation architecture. Second, we present our approaches ( NETplace and NETbalance ) to minimize the runtime of the network experiments. The idea of NETplace is to minimize the load of the testbed by calculating an initial placement of virtual nodes onto the testbed nodes. During the runtime of the experiment NETbalance adapts this placement to changed resource requirements of the software under test. Finally, we introduce NETcaptain , a graphical user interface to setup, control and visualize network experiments.

Variation-Aware Adaptive Voltage Scaling System

Conventional voltage scaling systems require a delay margin to maintain a certain level of robustness across all possible device and wire process variations and temperature fluctuations. This margin is required to cover for a possible change in the critical path due to such variations. Moreover, a slower interconnect delay scaling with voltage compared to logic delay can cause the critical path to change from one operating voltage to another. With technology scaling, both process variation and interconnect delay are growing and demanding more margin to guarantee an error-free operation. Such margin is translated into a voltage overhead and a corresponding energy inefficiency. In this paper, a critical path emulator architecture is shown to track the changing critical path at different process splits by probing the actual transistor and wire conditions. Furthermore, voltage scaling characteristics of the actual critical path is closely tracked by programming logic and interconnect delay lines to achieve the same delay combination as the actual critical path. Compared to conventional open-loop and closed-loop systems, the proposed system is up to 39% and 24% more energy efficient, respectively. A 0.18-mum technology test chip is designed to verify the functionality of the proposed system showing critical path tracking of a 16times16 bit multiplier

LAN emulation on an ATM network

The authors evaluate architecture alternatives relating to the provision of a LAN emulation service over a connection-oriented ATM network, and present the LAN emulation architecture as actually adopted by the ATM Forum LANE SWG. The role of servers is discussed as is the provision of broadcast/multicast services. >

Hierarchical emulation of well-coded programs through the use of streams of instructions buffered in on-chip associative memories and distributed control

Due to the rapid development of the VLSI technology, it is feasible to place the cache memory on the processor chip. This paper proposes an associative sequencer containing an on-chip cache memory. The sequencer emulates operations by streams of instructions and is hence called ‘associative stream emulator’. The associative cache memory stores emulation streams for operations belonging to several lexical levels. This includes also microinstruction streams. The individual instructions in the streams are frequency coded. This leads to code compaction, which increases the effective instruction transfer rate on the memory-processor bus enhancing by that the performance. A possible emulator architecture and its instruction stream processing principles are described. The structure of the associative cache cell is outlined. The operations on the cache memory are explained. Statistical measurement and their results are shown. These results prove that in order to obtain a reasonable performance it is enough with 50–150 cells in the cache memory.