Emitter Wrap-through Cells Research Articles

2-D SPICE Simulation and Analytical Calculation of Spreading Resistance Effects in Emitter Wrap-Through Cells With Nonsquare Via-Hole Pattern

Cell concepts that feature via-holes, like the emitter wrap-through concept, suffer from higher series resistance losses than conventional solar cells. A part of these resistance losses is due to the fact that a small size element, in this case a via-hole, has to collect the current of a wide area on the front side, which leads to the so-called spreading resistance. An analytical equation already exists which describes the spreading resistance effects that are present in these cells. This equation is an accurate description for a quadratic or hexagonal pattern of via-holes. For cells that feature an interdigitated metallization grid on the rear side, like emitter wrap-through solar cells, the arrangement is often nonsquare because the distance between two via-holes is different in the x- and y-directions. In this paper, it is shown that the existing formula is in excellent correlation with the results from simulation program with integrated circuit emphasis (SPICE) simulation if a quadratic symmetry element is chosen. The SPICE simulation is then adjusted for nonsquare symmetry elements, showing that the existing formula is not valid for these arrangements and has to be modified. The derived analytical modification is adapted to yield a better description of the spreading resistance in the emitter of such a cell structure for variable via-hole distances in the x- and y-directions. The relative deviation between the simulation results and the analytic approach is less than 15%. This enables an accurate calculation of the resistance losses of relevant technological configurations.

PC2D: A Circular-Reference Spreadsheet Solar Cell Device Simulator

This paper introduces PC2D, which is a new silicon solar cell device simulator that models 2-D effects entirely within a Microsoft Excel spreadsheet. The semiconductor drift-diffusion equations for electrons and holes are implemented using an iterative solution of cell formulas containing circular references. The familiar spreadsheet user interface and open-source access make this 2-D simulator a natural companion to PC1D. The 2-D simulator can run “live,” responding immediately to every change in parameter, or in “drive” mode, using macros to guide the solver through common tasks such as generating a current-voltage or a quantum efficiency curve. Example device simulations are presented for a selective-emitter cell, an emitter wrap-through cell, and an interdigitated back-contact cell.

Loss analysis of emitter-wrap-through silicon solar cells by means of experiment and three-dimensional device modeling

Currently, the emitter-wrap-through (EWT) design of Si solar cells is being intensively investigated as a potential candidate for cheap, low-quality Si materials. So far, experimentally achieved energy conversion efficiencies have stayed unexpectedly far below the expectations of common device theory. Therefore, we analyze fabricated EWT cells in detail and refine device theory to account for the limiting loss mechanisms present only in EWT cells. By means of rigorous three-dimensional numerical device modeling, we show that the fill factor (FF) is significantly reduced, primarily due to a effect we call the via-resistance induced recombination enhancement effect. The FF is only secondarily reduced by the resistive losses in the vias where the emitter is wrapped through the cell. This implies that lowering the base resistivity will improve cell efficiency more effectively than lowering the resistance in the vias. Our simulations predict that the EWT design with a nonpassivated rear emitter and a homogeneous emitter diffusion leads to an efficiency improvement of about 1% absolute, as compared to the common front-junction design. This is so for excess carrier lifetimes in the bulk between 1 and 100 μs, which means also for multicrystalline cells.

Investigations on low-cost back-contact silicon solar cells

Back-contacted cells offer multiple advantages in regard of reducing module assembling costs and avoiding grid shadowing losses. The investigated emitter-wrap-through (EWT) design is equipped with a front and a rear emitter (Gee et al., Proceedings of the 23th IEEE PVSC, 1993, p. 265). Both emitter areas are electrically connected by small holes drilled into the crystalline silicon wafer. Renouncing on expensive photolithographic steps several techniques appropriate for a low-cost process have been investigated. An increase in J sc of 15% was measured when compared to a conventionally processed reference cell. However, the open-circuit voltage V oc and the fill factor did not improve. Possible reasons for these losses are presented in this paper. The efficiency of one of the best low-cost EWT cells within this work reached 13.6% on Cz-silicon, which is the highest efficiency reported so far for this cell type (Schönecker et al., Proceedings of the Second WCPSEC, 1998, p. 1677).

Circuit modeling of the emitter-wrap-through solar cell

Back-contact solar cells have the potential to reduce module assembly costs and give a higher conversion efficiency. Such a device must be simple to fabricate on an industrial scale and be tolerant of low minority-carrier diffusion lengths. The emitter-wrap-through (EWT) cell is a device design that can meet these goals. In this device, the diffused junction is present on both sides and is connected by laser-drilled holes through the silicon. EWT cells were frequently found to have poor fill factors (FFs) due to shunt-like behavior. The holes were found to possess no defects that adversely affect device performance. However, detailed equivalent circuit modeling of the EWT cell was able to explain the shunt-like behavior. Experiments were performed to confirm the physical mechanisms described by the equivalent circuit model. Device optimization guided by the equivalent circuit model has led to the demonstration of a large area EWT cell with a FF of 77.64% and efficiency of 18.2%.