Embedded Memory Applications Research Articles

High-throughput screening to identify two-dimensional layered phase-change chalcogenides for embedded memory applications

Chalcogenide phase-change materials (PCMs) are showing versatile possibilities in cutting-edge applications, including non-volatile memory, neuromorphic computing, and nano-photonics. However, for embedded phase-change memory applications, conventional PCMs suffer from insufficient thermal stability because of their relatively low crystallization temperatures (Tx). Although doping with additional alloying elements could improve the amorphous stability, it also increases the tendency towards compositional partitioning and phase separation. Recently, a two-dimensional (2D) layered compound CrGeTe3 (CrGT) was developed as a PCM, showing a high Tx ~ 276 °C with an inverse change in resistive-switching character upon phase transition. Here, we report a high-throughput materials screening for 2D layered phase-change chalcogenides. We aim to clarify whether the high Tx and the inverse electrical resistance contrast are intrinsic features of 2D PCMs. In total, twenty-five 2D chalcogenides with CrGT trilayer structures have been identified from a large database. We then focused on selected layered tellurides by performing thorough ab initio simulations and experimental investigations and confirming that their amorphous phase indeed has a much higher Tx than conventional PCMs. We attribute this enhanced amorphous stability to the structurally complex nuclei required to render crystallization possible. Overall, we regard InGeTe3 as a balanced 2D PCM with both high thermal stability and large electrical contrast for embedded memory applications.

Designing Sb phase change materials by alloying with Ga2S3 towards high thermal stability and low resistance drift by bond reconfigurations

The pure Sb phase-change thin films alloyed with Ga2S3 alloy have been prepared and the related properties have been investigated. Compared with pure Sb, Ga2S3-alloyed Sb films exhibit higher crystallization temperature (∼250 °C), larger ten-year data retention temperature (∼166 °C), and higher crystallization activation energy (4.10 eV). These thermal parameters indicate that the thermal stability of the Ga2S3-alloyed Sb thin films can be considerably enhanced due to the formation of high binding energy Sb-S and Sb-Ga bonds. Moreover, the enhanced thermal stability can also significantly lower resistance drift coefficient (0.0014). According to the analysis of the crystallization mechanism, the crystallization kinetic index (n) is determined to be 0.625, implying one-dimensional growth type in Ga2S3-alloyed Sb thin films. This can benefit to reduce the nucleation randomness and decrease resistance drift. The work demonstrates that Ga2S3-alloyed Sb materials have excellent potential for embedded memory applications.

Review of 6T SRAM for Embedded Memory Applications

Due to the substantial impact embedded Static Random Access Memory (SRAM)s have on the overall system and their relatively limited design, it is essential to manage embedded SRAM trade-offs strategically. SRAMs have power, performance and density trade-offs in general. In all applications, all three dimensions are necessary to some extent; accordingly, embedded SRAM design must incorporate the most crucial system-specific requirements when developing embedded SRAM. This paper discusses many SRAM factors, including Static Noise Margin (SNM), Read Access Time (RAT),Write Access Time (WAT), Read Stability and Write Ability, Power, Data Retention Voltage (DRV), and Process Control. All these factors are crucial when designing SRAM for embedded memory applications. There has also been a discussion of the parameter comparisons and the literature review of the current papers.

Wake-Up Free Ferroelectric Capacitor With Quadruple-Level Storage by Inserting ZrO2 Interlayer and Bottom Layer in HfZrOx

Ferroelectric (FE) HfZrOx (HZO) integrated with ZrO2 interlayer and bottom layer was explored as the new stack (TiN/HZO/ZrO2/HZO/ZrO2/TiN) for FE capacitors processed at 400 °C. The capacitors show high remnant polarization (2Pr) of 37 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{C}$ </tex-math></inline-formula> /cm2 with wake-up free behavior up to 108 long-pulse cycles. High orthorhombic phase (o-phase) ratio is confirmed to be the root cause of wake-up free behavior and both ZrO2 layers play the pivotal role as a nucleation layer for o-phase HZO formation while providing tensile stress due to large thermal expansion coefficient mismatch with HZO. Furthermore, capacitors also exhibit quadruple-level cell (4 bits/cell) operation with small device-to-device variation after long cycling. The promising results make the stack eligible for high-performance, high-reliability and high-density embedded memory applications.

A Ge-Channel Ferroelectric Field Effect Transistor With Logic-Compatible Write Voltage

A major roadblock for the integration of ferroelectric-field-effect transistors (FEFETs) at advanced technology nodes for embedded memory applications is their high, logic-incompatible write voltages. Herein, we explore Ge as a channel material to reduce write voltage of FEFET and report the first demonstration of p-type Ge-FEFETs with record low write voltages of ±1.4 V with a memory window (MW) of 0.6 V at DC and write voltages of ±1.4 V, ±1.8 V and ±2.4 V for MW of 0.2 V, 0.5 V and 0.8 V for a write time of 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> , respectively. The write voltages observed in Ge-pFEFETs are ~50% lower than that of a Si-pFEFETs when compared against iso-memory window condition [±2.5 V with a MW of 0.6 V at DC, ±3.5 V for MW of 0.5 V for a write time of 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> ]. Such dramatic reduction of write voltages in Ge-pFEFETs is achieved due to the fact that the native oxide of Ge (GeOx), formed at the Ge interface, has a larger dielectric constant and lower thickness than those for SiO2 on the Si platform. In addition, the lower bandgap and higher dielectric constant of Ge may lead to a lower surface potential for a given semiconductor charge, leading to further reduction in the write voltage. Further, our Ge-pFEFETs show write endurance of 107 cycles (the best-in-class for Ge-pFEFETs, as reported in the literature), excellent data retention, and immediate read-after-write capability. Our results indicate the attractiveness of Ge platform for FEFETs for embedded memory applications.

Field-free reliable magnetization switching in a three-terminal perpendicular magnetic tunnel junction via spin-orbit torque, spin-transfer torque, and voltage-controlled magnetic anisotropy

Magnetic field-free switching of a three-terminal perpendicular magnetic tunnel junction driven by spin-orbit torque (SOT) and spin-transfer torque (STT) in the presence of a voltage-controlled magnetic anisotropy (VCMA) effect was investigated using micromagnetic simulation at 300 K. The VCMA effect assists or hinders magnetization switching depending on the polarity of the applied voltage. Thus, the impact of these effects on switching probabilities was evaluated using two write voltage pulses (V SOT, V STT). By optimizing the configuration of these voltage pulses, we demonstrated 100 successful switchings out of 100 trials within 3.2 ns under a limit voltage of 1.0 V. In addition, the write power consumption for SOT-STT writing with optimal pulse configurations was found to be one order of magnitude lower than that of STT-alone writing. We also found that the SOT-STT writing has the great potential in practical use compared with the external magnetic field assisted SOT-writing. Field-free, reliable, and deterministic SOT-STT switching with low power consumption offers significant advantages for embedded memory applications.

Phase Separation in Ge-Rich GeSbTe at Different Length Scales: Melt-Quenched Bulk versus Annealed Thin Films

Integration of the prototypical GeSbTe (GST) ternary alloys, especially on the GeTe-Sb2Te3 tie-line, into non-volatile memory and nanophotonic devices is a relatively mature field of study. Nevertheless, the search for the next best active material with outstanding properties is still ongoing. This search is relatively crucial for embedded memory applications where the crystallization temperature of the active material has to be higher to surpass the soldering threshold. Increasing the Ge content in the GST alloys seems promising due to the associated higher crystallization temperatures. However, homogeneous Ge-rich GST in the as-deposited condition is thermodynamically unstable, and phase separation upon annealing is unavoidable. This phase separation reduces endurance and is detrimental in fully integrating the alloys into active memory devices. This work investigated the phase separation of Ge-rich GST alloys, specifically Ge5Sb2Te3 or GST523, into multiple (meta)stable phases at different length scales in melt-quenched bulk and annealed thin film. Electron microscopy-based techniques were used in our work for chemical mapping and elemental composition analysis to show the formation of multiple phases. Our results show the formation of alloys such as GST213 and GST324 in all length scales. Furthermore, the alloy compositions and the observed phase separation pathways agree to a large extent with theoretical results from density functional theory calculations.

Scaling magnetic tunnel junction down to single-digit nanometers—Challenges and prospects

Magnetic tunnel junction (MTJ), a spintronics device, has been intensively developed in the past couple of decades because of its high potential in terms of non-volatility, fast operation, virtually infinite endurance, scalability, and compatibility with complementary metal-oxide-semiconductor (CMOS) integrated circuits as well as their process and circuits. Today, high-volume manufacturing of spin-transfer torque magnetoresistive random access memory based on MTJ has been initiated for embedded memory applications in CMOS logic. Whether MTJ is scalable along with the advancement of CMOS technology is critical for the technology's future. Here, we review the scaling of MTJ technology, from in-plane anisotropy MTJs to perpendicular interfacial- or shape-anisotropy MTJs. We also discuss challenges and prospects in the future 1X- and X-nm era.

Impact of Series-Connected Ferroelectric Capacitor in HfO₂-Based Ferroelectric Field-Effect Transistors for Memory Application

In this work, we demonstrated a HfO2-based ferroelectric field-effect transistor (FeFET) in series with a HfAlO ferroelectric capacitor for memory application and further investigated the impact of the ferroelectric capacitor with different thicknesses and areas. It was revealed that the memory window of the FeFET has a significant correlation with the ferroelectric capacitor from the transfer curves of the transistor after the series connection. By decreasing the thickness and area of the ferroelectric capacitor, the memory window of the FeFET was improved, which could be verified through the TCAD simulation tool and capacitance matching model. With the series-connected ferroelectric capacitor, in addition to optimizing the characteristics of ferroelectric memory, we can effectively avoid the interface-caused undesirable effects in conventional ferroelectric memory during film stacking. These results provide a solution for future low-power embedded memory application.

Vacancy-modulated self-rectifying characteristics of NiOx/Al2O3-based nanoscale ReRAM devices

A vacancy-modulated self-rectifying resistive random access memory (ReRAM) with a Ti/NiOx/Al2O3/Pt structure is proposed in this study. Here, NiOx is used as a resistive switching layer, and Al2O3 is used as a tunnel barrier layer for producing self-rectifying behavior. The tunnel barrier thickness in the NiOx/Al2O3 interfacial region can be increased or decreased according to the movement of oxygen vacancies in the NiOx layer under positive or negative voltages, respectively, thereby leading to self-rectifying resistive switching behavior. As a result, the NiOx/Al2O3-based self-rectifying ReRAM exhibits a low operation current of ∼3 × 10−7 A, large ON/OFF ratio of ∼6 × 103, high rectification ratio of ∼5 × 102, long retention of 105 s, and forming-free and self-compliance characteristics, meeting the next generation ReRAM requirements. The Ti/NiOx/Al2O3/Pt-based self-rectifying structures can pave the way to develop high-density embedded memory applications in the future.

Vulnerabilities and Reliability of ReRAM Based PUFs and Memory Logic

Resistive Random-Access Memory (ReRAM) devices have caught significant research attention as scalable nonvolatile memory technology for high-density data storage in 3-D crossbar architectures. ReRAM devices can switch with low programming voltages (<±1 V) at fast time-scales (≍10–100 ns) that make them an attractive option for not only off-chip data storage but also for on-chip embedded memory applications. ReRAM devices have also been explored for applications as reconfigurable switches in field programmable gate arrays (FPGAs). The random variabilities in the switching performance of ReRAM has been exploited to design Physically Unclonable Function (PUF) for hardware authentication, trust, and security. However, intrinsic vulnerabilities in ReRAM devices and its implications are not well-understood. Therefore, there is an urgent need to understand these so that the ReRAM-based circuits can be made robust against such attacks. This paper discusses our research on understanding the vulnerabilities in ReRAM through experimental studies and its implications on ReRAM based PUF operations. The Process, Voltage, Temperature (PVT) variabilities in ReRAM is experimentally studied and modeled. Some other ReRAM specific vulnerabilities, such as insertion of parasitic capacitances and Trojans by adversaries and its impact on ReRAM switching behavior is discussed. Based on experimental studies, models are created to capture these behaviors in ReRAM. Using these models, a 1 KB array of ReRAM devices in a crossbar architecture and its behavior is simulated. The challenge–response pairs of these ReRAM-based arrays were studied under ideal Trojan free conditions as well as with vulnerabilities models of ReRAM. Potential solutions are then proposed to make the PUF architecture and ReRAM devices more resistant to these vulnerabilities.

Modeling of a Magnetic Tunnel Junction for a Multilevel STT-MRAM Cell

In the recent past, spin-transfer torque (STT) magnetic random access memories (MRAMs) have gained stupendous research interest with a potential to provide a solution for the on-chip memory applications. The prevailing single-level cell STT-MRAMs pose significant challenges due to scaling issues, making them unviable for the low-power and high-density embedded memory applications. This paper describes a pathway to design low-cost-per-bit, energy-efficient, and high-density multilevel cell (MLC) STT-MRAMs. This paper presents a model for magnetic tunnel junction (MTJ) devices based on in-plane magnetic anisotropy (IMA) and perpendicular magnetic anisotropy (PMA) using Verilog-A and elemental SPICE simulation framework. These MTJ devices are connected in series or parallel configuration to carry out a comparative performance analysis of series-MLC (sMLC) or parallel-MLC (pMLC) STT-MRAMs. The proposed model is validated using experimental results of IMA- and PMA-based sMLC and pMLC configurations, and the simulation results reveal a close agreement. The PMA-based pMLC configuration offers ultralow-voltage operation, least tunnel magnetoresistance degradations, and distinct presentation of resistance states, making it suitable for embedded memory applications.

Area and Energy Efficient Series Multilevel Cell STT-MRAMs for Optimized Read–Write Operations

With the inception of perpendicular magnetic anisotropy-based magnetic tunnel junction (PMTJ) devices, spin-transfer torque (STT) magnetic random access memory (MRAM) is considered as a promising candidate for low power high-density embedded memory applications. However, the single-level cell STT-MRAM did not create much impact due to its energy/area inefficiency, higher cost per bit, and unoptimized read/write operations in sub-50 nm regime. In this paper, a series multilevel cell (sMLC) STT-MRAM is proposed that offers higher array density with reliable and energy efficient read–write operations with minimum error rates at the lower supply voltage. A high-k dielectric metal gate-based gate-all-around vertical silicon nanowire is used to drive the sMLC. A unified model based on Verilog-A and HSPICE is employed to imitate the PMTJ device. The results of 2 bit sMLC designs demonstrate switching error probability much below $10^{-9}$ , and average write energy <2 pJ at the pulsewidth of 20 ns with a footprint area of 2F2 per bit (F is the feature size).

Parallel Multilevel Cell STT-MRAMs for Optimized Area Energy and Read–Write Operations

Spin-transfer torque (STT) magnetic random access memory (MRAM) is considered as a promising candidate for the next generation embedded memory applications. The advent of a perpendicular magnetic anisotropy-based magnetic tunnel junction (PMTJ) device has made the STT-MRAM viable for low-power high-density on-chip memory architectures. However, intense research efforts are still required to optimize the single-level cell and multilevel cell (MLC) STT-MRAMs in terms of area, energy, and read–write operations at ultralow power supply voltages. In this paper, a parallel MLC (pMLC) STT-MRAM (20–50 nm) is proposed to provide smaller footprint area, energy efficient, and optimized read–write operations with very low failure probabilities at the supply voltage of 1 V. These designs utilize high- ${k}$ gate dielectric gate-all-around silicon nanowire-based vertical NMOS transistor as a switching device. The PMTJ device is modeled using Verilog-A. The HSPICE simulation results affirm the suitability of pMLC designs, e.g., 3-bit pMLC design exhibits, switching error probability much less than 10−9, and average write energy of <2 pJ with minimum cell-area at the pulsewidth of 10 ns.

Self-Rectifying and Forming-Free Resistive-Switching Device for Embedded Memory Application

The self-rectifying resistive-switching (RS) device is one of the most promising solutions to overcome the sneaking current issue in a 3D vertical crossbar array. In this letter, we report a CMOS-compatible, forming-free, self-rectifying resistive random access memory device with high uniformity and low operation voltage ( 109) characteristics. After introducing a 3-nm HfO2 thin film between Pd and WOx layer, Schottky contact of Pd/HfO2 was formed, which resulted in rectifying property. The HfO2 layer also served as an oxygen reservoir for RS in WOx layer. This novel memory device with excellent performance is a promising candidate for future high density embedded memory application.

A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters

The band-modulation and sharp-switching mechanisms in Z2-FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed. The Z2-FET is suitable for embedded memory applications.

A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak Path

In this paper, we have demonstrated an oxygen-vacancy-based bipolar RRAM on a pure logic 14-nm-node HKMG FinFET platform. A unit cell of the memory consists of a control transistor (FinFET) and a storage transistor (a second FinFET). The later performs as a bipolar RRAM. This unit cell can be integrated in an AND-type memory array. The memory cell has an ON/OFF ratio equal to 200 and 400 for the n-type and p-type FinFET RRAMs, respectively, endurance larger than 400 and 1000 times for n- and p-type devices, respectively, and the retention test for over 1 month under 125 °C temperature environment. To analyze the array performance of the AND-type FinFET RRAM at the circuit level, we have further discussed the issues of the sneak path and disturbance, in which an active-fin isolation of FinFET in an AND-type array has been suggested to minimize the leakage current induced by sneak paths. The results have shown a large window with up to 103 ON/OFF ratio, 30% standby power reduction, and 90% active power reduction with reference to the conventional AND-type array. As a result, the bipolar FinFET RRAM exhibits great potential for the embedded memory applications, in particular it can be extended to 28-nm HKMG and the FinFET platform beyond 14-nm technology node, to fill the Moore’s gap between the high-performance logic and the embedded memory.

Combination of volatile and non-volatile functions in a single memory cell and its scalability

A single memory cell which combines volatile memory and non-volatile memory functions has been demonstrated with an independent asymmetric dual-gate structure. Owing to the second gate whose dielectric is composed of oxide/nitride/oxide layers, floating body effect was observed even on a fully depleted silicon-on-insulator device and the non-volatile memory function was measured. In addition, read retention characteristics of the volatile memory function depending on the non-volatile memory state were evaluated and analyzed. Further scalability in body thickness was also verified through simulation studies. These results indicate that the proposed device is a promising candidate for high-density embedded memory applications.

Charge Trapping Analysis of Metal/Al2O3/SiO2/Si, Gate Stack for Emerging Embedded Memories

For Al2O3 charge trapping analysis, Metal/Al2O3/SiO2/Si (MAOS) structures are fabricated from atomic layer deposition and plasma enhanced chemical vapor deposition-based Al2O3 and SiO2 thin films, respectively. The fabricated MAOS devices showed high memory window of ~7.81V@16V sweep voltage and leakage current density of ${\sim } 3.88{\times }10^{{-6}}\text{A}$ /cm $^{{2}}$ @−1V. The charge trapping and decay mechanism are investigated with the variation of alumina thickness by Kelvin probe force microscopy (KPFM). It reveals that vertical charge decay is a dominant phenomenon of charge loss for Al2O3 in contrast to lateral charge spreading. Constant current stress (CCS) measurements mark the location of charge trap centroid at ~10.30 nm from metal/Al2O3 interface attributes that bulk traps present close to the Al2O3/SiO2 interface are dominant charge trap centres. In addition, a simple method is proposed to estimate the trap density using KPFM and CCS method at room temperature. Furthermore, there is ~28% exponential decay in high state capacitance observed after $10^{{4}}$ s in capacitance-time analysis at room temperature. This material engineering of charge traps will improve the performance and functionality of bilayer Al2O3/SiO2 structure for embedded memory applications.

Influence of the Reference Layer Composition on the Back-End-of-Line Compatibility of Co/Ni-Based Perpendicular Magnetic Tunnel Junction Stacks

Spin-transfer torque magnetic random access memory (STT-MRAM) is currently explored to challenge the dynamic random access memory and embedded memory applications. Perpendicular magnetic tunnel junction (p-MTJ) stacks used in the STT-MRAM must be compatible with CMOS back-end-of-line processing, such as high perpendicular magnetic anisotropy, high tunnel magnetoresistance (TMR), and intact resistance area (RA) product at temperatures, as high as 400°C. In this paper, we deposited a bottom-pinned Co/Ni-based p-MTJ stack with a trilayered Co/spacer/CoFeB as a reference layer and a CoFeB film as the storage layer. By replacing the standard Ta spacer material with CoFeBTa, the thickness of the spacer layer can be increased from 4 to 8 Å without TMR and RA penalty, which is beneficial to process controllability. Moreover, the TMR increases for an 8 Å CoFeB polarizer from 125% to 145% for a similar RA product after a 300°C 30 min anneal. In addition, the thermal budget of the p-MTJ stack containing a CoFeBTa spacer was improved. The p-MTJ stack with a 12 Å CoFeBTa reference layer spacer can even withstand annealing at 400°C for 90 min and can retain a TMR value of 100% at RA 10 Ω · μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , while TMR dropped below 40% for the p-MTJ stack containing a pure Ta spacer layer.