Embedded Image Processing Research Articles

Design and Testing of an On-Line Omnidirectional Inspection and Sorting System for Soybean Seeds

Abstract. At present, the manual grading of soybean seeds is both time consuming and laborious, and detecting the full-surface information of soybean seeds using an existing automatic sorting machine is difficult. To solve this problem, an on-line omnidirectional inspection and sorting system for soybean seeds was developed using embedded image processing technology. According to the principles employed by the system, the surface friction properties and full-surface information such as the shape, texture and color of soybean seeds were adopted in the study. Soybean seeds were inspected and sorted using their full surface information in combination with the embedded image processing technology. Split, worm-eaten, gray-spotted, slightly cracked, moldy and normal soybeans were used to test the system. According to the test results, the optimum design parameters of the preliminary sorting device based on the friction properties were a tilting angle of 12° and a linear velocity of 0.4 m/s. Furthermore, the optimum design parameters of the directional integrated device were a tilting angle of 19° and a linear velocity of 0.45 m/s. The sorting speed was 400 soybeans per minute with 8-channel parallel transmission. The average sorting accuracies were 99.4% for split soybeans, 98.5% for worm-eaten soybeans, 98.5% for gray-spotted soybeans, 97.7% for slightly cracked soybeans, 98.6% for moldy soybeans, and 98.9% for normal soybeans. The overall results suggest that the system can potentially meet the needs of the rapid inspection and automatic sorting of soybean seeds and provide references for research on the alternating rotational motion of granules and on-line collection of full-surface information. Keywords: Embedded image processing technology, Full surface, Granules, Inspection, On-line, Sorting, Soybean seeds.

Automatic Wheat Leaf Rust Detection and Grading Diagnosis via Embedded Image Processing System

Wheat leaf rust is one of the major fungal diseases that makes severe drop in the wheat production. With the desire for rapid and accurate identification of disease, real-time access to the degree of that and timely measures, a wheat leaf diseases detection system based on embedded image recognition technology is designed. The system adopted the ARM9 processor with the embedded Linux platform as the main body, and the program is developed in the Qt integrated environment. At first, the captured clear disease picture of wheat leaf rust was transformed into G single channel gray image of RGB model. Second, based on exploration Sobel operator method, vertical edges detection were implemented on the gray image, eliminate the background of image and extracts binary feature point set of disease spot. Third, the noisy points in the point set is further filtered out by flood filling algorithm. Finally, the area ratio of disease spots and leaf is calculated to get the precise diagnosis of disease level. It has been verified that the recognition rate reaches 96.2% and accuracy rated reaches 92.3% with the method of image processing, which is approximately equal to the result of human vision. This system can be used as agricultural robot to inspect in the field, realizing the intelligentization in detection, identification, diagnosis and classification of crop disease.

HNCP: A many-core microprocessor ASIC approach dedicated to embedded image processing applications

Highly regular many-core architectures tend to be more and more popular as they are suitable for inherently highly parallelizable applications such as most of the image and video processing domain. In this article, we present a novel architecture for many-core microprocessor ASIC dedicated to embedded video and image processing applications. We propose a flexible many-core approach with two architectures one implemented in CMOS 65 nm technology containing 16 open-source tiles and the other implemented in CMOS FD-SOI 28 nm technology containing 64 open-source tiles. Each tile of these architectures can choose its communication links depending on the most relevant overall parallelism scheme for a targeted application. Both chips are fully functional in simulation. The layouts are presented with frequency, area and power consumption results. Various case studies are presented to illustrate the proposed flexible many-core architectures and enable to focus on architecture exploration, instantiated scheme of parallelization and timing performance.

Design and Implementation of Image-Pyramid

This paper presents a System-On-a-chip for embedded image processing applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

A single-cycle parallel multi-slice connected components analysis hardware architecture

In this paper, a memory-efficient architecture for single-pass connected components analysis suited for high-throughput embedded image processing systems is proposed which achieves a speedup by partitioning the image into slices. Although global data dependencies of image segments spanning several image slices exist, a temporal and spatial local algorithm is proposed, together with a suited FPGA hardware architecture processing pixel data at low latency. The low latency of the proposed architecture allows reuse of labels associated with the image objects. This reduces the amount of memory by a factor of more than 5 in the considered implementations which is a significant contribution since memory is a critical resource in embedded image processing on FPGAs. Therefore, a significantly higher bandwidth of pixel data can be processed with this architecture compared to the state-of-the-art architectures using the same amount of hardware resources.

Real-time hardware\u2013software embedded vision system for ITS smart camera implemented in Zynq SoC

The article demonstrates the usefulness of heterogeneous System on Chip (SoC) devices in smart cameras used in intelligent transportation systems (ITS). In a compact, energy efficient system the following exemplary algorithms were implemented: vehicle queue length estimation, vehicle detection, vehicle counting and speed estimation (using multiple virtual detection lines), as well as vehicle type (local binary features and SVM classifier) and colour (k-means classifier and YCbCr colourspace analysis) recognition. The solution exploits the hardware–software architecture, i.e. the combination of reconfigurable resources and the efficient ARM processor. Most of the modules were implemented in hardware, using Verilog HDL, taking full advantage of the possible parallelization and pipeline, which allowed to obtain real-time image processing. The ARM processor is responsible for executing some parts of the algorithm, i.e. high-level image processing and analysis, as well as for communication with the external systems (e.g. traffic lights controllers). The demonstrated results indicate that modern SoC systems are a very interesting platform for advanced ITS systems and other advanced embedded image processing, analysis and recognition applications.

Image Processing Method for Embedded Optical Peanut Sorting

Sorting of finished products or agriculture food has different method for ultra high speed quality inspection. Optical sorting is one of the important applications of image processing used in industries to replace manual method to verify quality of finished products or row food. Most of the systems use the computer as main processing device that perform image processing algorithms on it, such kind of system having limitations like higher cost, bigger size and large Initial boot-up time. This type of design cannot be implemented for ultra fast, higher capacity and smaller in size agricultural products like nuts, grains and pulses. Standalone image processing have embedded image processing platform that can able to overcome the limitation of computer based systems at certain level. As peanuts (Arachis hypogeal) come from farm, they are mixed with foreign material like rocks, moisture contended soil particles and outer shells of raw peanuts and they must be separated with high level of accuracy and precision. here discussed the multi channel peanut sorting algorithm that apply on raspberry pi ARM platform for peanut quality segregation by sort out foreign material as well as defective peanut like aflatoxin contaminants and fungi allergies contents from the required quality good peanuts. In paper we discuss about implementation of such a system by using conveyor belt method and image processing algorithm. Algorithm takes consider the color and size of peanut for optical peanut sorting process.

ARC 2014

The embedded image processing systems like smartphones and digital cameras have tight limits on storage, computation power, network connectivity, and battery usage. These limitations make it important to ensure efficient image coding. In the article, we present a novel heap-based priority queue structure employed by an Adaptive Scanning of Wavelet Data scheme (ASWD) targeting an embedded platform. ASWD is a context modeling block implemented via priority queues in a wavelet-based image coder to reorganize the wavelet coefficients into locally stationary sequences. The architecture we propose exploits efficient use of FPGA’s on-chip dual-port memories in an adaptive manner. Innovations of index-aware system linked to each element in the queue makes the location of queue element traceable in the heap as per the requirements of the ASWD algorithm. Moreover, use of 4-port memories along with intelligent data concatenation of queue elements yielded in a cost effective enhanced memory access. The memory ports are adaptively assigned to different units during different processing phases in a manner to optimally take advantage of memory access required by that phase. The architectural innovations can also be exploited in other applications that require efficient hardware implementations of generic priority queue or classical sorting applications which sort into the index. We designed and validated the hardware on an Altera’s Stratix IV FPGA as an IP accelerator in a Nios II processor based System on Chip. We show that our architecture at 150MHz can provide 45X speedup compared to an embedded ARM Cortex-A9 processor at 666MHz targeting the throughput of 10MB/s.

Improvements in adhesion force and smart embedded programming of wall inspection robot

An intelligent wall inspection robot with sensors and embedded image processing system was studied based on a combination of vacuum-suction technique and four-wheel drive method to achieve good balance between strong adhesion force and high mobility. To obtain more stable adhesion forces, the height and weight of the robot body were reduced by analyzing the relation between the principal physical input variables and the output performance, such as the suction force and momentum. An object detection system on the embedded programming system for automatic wall inspection was also developed. For successful detection, threshold methods were compared and an improved Otsu method was adopted so that it could handle both unimodal and bimodal distributions well. Through the improvement, the robot could move upward a wall at a speed of 5.3 m/min and carry a payload of at least 7.5 kg in addition to its self-weight and it could also intelligently detect and classify small objects on the wall.

Evolutionary design of multiplierless lifting-based 2D DWT filters for low-resolution image processing

The most difficult challenge in developing a high-efficiency embedded image processing system relates to how to execute complicated Digital Signal Processing (DSP) algorithm with embedded processor, especially when processing high-resolution images. A whole system may start to run very slowly because of the large volumes of data being processed and the complexity of the algorithm, rendering it unable to achieve real-time processing. Executing motion detection in low-resolution image was already proved to be able to reduce the loading of data manipulation and to be able to help filter out noise and fake motion. However, smoothing filter pointed out in the work will affect the quality of image. Although the LL-band signal of a 2D Discrete Wavelet Transform (DWT) domain can retain the main part of the energy and information of the original image, a complex algorithm is more suitable for the application of a low-pass filter. Symmetric Mask-based DWT (SMDWT) has the advantage of reduced complexity, regular signal coding, and independent subband coding processing. In this paper, we use a Particle Swarm Optimization (PSO) approach to automatically evolve the multiplierless 2D SMDWT filters hardware architecture. The architecture employs only shift-and-addition operations to replace the complex floating-point multiplication and division operations. It can use shift-and-add based SMDWT filter to decompose a low-resolution image and do real-time image processing system design with low-resolution image processing technique.

Implementation of Spatial Domain Homomorphic Filtering on Embedded Mobile Devices

This paper describes the analysis of the Homomorphic filtering algorithm, the equivalency between the frequency and spatial-domain methods and the implementation of low-pass and high-pass spatial domain Homomorphic filter in low power embedded devices. It is shown that the Homomorphic filter in the spatial domain combines the sensitivity of local/neighbourhood operations in addition to Laplacian-type edge enhancement, averaging operation of illumination intensity estimation, in addition to dynamic range compression associated with frequency-domain Homomorphic filters. A qualitative and quantitative comparison of the image results confirms the validity of the theoretical approach and advantages for digital hardware implementation. The developed filters are implemented on a Java-enabled mobile phone and form a low cost embedded image processing enhancement system. http://dx.doi.org/10.4314/njt.v34i2.19

Embedded Image Processing Systems for Automatic Recognition of Cracks using UAVs

Aiming at the use of Unmanned Aerial Vehicle (UAV) in civil construction for autonomous inspection of building pathologies, this paper discusses some implementation alternatives of image processing algorithms for the detection of cracks in building facades. These algorithms should run in an embedded computing platform installed on UAVs. Two image processing algorithms for crack detection and classification were selected and different embedded system implementations were evaluated. A version of the algorithms running in a Matlab environment on a desktop computer, which can be used in an approach on which the image processing is done in the ground and the UAV is only applied for image acquisition, was used as a baseline for the comparison. This baseline is compared with implementations running on an embedded processor (a Raspberry PI, running a distribution of Debian ARM operating system) and with implementations on a Xilinx FPGA-board installed in the UAV. Different scenarios for the execution of a inspection task of building facades were defined and the obtained results are presented in the paper.

Study on the Technology of Digital Image Processing

The paper aims to study a design and technique of the image processing based on the architecture of embedded system. Aimed at the own characteristic of embedded system, designing a platform been endowed with more operating functions of embedded image processing with versatility. The author adopts the method of the embedded system design based on the basic functions and characteristic of image processing system, summarizing and comparing of the characteristic and new developments of the EOS for the ARM processor, and finally chooses the embedded Linux for the operating system of our platform, also transplant it in the hardware platform. Aimed at the characteristic of Linux device architecture, the author introduces how to develop the image capture and display, memory the data of an image, the programming method of that. Some base arithmetic of image processing, such as image smooth, sharpen, edge detect and so on, and the graphics user interface are developed on the platform with using the Mini GUI, according to the intercommunion between the human and the platform. At last, some key program's code is given.

Field-Programmable System-on-Chip for Localization of UGVs in an Indoor iSpace

The ability to perform accurate localization is a fundamental requirement of the navigation systems intended to guide unmanned ground vehicles in a given environment. Currently, the use of vision-based systems is a very suitable alternative for some indoor applications. This paper presents a novel distributed FPGA-based embedded image processing system for accurate and fast simultaneous estimation of the position and orientation of remotely controlled vehicles in indoor spaces. It is based on a network of distributed image processing nodes, which minimize the amount of data to be transmitted through communication networks and hence allow dynamic response to be improved, providing a simple, flexible, low-cost, and very efficient solution. The proposed system works properly under variable or nonhomogeneous illumination conditions, which simplifies the deployment. Experimental results on a real scenario are presented and discussed. They demonstrate that the system clearly outperforms the existing solutions of similar complexity. Only much more complex and expensive systems achieve similar performance.

Embedded Realization of a Adaptive Threshold Edge Detection Base on Canny Operator

Edge detection that is an important means to realize image segmentation has important application significance in image processing, industrial detection, artificial intelligence and the target recognition field. As the demand for real-time and rapidity in image processing, the embedded image processing technology has been widely applied. But the realization of real-time edge detection for image requires a large amount of data processing, limited system resources of embedded system is the main reason of the embedded image processing technology development. In order to shorten time embedded systems edge detection processing large amounts of data, based on adaptive threshold Canny algorithm, this paper as the FPGA data processing DSP chips and made a FPGA + DSP hardware architecture, effectively improve the system real-time, get a good edge detection results.

Implementation of the Fast Median Filtering Algorithm Based on FPGA

Real-time image processing has been a difficult problem in embedded image processing system. The traditional MCU could not meet the real-time demand when large volume of data awaited to be proceed. FPGA is an effective driver to achieve real-time parallel processing of data. The implementation rationale and the design of module have been given in this article; and the Hard Software has been truly achieved. At the end of the article, the simulation waveform graph has been obtained by processing functional simulation on algorithm module by using Modelsim software; and the simulation result shows that this design is able to proper functioning and has good application prospects.

Fast hardware architecture for grey‐level image morphology with flat structuring elements

Mathematical morphology operators, applied in many vision-based applications, are characterised by repetitive operations on large amounts of data. Thus, novel design strategies for efficient hardware implementations are necessary. This study presents and evaluates a real-time hardware architecture for grey-level image erosion and dilation that processes data in streams for an efficient utilisation of memory bandwidth and low on-chip memory requirements. A low-complexity and highly modular architecture is proposed based on a sequence of pipeline stages, and parallel processing in order to minimise computational times. The design is intended to be used as a hardware accelerator in real-time embedded image processing applications requiring moderate-size and non-rectangular flat structuring elements on high-resolution images. The architecture is prototyped on a field programmable gate array device operating at a clock frequency of 260 MHz on a Virtex-6 device which compares favourably to the well-known delay-line-based hardware architectures in terms of complexity, memory requirements and execution time. A 7 × 7 dilation/erosion operator on 1280 × 1024 grey-level image can be performed at a rate of 95 frames per second, but the architecture can be scaled up if required.

Navigation of Mobile Devices based on Embedded Image Processing with Support of GPS Systems and Sensors

A recent development in system-on-chip processors provides possibilities of integration performancedemanding tasks, which can be performed only with the help of superior range of computers before. The article introduces advanced control system with embedded image processing to improving GPS localization of autonomous mobile devices in real environment. The main control system is based on ARM (SoC.) architecture integrated in Raspberry PI development board. Presented control systems can handle real-time video capturing, power-efficient image processing operation for example (thresholding, binarization, motion detection, ...etc.) and streaming results images as video. GPS precision can provide only 3 meters precision together with WAAS (Egnos) satellite. Our solution uses GPS solution and embedded image processing to detect border of roads or sidewalks. Our algorithm detects road or sidewalk universally without detection of white line in roadside, because pathways and some roads cannot provide this feature. Control system can be used for small autonomous mobile devices for example parts transport in industrial park of heavy industries, where are long distances between production halls.

Research of Embedded Image Processing Based on ARM11 and SQLite

According to the fact that the embedded system is not efficient enough to access and manipulate image data, this paper put forward a research program of image JPEG compression algorithm and being stored in a combination based on the ARM11 and SQLite embedded database image processing system. Comparative Researches on the system without data prove that the program can make the embedded systems more reasonable to store image data and realize the localized efficient management of the image data, which has certain practical value.

Research and Realization of Hardware Back-Propagation Neural Network Based on FPGA

In order to meet the requirements of real-time and embedded of industrial field, a reconfigurable Back-Propagation neural network based on FPGA has been implemented on Xilinx's Spartan-3E (XC3S250E) chip which has 250000 gate. First the optimal network structure and weights were gotten by a variable structure of BP neural network algorithm. Then an improved hardware approaching method of excitation function was put forward, and the maximum error was 1.58% by simulation and comparative analysis on the error. Finally hardware co-imitation and timing simulation was token based on a reasonable choice of data accuracy, and then the hardware BP neural network algorithm was been downloaded and implemented on FPGA. This method has better accuracy and speed, it is an effective method of BP neural network modeling based on hardware, and lays the foundation for the hardware realization of other neural network and embedded image processing.