Embedded Data Compression Research Articles

History of IBM Z Mainframe Processors

IBM Z is both the oldest and among the most modern of computing platforms. Launched as S/360 in 1964, the mainframe became synonymous with large-scale computing for business and remains the workhorse of enterprise computing for businesses worldwide. Most of the world's largest banks, insurers, retailers, airlines, and enterprises from many other industries have IBM Z at the center of their IT infrastructure. This article presents an overview of the evolution of the IBM Z microprocessors over the past six generations. The article discusses some of the underlying workload characteristics and how these have influenced the microarchitecture enhancements driving the performance and capacity improvements. The article then describes how the focus shifted over time from speeds and feeds to new features, functions, and accelerators, and presents some examples on improved availability, enhanced security and cryptography, and embedded data compression acceleration.

Hardware/Software Co-Design and VLSI Implementation for the Intelligent Surveillance System

In this paper, we present a hardware design for the intelligent surveillance system. We have developed a complete system-level solution on algorithm level, and then algorithm has been implemented in very-large-scale integration (VLSI). The behavior of the moving objects is evaluated using adaptive search method. We propose the method to track the moving people in successive frames by object boundary box and velocity without color cues or appearance model. Even though people are interacting with each other or the occlusion is occurring due to other foreground objects, still the proposed algorithm can perform well in such situations. Furthermore, we consider the distance of object from camera for an adaptive search range to deal with the people movement issue. Although foreground is similar to the background in some conditions, the proposed algorithm can still detect the object well. We also propose an embedded data compression technique, which does not only reduce the computational complexity, but also achieves high compression rate. The overall system is developed in a platform-based system-on-a-programmable-chip for demonstration of result. In VLSI implementation results, the logical gate count is 139.890 K and the throughput of foreground detection is 6403 K pixels/s.

Image data compression with hierarchical pixel averaging and fully adaptive prediction error coder

The fully adaptive prediction error coder (FAPEC) is an entropy coder that typically offers better results than the adaptive Rice compressor. It uses basic preprocessing stages such as delta preprocessing, but it can also be combined with a discrete wavelet transform. We describe a new algorithm called hierarchical pixel averaging (HPA). It divides an image into blocks of 16 x 16 pixels, which are subsequently divided into smaller blocks, up to the basic level where one block corresponds to one pixel. Average pixel values are determined for each level from which differential coefficients are extracted. HPA allows the introduction of controlled losses with several quality levels, also allowing to progressively decompress a given image from lower to higher quality. It achieves better resolution in sharp image edges when compared to other lossy algorithms. HPA is based on simple arithmetic operations, allowing a very simple (thus quick) implementation. It does not use any floating-point operations, which is an interesting feature for satellite or embedded data compression. We present a first implementation of HPA and the results obtained on a variety of images, both for the lossless and lossy cases with different quality levels. Our results indicate that HPA + FAPEC offer a performance comparable to that of CCSDS 122.0. (C) 2015 Society of Photo-Optical Instrumentation Engineers (SPIE)

Data Compression for Image Sensor Arrays Using a 15-bit Two-Step Sigma–Delta ADC

This paper reports a readout integrated circuit with embedded data compression function for image sensors. Data compression is realized by adding a comparator in a two-step incremental sigma-delta analog-to-digital converter (ADC) with a fully floating double sampling integrator. The output difference between two adjacent pixels is compared with a predefined threshold using the comparator to detect redundant pixels. Once the difference is smaller than the threshold, indicating a redundant pixel, the AD conversion is omitted and the redundant information is stored using a Boolean variable. Thus, the conversion speed can be improved and the storage space is saved. An ADC test vehicle with an \(8 \times 8\) array has been fabricated using 0.5-\(\mu \) m CMOS technology. Measurement results show that the frame rate of the image sensor is 10%-236% faster than conventional ADC, and data compression ratios between 1 and 5 are achieved for images with different redundancy. The advantages of this on-chip image compression are the embedded and simple circuits, considerable speed and storage space improvement, and low power consumption. The preliminary results have demonstrated the feasibility and the effectiveness of the proposed compression method.