A hybrid-excited flux-switching machine for fault short-circuit current limitation in embedded DC alternator applications

A valve based on electro-rheological fluid (ERF) is introduced for its possibility of being a very small volume and power consuming. A novel linking method of these multiple valves and their control strategy contribute to the accomplishment of saving the numbers of power modules and the system power consuming, eventually the volume and weight of the system. For a N times M valves matrix, the saving numbers of power modules used for driving these valves are the difference between the product of N and M, and the plus of N and M. It provides a novel solution of shrinking system for a portable mechatronic embedded system application. A demonstration of these valves matrix on multi-line Braille displayer for blind people is shown.

Analysis and redesign of the ‘TTC’ and ‘TTH’ schedulers

This paper discusses the development of embedded controllers on a reconfigurable multiprocessor system using field programmable gate array (FPGA) technology. The system is reconfigurable in hardware and software in the sense that certain components may be reused in different applications, hence allowing rapid development of embedded control systems. Concurrent real-time operation can be achieved by utilising hardware and software modules consisting of dedicated hardware cores and real-time operating systems. For demonstration purposes, we discuss the development of a system consisting of a network-enabled master processor that handles two slave processors each controlling a mechatronic system. The user interface is implemented using an internet browser through the master processor which allows monitoring and supervisory control of the individual systems. A multi-threaded real-time operating system runs on each of the softcore processors which allows flexibility and modularity in software design whereas pre-designed hardware modules on the FPGA chip can be utilised for building comuting hardware for control applications. Experimental results are presented for illustrating how control applications can be developed and deployed using modular components and the hardware/software environment.

We investigate per-flow flit and packet worst-case delay bounds in on-chip wormhole networks. Such investigation is essential in order to provide guarantees under worst-case conditions in cost-constrained systems, as required by many hard real-time embedded applications. We first propose analysis models for flow control, link and buffer sharing. Based on these analysis models, we obtain an open-ended service analysis model capturing the combined effect of flow control, link and buffer sharing. With the service analysis model, we compute equivalent service curves for individual flows, and then derive their flit and packet delay bounds. Our experimental results verify that our analytical bounds are correct and tight.

Programming MPPAs for complex real-time embedded applications is difficult with conventional multiprogramming models, which usually treat communication and synchronization separately. Based on a programming model for massively parallel embedded computing that is reasonable and productive for software developers, we developed a scalable MPPA chip architecture that delivers tera-ops performance with very good energy efficiency in an ordinary 130-nm ASIC. This MPPA's architecture is based on the structural object programming model, which composes strictly encapsulated processing and memory objects in a structure of self-synchronizing channels. Small RISC CPUs and memories execute the objects.

Programming MPPAs for complex real-time embedded applications is difficult with conventional multiprogramming models, which usually treat communication and synchronization separately. To ease this ...

An approach to the design of RISC core processors for VLSI embedded systems