Electrostatic Discharge Voltage Research Articles

Design of a LVTSCR triggered SCR device for low voltage ESD protection

In this paper, a novel silicon-controlled rectifier (SCR) electrostatic discharge (ESD) protection device, called low voltage triggered SCR (LVTSCR) triggered SCR (LVTSCRTSCR), is proposed for 3.3 V I/O protection applications in 0.18 μm CMOS technology. One side of the device is the traditional LVTSCR structure, and other side is the traditional SCR structure. The two structures are connected by a floating P+ diffusion layer. The working principle of LVTSCRTSCR was verified by the TCAD simulation results and TLP test results. The test results show that the triggering voltage of LVTSCRTSCR is determined by the traditional LVTSCR, with a value of 9.850 V. The holding voltage of the device can be effectively improved by increasing the size of the floating diffusion layer D4. When D4 = 6 μm, the holding voltage can be 4.491 V, suitable for 3.3 V I/O.

Characterization of ESD-induced electromigration on CMOS metallization in on-chip ESD protection circuit

Electrostatic discharge (ESD) and electromigration are critical issues that significantly impact the reliability of ICs. While both of these phenomena have been studied independently, the combination of the two, ESD-induced electromigration, has received less attention, potentially compromising IC reliability. This work analyzes various types of metal with different lengths, widths, and angles commonly used in ESD protection circuits in the CMOS process. The objective is to observe their behavior under continuous ESD zapping. The ESD-induced electromigration of metallization in the CMOS process has been analyzed, and metal sensitivity to system-level ESD events has also been identified. It is also analyzed from the perspective of energy that the ESD energy that metal can withstand will decrease as the ESD voltage increases, which will be even more detrimental to the ESD reliability of ICs. The findings from this study aim to provide valuable insights for designing metal lines in ICs to enhance ESD protection.

MOSs-String-Triggered Silicon-Controlled Rectifier (MTSCR) ESD Protection Device for 1.8 V Application

In this work, a new low voltage-triggered silicon-controlled rectifier named MTSCR is realized in a 65 nm CMOS process for low voltage-integrated circuits electrostatic discharge (ESD) protections. The MTSCR incorporates an external NMOSs-string, which drives the internal NMOS (INMOS) of MTSCR to turn on, and then the INMOS drive SCR structure to turn on. Compared with the existing low trigger voltage (Vt1) ESD component named diodes-string-triggered SCR (DTSCR), the MTSCR can realize the same low Vt1 characteristic but less area penalty of ~44.3% reduction. The results of the transmission line pulsing (TLP) measurement shows that the MTSCR possesses above 2.42 V holding voltage (Vh) and a low Vt1 of ~5.03 V, making it very suitable for the ESD protections for 1.8 V input/output (I/O) ports in CMOS technologies.

An On-Chip ESD Sensor for Use in Advanced Packaging

Electrostatic discharge (ESD) failure results in about 35% of integrated circuit (IC) field return and causes several billion-dollar losses to the semiconductor industry per year. Most modern ICs include on-chip ESD protection circuitry which comes at the cost of I/O performance. Static charge accumulation during transport and handling may exceed the limits of this ESD protection and cause damage to the ICs. Modern advanced packaging technologies are not amenable to rework if one or more components are ESD compromised. An on-chip ESD sensor is useful in identifying and preventing the assembly of ESD compromised dielets in any advanced packaging technology. Two approaches for on-chip ESD sensor that can be employed on any die, following the ground rules within that technology are presented. Both approaches are designed, simulated, fabricated, and experimentally characterized using GlobalFoundries 22-nm fully depleted silicon-on-insulator (FDSOI) technology. While determining ESD voltage using sensors, we encounter two events that are naturally random. First, ESD is a random event with some probability distribution function (PDF) with respect to voltage. In addition, oxide breakdown within the ESD sensors is also random with a Weibull distribution. A Bayesian method is developed for the estimation of ESD voltage PDF using sensors. Experimental testing of the sensors using an ESD gun and ESD voltage estimation from the number of sensors that broke down is presented. The estimated ESD voltage closely matches the ESD voltage that the dies were subjected to during experimental verification.

Inhalation‐Driven Vertical Flutter Triboelectric Nanogenerator with Amplified Output as a Gas‐Mask‐Integrated Self‐Powered Multifunctional System

AbstractWith the widespread use of sensors and small electronics in the Internet of Things (IoT) era, triboelectric nanogenerators (TENGs) have emerged as sustainable and renewable energy sources owing to their high efficiency, compatibility with various materials, and low cost. However, the existing TENGs exhibit a low current output and require a large mechanical input to continuously generate an enhanced current output. In this study, an inhalation‐driven vertical flutter TENG (IVF‐TENG) with an amplified current output is developed. The IVF‐TENG exhibits two types of mechanical behaviors simultaneously, generating a high‐frequency continuous electrical voltage and closed‐circuit current (ICC) output of 17 V and 1.84 μA, respectively, during inhalation, and an electrostatic discharge voltage and ICC output of 456 V and 288 mA at the beginning and end of every inspiratory cycle, respectively. As a user‐position‐indicating light, the IVF‐TENG can power 130 LEDs in series and 140 LEDs in parallel for every inhalation. The IVF‐TENG can charge a capacitor of 660 μF, with a discharge process of a few seconds, to power a commercial Bluetooth tracker and wirelessly transfer the Bluetooth signal to a smartphone. Moreover, the IVF‐TENG can detect the user's respiration state or the presence of chemical warfare agents (GB, DMMP, etc.) via output waveforms.

Simulation Study of a High Gate-to-Source ESD Robustness Power p-GaN HEMT With Self-Triggered Discharging Channel

This article proposes a novel power p-GaN high-electron-mobility transistor (HEMT) with self-triggered discharging channel to improve gate-to-source electrostatic discharge (ESD) robustness. The self-triggered discharging channel consists of a small-size self-triggered p-GaN HEMT, a current-limiting resistor R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> , and a proportional amplification resistor R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . At ESD events, the proposed power p-GaN HEMT will be self-triggered by the high transient ESD voltage, and hence the accumulated electrostatic charges at its gate will be released through the self-triggered discharging channel. This avoids the gate-to-source damage of the proposed device, thereby enhancing the gate-to-source ESD robustness. Compared with the conventional power p-GaN HEMT, simulation results show that the transmission line pulsing (TLP) current handling capability (over 6.5 kV human body model failure voltage) of the proposed device is improved by 1900% without compromising other device characteristics. In addition, the fabrication process of the proposed device is fully compatible with the traditional power p-GaN HEMT platform, and the increase of total active area is less than 0.5%. The proposed device with self-triggered discharging channel can be a good reference for the design of power p-GaN HEMT with high ESD robustness.

An electronically programmable Off-State breakdown voltage in LDMOS transistor with dual-dummy-gate for high voltage ESD protection

A simulation study of the Off-State breakdown characteristics for a dual-dummy-gate SOI-LDMOS transistor is presented. The proposed device is a modification of a bulk-LDMOS transistor with a single dummy gate and two different diffused layers in the drift region. It introduces two additional dummy gates in the drift region, apart from the gate and extended drain electrode in the conventional device. The dummy gates need to be optimally biased to maximise the breakdown (VBR) and snapback voltages. 1D model modifying the 2D Poisson's equation has been proposed to analyse the 2D phenomena arising due to the perpendicular electric field originating from the dummy gate and extended-drain voltages and optimize the two dummy-gates bias. This approach provides an analytical solution for the Off-State VBR under the depletion condition. The model is verified with the TCAD simulations. The simulation results provide an insight into the electric field, potential distributions, and carrier concentrations in the drift region that characterizes the device performance. The impact ionization and current density contours are also included. It is found that the introduction of the two dummy gates enhances the maximum achievable VBR while it eliminates the need to have two different diffused regions that necessitate additional masks. Also, the proposed device has an intrinsic structural advantage of the reduced gate to drain capacitance due to the shielding effect of dummy gates. As the performance of the proposed device is controlled externally by the applied dummy gate voltage, the VBR is user programmable as per the requirement in electrostatic discharge (ESD) protection circuits for a sub-100 V application.

Design of a cascade-MOS-triggered SCR with high holding-voltage for high-voltage ESD protection

A parallel-MOS-triggered silicon-controlled rectifier (PMTSCR) is firstly proposed and verified in a 0.25-μm Bipolar-CMOS-DMOS process, aiming to prevent the latch-up effect of SCR in the electrostatic discharge (ESD) protection. Comparing to the conventional SCR, the trigger voltage (Vt1) of the PMTSCR decreases because of the effect of PMOS embedded in the N-well, and the holding voltage (Vh) increases because of the attribution of the NMOS embedded in the P-well. By shortening the SCR current conduction path and designing a special metal connection, the modified-PMTSCR (M-PMTSCR) is obtained. The failure current of the M-PMTSCR remarkably increases from 1.8 to 4.8 A. However, M-PMTSCR exhibits a lower Vh and a higher Vt1. By further optimizing the location and connection of the embedded PMOS and NMOS, the obtained cascade-MOS-triggered SCR (CMTSCR) possesses a high Vh of 8.4 V and a strong ESD robustness of 6000 V in a small chip area. Meanwhile, the operation mechanism simulated by Sentaurus was consistent with the theoretical circuit analysis and transmission line pulse measurements. Thus the proposed CMTSCR with the good latch up immunity and temperature stability is a promising device to meet the requirements of high voltage ESD protection.

Design and analysis of a multi-finger dual-direction SCR discharging electro-static current in a gradual transition manner

In order to seek an electro-static discharge with higher failure current per unit area and latch-up immunity, a novel multi-finger dual-direction silicon controlled rectifier (DDSCR) using the 0.5 μm complementary and double-diffusion metal-oxide-semiconductor technology was proposed. The working principle of the device is analyzed by using equivalent circuit and technology computer aided design simulation. From the test result of the transmission line pulse testing system we can see that the holding voltages for the traditional dual-direction silicon controlled rectifiers with a single-finger and two-fingers are 11.34 V and 7.63 V, respectively, which is decreased as the number of fingers increases. The holding voltage of the proposed device is 12.2 V, which is higher than that of the traditional 2-finger DDSCR and suitable for communication interface high voltage electrostatic discharge (ESD) protection. Furthermore, the influence of some dimensions, fingers and total finger width on the device is discussed. The proposed device not only solves the problem of decreasing the holding voltage caused by increasing the number of fingers, but also has a slight effect on the failure current. The root cause for such holding voltage trend is their different working mechanisms. The proposed device is turning on one finger by another instead of simultaneously turning on in the multi-finger traditional devices. Therefore, the proposed ESD device owns a holding voltage similar to that of the 1-finger device.

Design of a Dual-directional Diode-triggered SCR for Low Voltage ESD Protection

A novel dual-directional diode-triggered silicon controlled rectifier (DDTSCR) for low voltage electrostatic discharge (ESD) protection was designed and realized in a 0.18-µm CMOS process. Compared to the single-directional diode-triggered SCR (SDTSCR), the DDTSCR has dual-directional ESD protection performance due to the symmetric structure, and its ESD protection efficiency per unit area is about 2 times larger than that of SDTSCR under opposite ESD stresses, while remaining the similar trigger voltage of 1.68 V and the figure of merit. The human body model robustness of the DDTSCR measured by the transmission line pulse system is up to 8000 V with an area of 1400 µm2, suitable for low voltage ESD protection requirements.

Обеспечение электромагнитной совместимости морской техники при возникновении электростатических разрядов

The paper describes the problem of electromagnetic compatibility for electrostatic discharge (ESD), which is most actual for ships where all systems are highly automated and susceptible to ESD digital technology. The results of electromagnetic compatibility tests of ship systems after their installation on the vessel allow to conclude that it is not enough to fulfill only the existing ESD immunity requirements of the Russian Maritime register of shipping which are currently confirmed by ESD tests in the laboratory. ESD methods and reasons have been analyzed. The possible accumulated potentials and parameters of currents, voltages and field strengths during discharge are presented. The existing ESD immunity standards are being considered. The scheme of the developed and certified generator of electrostatic discharges ESD – 25000 is presented. The most frequent defects under the influence of ESD are given. There have been formulated the equivalent schemes of the electric equipment housing at different lengths of grounding of the housing and the methods of connecting the cover with the housing. The results of measurements of electric field and magnetic field parameters are presented. The results of modeling and experiments are compared. The developed sensors, methods of their calibration and obtained technical characteristics are being tested. There are given the parameters and forms of ESD voltage and current, experimental data of ESD secondary effects in the EE hull and adjacent equipment, results of discharges in the ship's cable, interference in the supply network through secondary power sources. The most effective design and ESD protection methods have been analyzed

Common‐mode rejection ratio characterisation of a broadband electro‐optical differential ESD voltage probe

The concept of an isolated differential voltage measurement system is presented. The proposed probe circuit is designed for broadband measurement of electrostatic discharge (ESD) waveforms. The electro-optical conversion of the measured signal allows the system to operate in an electromagnetically polluted environment. The signal capture and signal processing stages of the system are separated. Characteristics of the system in terms of differential-mode and common-mode signal sensing are discussed. The common-mode rejection ratio (CMRR) of the system is explored in the gigahertz frequency range. Given the low cost, the system can be implemented both as a standalone probe or as a part of an integrated circuit characterisation and test environment.

Dual direction SCR with deep well structure for high voltage ESD in communication bus

In order to improve the robustness of the ESD of the dual-direction silicon-controlled rectifier, a low doping deep well PB structure is proposed instead of the traditional high doping P+ structure. The ESD stress of the dual-direction SCR devices with deep well structure is discharged from inside and the lattice temperature of the device is low to avoid premature burnout of the device. The deep well PB structure on the surface of the device increases the parasitic resistance of the device and improve the conduction uniformity of the device. As the main conduction path of the device is located in NBL, the PB structure does not have a large influence on the sustain voltage. It is verified in a 0.25 μm BCD process. With equivalent circuit and two-dimensional device simulation, the working mechanism is analyzed. According to the transmission line pulse test results and comparing with the data from traditional dual-direction SCR structure. The device’s fault current increases from 5.486 A to 8.13 A which is suitable for communication bus high voltage electrostatic discharge (ESD) protection.

Modeling and Simulation of Comprehensive Diode Behavior Under Electrostatic Discharge Stresses

Diodes are effective devices for electrostatic discharge (ESD) protection. To accurately predict ESD robustness through circuit simulation of protection architectures in integrated circuits that use diodes, an enhanced model is proposed. This model is constructed with several compact model elements to simulate all physical device behaviors under high current transient ESD conditions, namely, voltage overshoot, on-resistance variation, and thermal failure. The proposed model implements a thermal monitor, which cannot only correlate current–voltage characteristics with the self-heating effect, but accurately predicts thermal failure under different pulse width conditions. The simulation results of this comprehensive diode model benchmarked against measurements are also reported.

Different Ignition Responses of Powdery and Bulky 1,3,5-Triamino-2,4,6-Trinitrobenzene (TATB) Based Polymer-bonded Explosives under Ultra-high Voltage Electrostatic Discharge

Different Ignition Responses of Powdery and Bulky 1,3,5-Triamino-2,4,6-Trinitrobenzene (TATB) Based Polymer-bonded Explosives under Ultra-high Voltage Electrostatic Discharge

Pin-pin ESD protection for electro-explosive device under severe human body ESD

Electrostatic discharge (ESD) may introduce huge damages to electro-explosive devices (EEDs). This paper studies the pin-pin ESD protection for EED under server human body ESD. We use the PSpice and MATLAB to simulate the ESD of EED protected with transient voltage suppressor (TVS), varistor, semiconductor arrester and capacitance. Moreover, we achieve the decay time, current waveforms, voltage waveforms and energy integration waveforms of the EED during the ESD, with different protections. Simulation results reveal that TVS succeeded in protecting bridgewire EED against the pin-pin ESD, while other three did not provide adequate protection. The pin-pin ESD experiments have been performed using the TVS and varistor. Experimental results show that, using the TVS protection, the EED is not firing under the severe 50kV ESD voltage. However, by using varistor protection, the ESD protection capability increases by more than 90%, while the protection capability only enhances by 3.1%. The response time of the TVS, i.e. 10−12s, is much faster than that of the varistor, i.e. 10−8s.

Design and optimization of LDMOS-SCR devices with improved ESD protection performance

The lateral diffusion metal-oxide semiconductor embedded silicon controlled rectifier (LDMOS-SCR) devices with optimized structures and layouts for improving the electrostatic discharge (ESD) protection ability have been proposed. The devices are designed and fabricated in 0.25-μm, 0.35-μm and 0.5-μm Bipolar-CMOS-DMOS processes. Firstly, by designing an appropriate stripe resistance in series with the source of the LDMOS-SCR, the holding voltage of the proposed high resistance LDMOS-SCR (HRLDMOS-SCR) increases. Secondly, by inserting a floating Zener-diode into the LDMOS-SCR, the trigger voltage of the modified Zener-diode triggered LDMOS-SCR (ZTLDMOS-SCR) decreases. Finally, the ZTLDMOS-SCR is further optimized by using a ring layout and incorporating a square source resistance, resulting in a significantly improved figure of merit in comparison to traditional LDMOS-SCR devices. The optimized ZTLDMOS-SCR devices are very attractive for constructing effective and latch-up immune high voltage ESD protection solutions in power integrated circuits.

Investigation on LDMOS-SCR with high holding current for high voltage ESD protection

We investigate a novel lateral diffused metal-oxide semiconductor (LDMOS) device embedded in silicon controlled rectifier (SCR) and resistance-capacitance circuit (LDMOS-SCR-RC). The internal RC-coupling effect helps to increase the holding current (Ih), resulting in the enhanced latch-up immunity of electrostatic discharge (ESD) protection device in high voltage integrated circuits (HV ICs). Transmission line pulse testing results show that the proposed LDMOS-SCR-RC has the largest Ih and smallest trigger voltage (Vt1), comparing to the conventional LDMOS-SCR and LDMOS-SCR embedded a resistance. When key parameters such as the gate-length and resistance are optimized, the Ih increases further from 1.1A to 1.5A, while the Vt1 changes insignificantly. The detailed internal mechanism of LDMOS-SCR-RC with regard to key parameters is analyzed numerically by the SENTAURUS simulation. Results confirm that the increased Ih is mainly due to the enhanced RC-coupling effect. Finally, DC measurements conducted with a semiconductor curve tracer also confirm that the LDMOS-SCR-RC with small device area is effective for avoiding latch-up risks. The optimized LDMOS-SCR-RC provides a useful latch-up immune ESD protection solution for HV ICs input/output ports.

Design and fabrication of microfluidic inkjet chip with high voltage ESD protection system for DNA droplets arrangement and detection

This article describes the aims to establish a thermal inkjet (TIJ) printhead with multi-channel driven simultaneously for DNA droplet arrangement. It proposed a monolithic CMOS/MEMS system with multi-level output voltage ESD protection system for protected inkjet printhead. High voltage power, low voltage logic and CMOS/MEMS architecture were integrated in inkjet chip. It used bulk micromachining technology (MEMS). On-chip high voltage electrostatic discharge (HV-ESD) protection design in smart power technology of monolithic inkjet chip is a challenging issue. The time interleaving scanning sequence is controlled spatially on the jet elements to avoid the strong interference with DNA droplets caused by the excitation of the neighbor driven elements. A heating element, disposed on the substrate, includes a conductor loop which does not encompass the heating elements on the substrate. The configuration of the heater jet significantly reduces both electromagnetic and capacitance interference caused by the heating elements. The simulation and experience result has shown in the research. It is reduced nearly half the time compared to the case with traditional scanning sequence. This experiment develops new controlled structure designs of chip for inkjet printheads. A TIJ device is designed, several of the architectures may be adjusted just a small microns to improve and optimize the DNA drop nucleation and generation efficiency. The DNA droplet ejection behavior of the multiplexer inkjet printhead within 10 μm orifice size has been measured beyond 26 kHz operation system, 3 pL capacity of ejected DNA droplet volume.

Electrostatic Discharge Characteristics of InGaN/GaN Light-Emitting Diodes with Si-Doped Graded Superlattice.

We report the influences of a Si-doped graded superlattice (SiGSL) on the electrostatic discharge (ESD) characteristics of an InGaN/GaN light-emitting diode (LED). For comparison, a conventional InGaN/GaN LED (C-LED) was also investigated. The luminous efficacy for the SiGSL-LED was 2.68 times stronger than that for the C-LED at the injection current of 20 mA. The resistances estimated from current-voltage (I-V) characteristic curves were 16.5 and 8.8 Ω for the C-LED and SiGSL-LED, respectively. After the ESD treatment at the voltages of 4000 and 6000 V, there was no significant change in the I-V curves for the SiGSL-LED. Also, there was small variation in the I-V characteristics for the SiGSL-LED at the ESD voltage of 8000 V. However, the I-V curves for the C-LED were drastically degraded with increasing ESD voltage. While the light emission was not observed at the injection current of 20 mA from the C-LED sample after the ESD treatment, the emission spectra for the SiGSL-LED sample were clearly measured with the output powers of 10.47, 9.66, and 7.27 mW for the ESD voltages of 4000, 6000, and 8000 V respectively.