Electrostatic Discharge Protection Design Research Articles

On-chip ESD Protection Design Methodologies by CAD Simulation

Electrostatic discharge (ESD) can cause malfunction or failure of integrated circuits (ICs) . On-chip ESD protection design is a major IC design-for-reliability (DfR) challenge, particularly for complex chips made in advanced technology nodes. Traditional trial-and-error approaches become unacceptable to practical ESD protection designs for advanced ICs. Full-chip ESD protection circuit design optimization, prediction, and verification become essential to advanced chip designs, which highly depends on CAD algorithm and simulation that has been a constant research topic for decades. This paper reviews recent advances in CAD-enabled on-chip ESD protection circuit simulation design technologies and ESD-IC co-design methodologies. Key challenges of ESD CAD design practices are outlined. Practical ESD protection simulation design examples are discussed.

Temperature dependence ofESDeffects on 28 nmFD‐SOI MOSFETs

AbstractThe failure mechanisms caused by electrostatic discharge (ESD) effects at ambient temperatures ranging from −75 to 125°C are investigated by Silvaco TCAD simulator. The devices are NMOS transistors fabricated with 28 nm fully depleted silicon‐on‐insulator (FDSOI) technology. Results indicate that with an increase in temperature, the first breakdown voltage of the device decreased by 27.32%, while the holding voltage decreased by approximately 8.49%. The total current density, lattice temperature, potential, and so forth were extracted for a detailed insight into the failure process. These findings provide valuable references for the design and development of ESD protection devices applied at different temperature ranges.

Graphene-Based ESD Protection for Future ICs.

On-chip electrostatic discharge (ESD) protection is required for all integrated circuits (ICs). Conventional on-chip ESD protection relies on in-Si PN junction-based device structures for ESD. However, such in-Si PN-based ESD protection solutions pose significant challenges related to ESD protection design overhead, including parasitic capacitance, leakage current, and noises, as well as large chip area consumption and difficulty in IC layout floor planning. The design overhead effects of ESD protection devices are becoming unacceptable to modern ICs as IC technologies continuously advance, which is an emerging design-for-reliability challenge for advanced ICs. In this paper, we review the concept development of disruptive graphene-based on-chip ESD protection comprising a novel graphene nanoelectromechanical system (gNEMS) ESD switch and graphene ESD interconnects. This review discusses the simulation, design, and measurements of the gNEMS ESD protection structures and graphene ESD protection interconnects. The review aims to inspire non-traditional thinking for future on-chip ESD protection.

Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs With Decoupling Capacitors

The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by the charged-device model (CDM), as compared with other ESD models. In this work, the CDM ESD protection capability among different power-rail ESD clamp circuits was studied and analyzed with the very-fast transmission line pulse (VF-TLP) and all the measurements are performed at room temperature. The combinations of power-rail ESD clamp circuits with internal circuits together, which are realized by ring oscillator and different decoupling capacitors, were fabricated in the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology with the 1.8-V devices to further investigate their overall CDM ESD robustness under chip-level field-induced CDM (FI-CDM) ESD stress. The investigation result of this work is helpful to provide the best selection on the power-rail ESD clamp circuit for on-chip CDM protection design in CMOS ICs.

ESD Protection Designs: Topical Overview and Perspective

Electrostatic discharge (ESD) protection remains a major challenge to integrated circuits (ICs), particularly for complex chips implemented at advanced technology nodes. Over decades, substantial advances have been made to on-chip ESD protection. This paper, instead of reviewing various specific ESD protection structures reported, provides an overview of selected key topics on practical ESD protection designs, focusing on new ESD protection concepts and design methodologies, as well as an outlook to future ESD protection designs.

RC-diode ESD protection design for high-frequency applications

To offer the electrostatic discharge (ESD) protection in high-frequency integrated circuits, a new RC-diode ESD protection design is presented in this work. The protection circuit combines the ESD diodes with the embedded silicon-controlled rectifier (SCR) and the inserting resistors to provide the appropriate performances including ESD-current-handling ability, signal loss, and layout area. Based on the experimental results in CMOS chip, the new design is a proper solution for ESD protection in high-frequency applications.

ESD Design Verification Aided by Mixed-Mode Multiple-Stimuli ESD Simulation

Electrostatic discharge (ESD) protection is a grand design challenge for complex ICs in advanced technologies. ESD simulation is indispensable to guide ESD protection designs. However, no existing ESD simulation methods may accurately predict ESD protection designs in a universal manner due to various inherent limitations. TCAD-based ESD simulation is very useful for ESD protection designs. Transmission line pulse (TLP) and very fast TLP (VFTLP) are widely used to evaluate human body model (HBM) and charged device model (CDM) ESD protection designs, which provide rich details for calibrating TCAD ESD simulation for design prediction and validation. Using various ESD protection devices fabricated in 28nm CMOS and 45nm SOI CMOS technologies, a comprehensive experimental and simulation study finds that the ESD stimuli used in TCAD ESD design simulation have profound impacts on many subtle ESD protection behaviors, particularly in comparison with ESD testing. This study cautions against over-interpretation of TCAD ESD simulation results, obtained using any specific ESD stimulus, attempting to accurately predict practical ESD protection designs. A mixed-mode multiple-stimuli ESD simulation method is therefore developed to address the ESD stimulus induced ESD performance variation, hence offering a technique to achieve ESD protection design prediction.

4H-SiC-Based ESD Protection Design With Optimization of Segmented LIGBT for High-Voltage Applications

4H-SiC is a wide-bandgap material that exhibits excellent high-temperature conductivity and high operating voltage. These characteristics can provide high electrostatic discharge (ESD) robustness in high voltage applications. However, a considerably wide range of snapback phenomena is triggered for 4H-SiC-based ESD protection devices owing to a high critical electric field. In this study, an ESD protection device based on a lateral insulated-gate bipolar transistor (LIGBT) with a new structure that creates an internal silicon-controlled rectifier (SCR) path is proposed. The proposed ESD protection device minimizes the effective base region of the NPN parasitic bipolar transistor to the gate length based on the internal SCR operation of the LIGBT. It also adjusts the emitter injection efficiency of the PNP parasitic bipolar transistor by introducing a segment topology and inserting an additional implant area. Consequently, the proposed ESD protection device significantly improves the wide range of snapback phenomena occurring in the 4H-SiC materials. A conventional SCR, the LIGBT, and the proposed protection device were fabricated using the 4H-SiC process under the same condition, and their electrical characteristics were comparatively analyzed using a transmission-line pulse system. Moreover, its high-temperature reliability was evaluated at 300–500 K to examine the compatibility with 4H-SiC devices and circuits that require a relatively high-temperature operation.

Non-Pad-Based in Situ In-Operando CDM ESD Protection Using Internally Distributed Network

Charged device model (CDM) electrostatic discharge (ESD) protection is an emerging design challenge to ICs at advanced technology nodes. It was recently reported that the traditional pad-based CDM ESD protection methods are fundamentally faulty, which causes uncertainties in CDM ESD protection designs, testing and failure analysis. Re-thinking of onchip CDM ESD protection becomes imperative for complex ICs implemented in advanced technologies. This paper reports a disruptive CDM ESD protection method utilizing non-pad-based internally-distributed ESD protection network as a robust in situ in-operando CDM ESD protection solution. The proposed internal-distributed CDM ESD protection mesh network can be realized using interposer or through-silicon-via (TSV) ESD protection structures to achieve local 3D CDM ESD protection via heterogeneous integration. The new concept was validated using an internal-CDM-protected oscillator IC implemented in a foundry 45nm silicon-on-insulator (SOI) technology.

A Study of Transient Voltage Peaking in Diode-Based ESD Protection Structures in 28nm CMOS

Transient voltage peaking under very fast electrostatic discharge (ESD), like charged device model (CDM) pulse, is a serious problem to integrated circuits (ICs). A combined TCAD simulation and very fast transmission line pulse (VFTLP) testing method is proposed to thoroughly investigate the transient voltage peaking phenomena of diode-based ESD protection structures under CDM stressing. The study of a set of diode, diode-string and diode-triggered silicon-controlled rectifier (DTSCR) ESD protection structures, fabricated in a 28nm CMOS process, reveals that the inductive impedance along the ESD discharging path may be the root cause of voltage peaking under CDM stressing. The observation provides the design insights overcoming the voltage peaking problem in ESD protection designs before complicate CDM package level testing.

3D TCAD Analysis Enabling ESD Layout Design Optimization

On-chip electrostatic discharge (ESD) protection design for integrated circuits (ICs) is a challenging design-for-reliability problem. Since ESD events involve very high current transients in very short time period, current crowding is unavoidable, which leads to local overheating and creates local hot spots, resulting in ESD thermal failures. Therefore, layout design plays a critical role in practical ESD protection designs, which cannot be addressed by 2D TCAD ESD simulation. This article reports a comprehensive ESD simulation analysis by comparing true 3D TCAD with 2D TCAD, using exemplar diode ESD devices in a 55nm CMOS, which reveals 3D ESD discharging behaviors upon ESD layout variations. It concludes that true 3D TCAD ESD simulation is a powerful technique to enable ESD layout design optimization in real-world ESD protection designs.

Pad-Based CDM ESD Protection Methods Are Faulty

Charged device model (CDM) electrostatic discharge (ESD) protection remains a huge challenge for integrated circuit (IC) reliability designs. The “internal-oriented” CDM model and the “external-oriented” human body model (HBM) describe fundamentally different ESD phenomena. Through the comprehensive analysis, this article concludes that the classic pad-based ESD protection methods, commonly used for “from-external-to-internal” HBM ESD protection, are theoretically not working for “from-internal-to-external” CDM ESD protection. It states that the actual internal distribution of static charges within a chip is vitally critical to CDM ESD protection. The discovery explains the potential root cause of the randomness and uncertainty of pad-based CDM ESD protection designs commonly observed today, hence calls for new CDM ESD protection solutions.

Drain-Extended FinFET With Embedded SCR (DeFinFET-SCR) for High-Voltage ESD Protection and Self-Protected Designs

This article presents device design insights and design challenges for drain-extended FinFET devices with embedded silicon-controlled rectifier (SCR) (DeFinFET-SCR), which can be used as an electrostatic discharge (ESD) protection device and a self-protected high-voltage switch/driver for system-on-chip applications. The tradeoff between maximizing ESD robustness without hindering the transistor’s operation is discussed in detail. An interplay between parasitic p-n-p turn-on and space charge modulation (SCM) is revealed, which strongly influences the strength of parasitic SCR and its turn-on efficiency during ESD and DC operations. Developed physical insights show that engineering p-n-p turn-on and onset of SCM are the key to maximize ESD robustness without causing early SCR turn-on during transistor operation. Based on new findings and developed physical insights, design guidelines have been derived for ESD robust DeFinFET-SCR.

A Survey on ESD protection design in different RF circuits

ESD (electrostatic discharge) protection circuits are always needed in any of the RF circuits to protect the circuit from electrostatic discharge. There are different types of ESD protection circuits. It is very important to protect the circuit from CMOS devices. In this review we have discussed ESD protection design in different RF circuits through different papers. In introduction part we have discussed causes of ESD. The problem is also discussed in the paper at the conclusion point.

ESD Protection Design With Diode-Triggered Quad-SCR for Separated Power Domains

To effectively protect the interface circuit between separated power domains from electrostatic discharge (ESD) damage, a new diode-triggered quad-silicon-controlled rectifier (DTQSCR) is proposed and realized in a 0.18- $ {\mu }\text{m}$ 1.8-V/3.3-V CMOS process. Since the DTQSCR embeds four silicon-controlled rectifier paths and a structure of back-to-back diodes, the silicon area can be efficiently reduced more than 30% as compared to the traditional ESD protection design under the same ESD specification. From the measurement results in silicon chip, an interface circuit (level shifter) with the proposed ESD protection design can successfully sustain a human-body-model of greater than 5.5 kV. The proposed ESD protection device is suitable to protect the interface circuits between different power domains.

A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models

Full-chip electrostatic discharge (ESD) protection circuit design verification is needed for complex ICs at advanced technology nodes despite being largely impractical due to the limitation of ESD device models and CAD tools. This paper reports a new circuit-level ESD protection design simulation and dynamic checking method using SPICE and ESD device behavior models which allows comprehensive, quantitative, and dynamic verification of ESD protection circuit designs at chip level-based entirely on ESD discharging functions. The new ESD protection circuit simulation method is validated using ICs designed and fabricated in a 28 nm CMOS. This ESD-function-based ESD circuit simulation method is technology independent, which can handle various ICs including complex multiple power domain circuits and ICs using nontraditional ESD protection structures.

On-Chip HBM and HMM ESD Protection Design for RF Applications in 40-nm CMOS Process

On-chip electrostatic discharge (ESD) protection device with large dimension can sustain high-ESD current, but the parasitic capacitance of the ESD protection device will increase the difficulty of impedance matching and degrade the bandwidth for broadband radio frequency (RF) applications. The traditional distributed ESD protection circuit can achieve good impedance matching, but it has a worse ESD robustness because of larger resistance caused by the input inductor. In this paper, a new distributed ESD protection structure with the stacked diodes with embedded silicon-controlled rectifier is proposed to attain good ESD robustness without degrading the RF performance. The proposed ESD protection circuit has been successfully verified in a 40-nm, 2.5-V CMOS process to sustain a human-metal model of 5 kV. The proposed ESD protection circuit is suitable to protect the broadband RF circuits in advanced nanoscale CMOS technology.

Low-C ESD Protection Design With Dual Resistor-Triggered SCRs in CMOS Technology

The electrostatic discharge (ESD) protection design with low parasitic capacitance seen at I/O pad is needed for high-frequency applications. Conventional ESD protection designs with dual diodes or dual stacked diodes have been used for gigahertz applications. To further reduce the parasitic capacitance, the ESD protection design by using complementary resistor-triggered silicon-controlled rectifiers (RTSCRs) is proposed in this paper. The proposed design includes a P-type RTSCR between I/O and ${{V}}_{{DD}}$ , an N-type RTSCR between I/O and ${{V}}_{{SS}}$ , and a power clamp circuit between ${{V}}_{{DD}}$ and ${{V}}_{{SS}}$ to achieve whole-chip ESD protection. Verified in silicon chip, the RTSCRs have the advantages, such as the sufficient low clamping voltage and lower parasitic capacitance, as compared with the conventional ESD protection designs. Therefore, the proposed design is suitable for low-C ESD protection in CMOS technology.

On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly requested in high-speed I/O applications. The traditional methods to reduce parasitic capacitance were using a stacked diode or a stacked diode with embedded silicon-controlled rectifier (SCR). The stacked diode or the stacked diode with embedded SCR would have larger turn-on resistance to cause a higher clamping voltage. It should be further improved to achieve good ESD protection effectiveness for the high-speed I/O applications. In this paper, a new ESD protection device with reduced parasitic capacitance and smaller turn-on resistance to improve ESD protection effectiveness is proposed. The measurement results from the silicon chip have demonstrated that the proposed ESD device can achieve smaller parasitic capacitance, lower turn-on resistance, and higher ESD robustness, compared with the conventional devices. The proposed ESD protection device is very suitable to protect the high-speed I/O circuits in nanoscale CMOS technology.

ESD protection design and enhancement in the power 60‐V n‐channel LDMOS by embedded‐SCR anode islands

An electrostatic discharge (ESD) strengthening design of high-voltage (HV) n-channel laterally diffused metal–oxide semiconductor (nLDMOS) transistors combined with embedded-SCR anode islands is investigated. After a systematic layout implementation and analysis, the anti-ESD robustness [or secondary breakdown current (It2)] of drain pnp-arranged and SCR isolated-type DUTs were higher than 7-A (ESD reliability improvements of these nLDMOS-SCR devices were more than 282.5% (199.2%) higher than that of the pure nLDMOS (pnp-stripe) component. Also, it can be found that the ESD robustness of the pnp-arranged type is greater than the npn-arrangement. Therefore, an adequate architecture of an HV nLDMOS device embedded with an SCR (pnp-arranged) and SCR isolated manner can gain high ESD-reliability immunity.