Electrostatic Discharge Characteristics Research Articles

A novel low trigger voltage low leakage SCR for low-voltage ESD protection

Reducing trigger voltage has always been a research hotspot in low-voltage electrostatic discharge (ESD) protection applications for integrated circuit. Thus, a novel low trigger voltage low leakage silicon-controlled rectifier (LTVLLSCR) for low-voltage ESD protection has been proposed. The proposed device uses a PMOS connected with the SCR to reduce the trigger voltage and the PMOS gate can be applied with the supply voltage to further reduce the trigger voltage and the leakage current. The operating principle and the physical mechanism of the proposed device were discussed by the Human Body Model simulation. The ESD characteristics of the proposed device were verified in 55 nm CMOS process. The experimental results demonstrate that the trigger voltage of the proposed device can reach a minimum of 2.86 V with an external bias, and the leakage current at 25 °C is about 1 nA which can be reduced by 13% with an external bias. With lower trigger voltage, lower leakage, smaller ESD design window and good ESD robustness, the LTVLLSCR is very suitable for 1 V low voltage applications.

Dual-directional SCR device with dual-gate controlled mechanism for ESD protection in photoelectric chip

The dual-directional silicon-controlled rectifier (DDSCR) is an electrostatic discharge (ESD) protection device. It can provide positive and negative ESD surge paths and has excellent robustness. However, industry-level sensors operating in strong electromagnetic interference environments impose higher reliability requirements on photoelectric chips. This paper proposed a novel DDSCR with a dual-gate controlled mechanism. By incorporating the gate diode triggering and the gate field modulation mechanism into the traditional DDSCR, and further utilizing additional parasitic bipolar junction transistors (BJTs) for diversion, the proposed device exhibits significantly improved ESD characteristics. Measurement results indicate that, compared to DDSCR, the proposed device exhibits a 27.5% reduction in trigger voltage (Vt1 ), a 96.1% improvement in holding voltage (Vh ), and achieves an equivalent human body model protection level of 11.45 kV, demonstrating exceptional design area efficiency. The experimental findings validate the effectiveness of the proposed device in 5 V photoelectric chip applications.

Design and verification of a hybrid electrostatic discharge model for Gate-Controlled silicon controlled rectifier

The DC breakdown characteristic of electrostatic discharge (ESD) protection device, which is an important indicator of its transparency and circuit compatibility, has received widespread attention. Currently, methods such as Verilog-A hardware description language, circuit-level SPICE simulation, and process-level device modeling cannot simultaneously achieve high accuracy, good convergence, and fast simulation speed. Therefore, in this paper, a hybrid ESD model based on Technology Computer Aided Design (TCAD) device-level simulation, Monte Carlo numerical modeling and Verilog-A behavioral modeling is proposed to characterize the ESD characteristics of gate-controlled silicon-controlled rectifier (GCSCR). A device-level model of GCSCR was established using TCAD, and the working mechanism was simulated. By extracting the electric field from TCAD and using the Monte Carlo modeling method, the DC characteristic of GCSCR was accurately characterized. In addition, the snapback characteristic of the device was successfully simulated by Verilog-A. The effectiveness of the above approaches was further verified based on the 0.18 μm standard BCD (Bipolar-CMOS-DMOS) process. Comparison results indicate that the hybrid model exhibits high simulation accuracy, good convergence and good universality and scalability, providing a simple and effective modeling solution for ESD devices of different structures and sizes.1This work is supported by the National Natural Science Foundation of China (Grant No. 62174052, 61827812), Hunan Science and Technology Department Huxiang High-level Talent Gathering Project (Grant No. 2019RS1037) and Innovation Project of Science and Technology Department of Hunan Province (Grant No. 2020GK2018).

A novel robust SCR with high holding voltage for on-chip ESD protection of industry-level bus

In an industry-level bus, strong electrostatic interference seriously threatens the reliability of chips. However, the holding voltage (Vh) and robustness of traditional silicon-controlled rectifier (SCR) cannot meet the electrostatic discharge (ESD) window of industry-level applications. To better cope with extreme environments, this paper proposes a novel SCR with high robustness and latch-up immunity for on-chip ESD protection of the industry-level RS485 bus. By incorporating a surface current diverting path into the traditional SCR, the ESD characteristics of the proposed device are significantly improved. Through two-dimensional device simulation, the ESD characteristics of traditional SCR, proposed P-Well Floating SCR (PFSCR) and proposed P-Well Grounded SCR (PGSCR) are compared, with a focus on exploring the role of surface discharge path. Three types of SCR are realized based on the 0.18 μm BCD process. The transmission line pulse (TLP) test results show that PGSCR (13.64 V) has a higher Vh and higher robustness than traditional SCR (2.13 V) and PFSCR (4.39 V). In addition, the trigger voltage (Vt1:22.9 V) and failure current (It2:18.49A) of the PGSCR fully meet the ESD window of the target chip.

The ESD Characteristics of a pMOS-Triggered Bidirectional SCR in SOI BCD Technology

In this work, the electrostatic discharge (ESD) characteristics of a pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) that was fabricated in a 0.18 μm silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process, is investigated. The multi-snapback phenomenon was observed under the transmission line pulsing (TLP) test system. It was found that gate voltage and inserting shallow trench isolation (STI) can significantly affect the trigger voltage and holding voltage. The underlying physical mechanism related to the multi-snapback phenomenon and the effects of gate voltage on the critical parameters was investigated through the experimental results and the assistance of technology computer-aided design (TCAD) simulations. The adjustments of gate voltage and STI on the critical ESD parameters of the device provide an effective design idea for low-voltage ESD protection in the SOI BCD process.

Effect of high-temperature on holding characteristics in MOSFET ESD protecting device

The holding voltage of electrostatic discharge (ESD) protecting structure is the critical parameter to determine the latch-up performance of the protecting device, but the thermal change of ESD device parameters lead the protecting device to suffer latch-up risk at high ambient temperature. In this paper, the holding characteristics of the ESD protecting device at various ambient temperatures ranging from 30 ℃ to 195 ℃ are studied. The investigated ESD structure is the N-channel metal oxide semiconductor (NMOS) transistors fabricated with the 0.18 μm partially depleted silicon-on-insulator process. The ESD characteristics of the device are measured by the transmission line pulse test system at different ambient temperatures. The test results show that the holding voltage (<i>V</i><sub>H</sub>) decreases with temperature increasing. The TCAD simulation is carried out to support and analyze the experimental results, and the same trend of <i>V</i><sub>H</sub> versus temperature is obtained. Through the analysis of simulation results and theoretical derivation, the underlying physical mechanisms related to the effects of temperature on <i>V</i><sub>H</sub> and holding current (<i>I</i><sub>H</sub>) are discussed in detail. When the drain is subjected to the same current pulsing and the Source and Body are both grounded, the distributions of current density, electric potential, and injected electron density of NMOS at various temperatures are extracted and analyzed. When the Drain, Source, and Body are all grounded, the distributions of the electrostatic field at various temperatures are extracted and analyzed. The distribution of electric potential in NMOS indicates that the voltage drop on the Drain-Body junction (<i>V</i><sub>DB</sub>) is affected by ambient temperature significantly, and the variation of <i>V</i><sub>DB</sub> dominates the variation trend of <i>V</i><sub>H</sub> with temperature increasing. The reducing electrostatic field and increasing injected electron density with temperature decreasing contribute to the decreasing of <i>V</i><sub>DB</sub>. The trend of <i>I</i><sub>H</sub> and parasitic Body resistance (<i>R</i><sub>Body</sub>) weakens the temperature dependence of the <i>V</i><sub>H</sub>. The current gain of parasitic bipolar transistor (<i>β</i>) decreases with ambient temperature rising, which is the main contributor to the decreasing of <i>I</i><sub>H</sub>. Therefore, increasing <i>I</i><sub>H</sub> and <i>R</i><sub>Body</sub> is helpful in reducing the temperature dependence of the latch-immune ESD protection structure.

A novel percolation model of leakage fluctuation behavior in gate-control dual-direction silicon controlled rectifier

Gate structures are used as efficient auxiliary components to improve the electrostatic discharge (ESD) performance of traditional silicon controlled rectifiers (SCRs). However, it has not been explored how the gate geometry potentially affects leakage behaviors and ESD characteristics of SCR devices. In this paper, a novel percolation model is proposed to address this problem. The percolation model fundamentally interprets the leakage fluctuation behavior of the gate-control dual-direction silicon controlled rectifier (GC-DDSCR) under ESD events. Two key parameters breakdown charge (QBD) and tunneling current (Jg) are simulated to link the gate geometry and gate oxide quality, revealing the principle of the leakage fluctuation behavior. The leakage fluctuation behavior may cause GC-DDSCR to work in an unstable state, leading to the premature functional failure of the intrinsic SCR path. Two GC-DDSCRs with different gate sizes are fabricated under a 0.5 μm CMOS technology and characterized by a transmission line pulse (TLP) test. Experiment results show the GC-DDSCR with a larger gate size is more prone to the leakage fluctuation behavior and the premature functional failure. The percolation model is qualitatively verified and the understanding of the gate structure in ESD devices is deepened.

Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN* *Project supported by the National Natural Science Foundation of China (Grant No. 61504049).

Ultra-high-voltage (UHV) junction field-effect transistors (JFETs) embedded separately with the lateral NPN (JFET-LNPN), and the lateral and vertical NPN (JFET-LVNPN), are demonstrated experimentally for improving the electrostatic discharge (ESD) robustness. The ESD characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-kV human body model (HBM) test. The JFETs embedded with different NPNs have 3.75 times stronger in ESD robustness than the conventional JFET. The failure analysis of the devices is performed with scanning electron microscopy, and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance capabilities. Finally, the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation, and the results confirm that the JFET-LVNPN has stronger ESD robustness than the JFET-LNPN, because the vertical NPN has a better electron collecting capacity. The JFET-LVNPN is helpful in providing a strong ESD protection and functions for a power device.

Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network

The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing a secondary path in a whole-chip electrostatic discharge (ESD) protection network. In this paper, the ESD characteristics of a traditional point TFET, a line TFET and a Ge-source TFET are investigated using technology computer-aided design (TCAD) simulations, and an improved TFET-based whole-chip ESD protection scheme is proposed. It is found that the Ge-source TFET has a lower trigger voltage and higher failure current compared to the traditional point and line TFETs. However, the Ge-source TFET-based secondary path in the whole-chip ESD protection network is more vulnerable compared to the primary path due to the low thermal instability. Simulation results show that choosing the proper germanium mole fraction in the source region can balance the discharge ability and thermal failure risk, consequently enhancing the whole-chip ESD robustness.

Vertical bipolar junction transistor triggered silicon‐controlled rectifier for nanoscale ESD engineering

In this Letter, a novel vertical bipolar junction transistor (BJT) triggered silicon-controlled rectifier (VBTSCR) is proposed for advanced nanoscale electrostatic discharge (ESD) protection applications. With the help of a vertical NPN transistor in floating base configuration, the new silicon-controlled rectifier (SCR) structure achieves lower trigger voltage and better clamping capacity than the prior enhanced modified lateral SCR (EMLSCR) under the same layout footprint. The ESD characteristics are measured using the transmission line pulsing tester. Compared with that of EMLSCR, the trigger voltage of VBTSCR drops by 1 V, and the effective ESD robustness of VBTSCR has been doubled significantly. Based on these advantages, the proposed VBTSCR can provide ESD protection for the advanced 1.8/2.5 V input/output circuits more efficiently.

Analysis of High-Failure Mechanism Based on Gate-Controlled Device for Electro-Static Discharge Protection

As semiconductor process continues to advance, the miniaturization of feature sizes places higher demands on high-failure electro-static discharge (ESD) applications. This article explores the connection between the physical structure of a device-level silicon controlled rectifier (SCR) and high-failure ESD characteristics. The gate-controlled silicon controlled rectifier (GCSCR) based on the gate control effect is fabricated using the $0.18~\mu \text{m}$ standard bipolar complementary-metal-oxide-semiconductor double-diffused-metal-oxide-semiconductor (BCD) process. The ESD characteristics of the device are analyzed by technology computer aided design (TCAD) simulation and equivalent circuits. The transmission line pulse (TLP) is used to test the performance of the device. The results show that when the gate length is $4~\mu \text{m}$ , the failure current of the device is only 1.56A. When the gate length is $1~\mu \text{m}$ , the trigger voltage and the holding voltage of the device are 24.4V and 21.1V respectively, and the failure current is 34.94A. According to the test results of the above devices, it can be concluded that the current release mode of GCSCR with different gate sizes significantly affects the ESD characteristics of the device.

Bidirectional silicon‐controlled rectifier for advanced ESD protection applications

In this Letter, an enhanced bidirectional modified lateral silicon-controlled rectifier (EBMLSCR) is proposed for advanced dual-directional electrostatic discharge (ESD) protection applications. The ESD characteristics of the novel EBMLSCR and conventional bidirectional modified lateral silicon-controlled rectifier (BMLSCR) are measured using the transmission line pulsing tester. Compared with the BMLSCR, the EBMLSCR owns a lower trigger voltage down to 7.7 V, a higher failure current up to 6.5 A, a suitable holding voltage as well as the same superior leakage current. Based on these advantages, the proposed EBMLSCR can provide an effective ESD protection for the advanced 2.5 V/3.3 V input/output circuits, while the traditional BMLSCR becomes invalid for these applications due to its high trigger voltage and low robustness. In addition, the impact of some critical dimensions of the EBMLSCR has also been evaluated to further optimise the device performances.

Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET.

Currently, a tunnel field-effect transistor (TFET) is being considered as a suitable electrostatic discharge (ESD) protection device in advanced technology. In addition, silicon-germanium (SiGe) engineering is shown to improve the performance of TFET-based ESD protection devices. In this paper, a new TFET with SiGe source/drain (S/D) regions is proposed, and its ESD characteristics are evaluated using technology computer aided design (TCAD) simulations. Under a transmission line pulsing (TLP) stressing condition, the triggering voltage of the SiGe S/D TFET is reduced by 35% and the failure current is increased by 17% in comparison with the conventional Si S/D TFET. Physical insights relevant to the ESD enhancement of the SiGe S/D TFET are provided and discussed.

Characteristics of electrostatic discharges between metallic objects in the ion‐flow field under HVDC lines

Metallic objects under high-voltage direct current (HVDC) transmission lines will produce certain induced voltages due to the charging of ion flow. Electrostatic discharge (ESD) may occur between two objects at different potentials when they are close enough to spark under HVDC transmission lines. With a view to investigating such events in the ion-flow field generated by HVDC transmission lines, a laboratory study on the ESD characteristics of two metallic objects in a close approach to each other under HVDC line is conducted. Discharge current and induced voltage are monitored to analyse the effect of experimental parameters. The ground-level electric field without objects was measured, and the relationship between it and the voltage on objects was explored.

Improvement of device performances, including electrostatic discharge characteristics, of InGaN/GaN light-emitting diodes by using a Si-doped graded superlattice

We report the influences of a Si-doped graded-superlattice (SiGSL) on the structural, optical, and electrical properties of InGaN/GaN light-emitting diodes (LEDs). For comparison, LEDs fabricated on an undoped graded superlattice (unGSL-LED) and conventional LEDs without the superlattice (C-LED) were prepared. The dependences of the carrier behaviors on the surface inhomogeneity and the defect/dislocation distribution were investigated by using fluorescence microscopy images, wherein the dark features corresponding to the defects/threading dislocations for the unGSL-LED and the SiGSL-LED were significantly reduced compared to that for the C-LED. The photoluminescence intensities of the unGSL-LED and the SiGSL-LED were 1.15 and 1.24 times stronger than that of the C-LED, respectively. The output powers of the unGSL-LED and the SiGSL-LED at an injection current of 20 mA were measured to be 1.32 and 1.41 times higher than that of the C-LED, respectively. Moreover, the electrostatic discharge characteristics of the LED sample using the SiGSL structure were drastically improved.

Influences of graded superlattice on the electrostatic discharge characteristics of green InGaN/GaN light-emitting diodes

In this paper, the influence of a Si-doped graded superlattice (SiGSL) on the electrostatic discharge (ESD) characteristics of green InGaN/GaN light-emitting diodes (LEDs) is discussed. To investigate the effects of Si doping to the superlattice, green LEDs were also fabricated on undoped graded superlattice (unGSL). Furthermore, a conventional green InGaN/GaN LED without the superlattice (C-LED), emitting at a wavelength of 534nm, was also prepared as a reference. The current-voltage (I-V) curves for the C-LED and the unGSL-LED subjected to the ESD treatments at surge voltages from 2000 to 8000V showed a drastic increase in the leakage current. However, there was relatively small change in the I-V curves for the SiGSL-LED after the ESD treatments, even at the surge voltages of 6000 and 8000V. After the ESD treatment at a surge voltage of 8000V, the EL intensities for the C-LED, unGSL, and SiGSL, measured at a driving current of 120mA, were reduced by 55, 53, and 30%, respectively, compared to those of the as-fabricated LEDs.

A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS

This paper discusses a systematic study of electrostatic discharge (ESD) protection circuit co-design and analysis technique for high-frequency and high-speed ICs in 28 nm CMOS. The comprehensive ESD-IC co-design flow includes ESD device optimization and characterization, ESD behavioral modeling, backend interconnect characterization, parasitic ESD parameter extraction, ESD failure analysis and ESD co-design evaluation for ICs operating at up to 15 GHz and 40 Gbps. Ring oscillator, dummy I/O buffer and current mode logic (CML) circuits were used to demonstrate the co-design method. This practical ESD-IC co-design technique can be applied to high-performance, high-frequency and high-speed ICs.

Electrostatic Discharge Characteristics of InGaN/GaN Light-Emitting Diodes with Si-Doped Graded Superlattice.

We report the influences of a Si-doped graded superlattice (SiGSL) on the electrostatic discharge (ESD) characteristics of an InGaN/GaN light-emitting diode (LED). For comparison, a conventional InGaN/GaN LED (C-LED) was also investigated. The luminous efficacy for the SiGSL-LED was 2.68 times stronger than that for the C-LED at the injection current of 20 mA. The resistances estimated from current-voltage (I-V) characteristic curves were 16.5 and 8.8 Ω for the C-LED and SiGSL-LED, respectively. After the ESD treatment at the voltages of 4000 and 6000 V, there was no significant change in the I-V curves for the SiGSL-LED. Also, there was small variation in the I-V characteristics for the SiGSL-LED at the ESD voltage of 8000 V. However, the I-V curves for the C-LED were drastically degraded with increasing ESD voltage. While the light emission was not observed at the injection current of 20 mA from the C-LED sample after the ESD treatment, the emission spectra for the SiGSL-LED sample were clearly measured with the output powers of 10.47, 9.66, and 7.27 mW for the ESD voltages of 4000, 6000, and 8000 V respectively.

Research on electrostatic discharge characteristics of tunnel field effect transistors

Power consumption has been the major bottleneck in the development of integrated circuits with reduced critical dimensions and improved integrated level. Tunnel field effect transistor (TFET) has been investigated as one of the promising replacements for traditional metal oxide semiconductor field effect transistor (MOSFET), owing to the introduction of band to band tunneling (BTBT) mechanism based on which a smaller subthreshold slope is achieved. However, a thinner oxide layer and a shorter channel length in TFET may induce localization of high current density, high electrical field distribution, and generation of heat, which abate the probability to survive electrostatic discharge (ESD). Besides, the novel BTBT operating principles also present a challenge to TFET ESD protection design. In this paper transmission line pulse test method is adopted to analyze the working principle of conventional TFET at onset, holding, discharge, and second breakdown during an ESD event. Based on these a new TFET ESD device protection design is proposed and characterized with a deeply doped n+ pocket near the source region beneath the gate, which can make effective adjustments of contact potential barrier, reduce tunneling junction width, thus better ESD design windows are obtained.

An investigation on capacitance-trigger ESD protection devices for high voltage integrated circuits

A novel cascaded complementary dual-directional silicon controlled rectifier (CCDSCR) structure has been proposed and implemented in a 0.5μm 20V Bipolar/CMOS/DMOS process as an ESD (electrostatic discharge) protection device. The ESD characteristics of the capacitance-trigger CCDSCR has been investigated by transmission line pulse (TLP) testing. Compared with the substrate-trigger insulated gate bipolar transistor with the enhanced substrate parasitic capacitance, the gate-driven trigger insulated gate bipolar transistor with the gate coupling capacitance and the normal dual-directional silicon controlled rectifier, the CCDSCR has the highest holding voltage of about 25.4V and the best current conduction uniformity. In addition, it has the best figure of merit (FOM) with the value of about 0.64mA/μm2. The good current conduction uniformity in CCDSCR due to the enhanced substrate parasitic capacitance-trigger effect is finally confirmed by Sentaurus simulations.