Electrostatic Discharge Capability Research Articles

Research on the electro-magnetic protection technique of SCB bridge based on vertical punch through PN junction

Pyrotechnic device is the key initiating component of weapon system, and its function reliability will directly affect the triggering of detonation and actuation mechanism. In order to enhance the survival ability of pyrotechnic device in intricate electromagnetic interference environment, it is necessary to carry out in-depth research on the electromagnetic protection technique of pyrotechnic device. In this paper, a new electromagnetic protection circuit based on vertical punch through PN junction device is proposed, which monolithically integrates the circuit with polysilicon semiconductor bridge on a single chip. The Electro-static Discharge (ESD) test was carried out according to the method specified by standard electrostatic standard 500 pF/500 Ω/25 kV, and the ESD capability of the proposed new chip was not less than 25 kV. Compared with the electromagnetic protection circuit by transient voltage suppressor diode based on lateral punch through junction device structure, the new chip increases the effective junction area of PN junction, reduces the current density, and increases the current conduction ability and electrostatic roughness of the diode. The new chip has a larger diode effective junction capacitance, which not only improves the ESD capability but also improves the RF protection capability at the same time.

Additive manufacturing of polyamide nanocomposites for electrostatic charge dissipation applications

Polyamide 6 (PA 6) nanocomposites are viable engineered nanocomposite materials with potential application in electrostatic discharge dissipation applications. Creating an electrically conductive path to dissipate electrostatic charges in such materials can be a viable solution to electrostatic discharge (ESD) concerns. The addition of nanofillers can also enhance mechanical properties of the parent polyamide 6, a structural thermoplastic ideal for 3D printing via fused deposition modelling (FDM). While improving the ESD capability, it is imperative to sustain the structural integrity of the nanocomposites. Hence, this study evaluated the mechanical, thermal, and electrical properties of 3D printed PA6 nanocomposites for electrostatic discharge applications. 3 and 5 wt% of carbon nanofibers (CNF) was compounded with PA6 using co-rotating twin screw extruder to produce 1.75 mm diameter monofilaments for fused deposition modelling (FDM). The test samples were printed using commercial-off-the-shelf (COTS) 3D printer, Lulzbot TAZ 6 FDM printer. Mechanical, electrical, and thermal characterization was carried out according to their respective ASTM standard. The tensile and flexural properties were enhanced by 3 wt% addition of CNF, but no significant improvement was observed at 5 wt%. The CNF nanocomposites exhibited good thermal stability and crystallization phenomenon at both loading levels. The volume resistivity of the of the PA6 matrix was reduced to order of 1011 and 1012 by 3 wt% and 5 wt% CNF addition respectively, which seems promising for manufacturing static discharge products.

Enhance the ESD Ability of UHV 300-V Circular LDMOS Components by Embedded SCRs and the Robustness P-Body Well

The ultra-high voltage (UHV) Lateral-diffused MOSFET (LDMOS) transistor has been widely used in power circuit applications and also used as an electrostatic discharge (ESD) self-protection device. However, the ESD ability of an UHV LDMOS is generally worse than that of low- and high-voltage (HV) devices, which means this UHV LDMOS device can be easily failed under an ESD event. Then, the method of embedded a silicon-controlled rectifier (SCR) into the HV LDMOS has been used in the HV circuit as an ESD protection technique. But when this architecture is applied to UHV devices, will its ESD capability be as good as in HV devices? A novel SCR with a P-body well architecture is proposed, which can effectively enhance the ESD ability of the UHV nLDMOS device when the drain side is embedded this new structure. The proposed structure can greatly improve the ESD capability of the device without adding any extra process step (& photomask), layout area and affecting the basic breakdown voltage. Finally, the proposed structure of the PPP-arranged type with the P-body well can greatly increase the ESD (FOM) ability which $\text{I}_{\mathrm{ t2}}$ and HBM ability can be increased by 68.7% and 22.2% (72.9%), respectively, as compared with the conventional SCR PPP-arranged type.

Robust ESD-Reliability Design of 300-V Power N-Channel LDMOSs with the Elliptical Cylinder Super-Junctions in the Drain Side

The weak ESD-immunity problem has been deeply persecuted in ultra high-voltage (UHV) metal-oxide-semiconductor field-effect transistors (MOSFETs) and urgently needs to be solved. In this paper, a UHV 300 V circular n-channel (n) lateral diffused MOSFET (nLDMOS) is taken as the benchmarked reference device for the electrostatic discharge (ESD) capability improvement. However, a super-junction (SJ) structure in the drain region will cause extra depletion zones in the long drain region and reduce the peak value of the channel electric field. Therefore, it may directly increase the resistance of the device to ESD. Then, in this reformation project for UHV nLDMOSs to ESD, two strengthening methods were used. Firstly, the SJ area ratio changed by the symmetric eight-zone elliptical-cylinder length (X) variance (i.e., X = 5, 10, 15 and 20 μm) is added into the drift region of drain side to explore the influence on ESD reliability. From the experimental results, it could be found that the breakdown voltages (VBK) were changed slightly after adding this SJ structure. The VBK values are filled between 391 and 393.5 V. Initially, the original reference sample is 393 V; the VBK changing does not exceed 0.51%, which means that these components can be regarded as little changing in the conduction characteristic after adding these SJ structures under the normal operating conditions. In addition, in the ESD transient high-voltage bombardment situation, the human-body model (HBM) capability of the original reference device is 2500 V. Additionally, as SJs with the length X high-voltage P-type well (HVPW) are inserted into the drain-side drift region, the HBM robustness of these UHV nLDMOSs increases with the length X of the HVPW. When the length X (HVPW) is 20 μm, the HBM value can be upgraded to a maximum value of 5500 V, the ESD capability is increased by 120%. A linear relationship between the HBM immunity level and area ratio of SJs in the drains side in this work can be extracted. The second part revealed that, in the symmetric four-zone elliptical cylinder SJ modulation, the HBM robustness is generally promoted with the increase of HVPW SJ numbers (the highest HBM value (4500 V) of the M5 device improved by 80% as compared with the reference device under test (DUT)). Therefore, from this work, we can conclude that the addition of symmetric elliptical-cylinder SJ structures into the drain-side drift region of a UHV nLDMOS is a good strategy for improving the ESD immunity.

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the Vt1 and Vh values were closest to 21.85, and 9.27 V, respectively. The It2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low Vh characteristic. By removing the entire heavily doped drain-side N+ region, the equivalent series resistance in the drain region was increased, so that the It2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high Vh behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%.

Novel Cathode Design to Improve the ESD Capability of 600 V Fast Recovery Epitaxial Diodes

Silicon power diodes are used to design different types of electrical energy systems. Their performance has been improved substantially, as a result of a concentrated research efforts that have taken place in the last two decades. They are considered immune to electrostatic discharge (ESD) failures, since usually they withstand an avalanche energy one order of magnitude higher than that of the ESD. Consequently, few works consider this aspect. However, it was observed that during the mounting of power diodes in automotive systems (e.g., with operators touching and handling the devices), ESD events occur and devices fail. In this paper the ESD capability of 600 V fast recovery epitaxial diode (FRED) is analyzed by means of Technology Computer-Aided Design (TCAD) simulations, theoretical analyses and experimental characterization. Two doping profiles are investigated in order to improve the ESD robustness of a standard device and an optimized doping profile is proposed. The proposed design exhibits a higher ESD robustness and this is due to its superior capability in keeping the current distribution uniform in the structure in a critical condition such as the impact ionization avalanche effect. Both experimental and numerical results validate the proposed design.

Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process

As CMOS processes advanced, the integration of radio-frequency (RF) integrated circuits was increasing. In order to protect the fully-integrated RF transceiver from electrostatic discharge (ESD) damage, the transmit/receive (T/R) switch of transceiver frond-end should be carefully designed to bypass the ESD current. This work presented a technique of embedded ESD protection device to enhance the ESD capability of T/R switch. The embedded ESD protection devices of diodes and silicon-controlled rectifier (SCR) are generated between the transistors in T/R switch without using additional ESD protection device. The design procedure of RF circuits without ESD protection device can be simplified. The test circuits of 2.4-GHz transceiver frond-end with T/R switch, PA, and LNA have been integrated and implemented in nanoscale CMOS process to test their performances during RF operations and ESD stresses. The test results confirm that the embedded ESD protection devices can provide sufficient ESD protection capability and it is free from degrading circuit performances.

Drain Side N<sup>+</sup> Layout Manners ("npnpn" Arranged-Type) on ESD Robustness in the 60-V pLDMOS-SCR

Electrostatic-discharge (ESD) immunity measurements of different layout manners in the drain-side of HV pLDMOS devices are investigated in this paper. Here, eleven kinds of drain-side "npnpn" arranged-types of pLDMOS-SCR parasitic structure are used to evaluate the layout impacts on ESD robustness. In this study, at first the layout type of N+ region is continuous extended into the drain-side P+ cathode. Secondly, the layout type of N+ region is modulated by some discrete-distributed areas in the drain-side. From the experimental results, we can find that the ESD capability of the continuous extended and discrete distributed in the drain-side can be promoted, where all of the secondary breakdown current (It2) values can be achieved 7 A. However, the discrete-distributed layout type has higher breakdown voltage (VBK) than that of the reference group (the pure none modulated pLDMOS-SCR npnpn-type structure). Therefore, the discrete-distributed layout types show good electrical properties and reliability immunities.

200 V Fast Recovery Epitaxial Diode with superior ESD capability

In this paper the Electrostatic Discharge (ESD) capability of 200V Fast Recovery Epitaxial Diodes (FREDs) is analysed by means of suitable experiments, TCAD simulations and theoretical analyses. Different doping profiles are investigated in order to improve the ESD robustness of a standard device and an optimized doping profile is proposed. The newly fabricated devices show a remarkably high ESD capability without any significative loss in forward voltage drop and a reduction of the breakdown voltage that does not affect device rating.

Systematic Characterization of Graphene ESD Interconnects for On-Chip ESD Protection

We report systematic transient characterization of a graphene ribbon (GR) used as an interconnect for electrostatic discharge (ESD) protection of future integrated circuits. A large set of GR wires (around 6000) with varying and practical dimensions were fabricated using the chemical vapor deposition method and characterized by transmission line pulsing (TLP) and very fast TLP (VFTLP) measurements. Comprehensive TLP and VFTLP testing with varying pulse rise time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{r})$ </tex-math></inline-formula> and duration ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{d})$ </tex-math></inline-formula> was performed across a wide temperature range ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T = -30/+110~^{\circ }\text{C}$ </tex-math></inline-formula> ). Measurement-based statistics reveal the relationship between ESD capability of GR wires and the wire length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L$ </tex-math></inline-formula> ), width ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$ </tex-math></inline-formula> ), and number of graphene layers, as well as ESD pulse shapes and operation temperature.

Ultralow Capacitance Transient Voltage Suppressor Design

A novel transient voltage suppressor (TVS) that features ultralow capacitance is proposed. This structure is able to reduce the input capacitance by 21.1%, and is designed to protect against electrostatic discharge (ESD) issues for high-speed ports. The device is also able to withstand IEC 61000-4-2 contact testing at ±14 kV and transmission line pulse (TLP) testing at 20 A. The device is fabricated using a typical planar Bipolar-CMOS-DMOS (BCD) process. By slotting the doping well to decrease the concentration of diodes, a TVS with an ultralow $C_{j}$ is obtained without the need to add to the process procedures or without damaging the ESD capability.

A Comprehensive Evaluation of Drain-side Layout Topologies on the Power nLDMOS ESD/LU Reliabilities

The non-uniform turned-on and low holding-Voltage (V h) issues are seriously impacted the reliability abilities of an n-channel lateral-diffused power MOSFET (nLDMOS). Therefore, basing on the drain Field-Oxide Device (FOD) structure of an nLDMOS and changing the thin-Oxide Definition (OD) topology for contacts located in the middle region of drain-side will be investigated in this study. The OD structure will renew as some dotted-OD manners. Experimental results show that the dotted-OD layout has a higher Electrostatic Discharge (ESD) capability than that of the FOD structure and the layout type of dotted-OD will affect the ESD capability of an HV component. A uniformly distributed type of dotted-OD will have a highest I t2 value, the I t2 value is increased about 12% as compared with the Ref. traditional nLDMOS. And, the V h value will increase with the contacts number increasing within the dotted-OD, which is increased about 28.2% of a dotOD46 device as compared with the traditional nLDMOS. Furthermore, as adding an FODs structure combined with a uniform dotted-OD structure in the drain side will be haven a high ESD capability (about 5.9% increasing) and high LU immunity (25.8% increasing) compared with the traditional nLDMOS DUT. Therefore, it is good both for ESD and Latch-Up (LU) reliability considerations.

파워 클램프용 래치-업 면역 특성을 갖는 SCR 기반 ESD 보호회로

In this paper, SCR(Silicon Controlled Rectifier)-based ESD(Electrostatic Discharge) protection circuit for power clamp is proposed. In order to improve latch-up immunity caused by low holding voltage of the conventional SCR, it is modified by inserting n+ floating region and n-well, and extending p+ cathode region in the p-well. The resulting ESD capability of our proposed ESD protection circuit reveals a high latch-up immunity due to the high holding voltage. It is verified that electrical characteristics of proposed ESD protection circuit by Synopsys TCAD simulation tool. According to the simulation results, the holding voltage is increased from 4.61 V to 8.75 V while trigger voltage is increased form 27.3 V to 32.71 V, respectively. Compared with the conventional SCR, the proposed ESD protection circuit has the high holding voltage with the same triggering voltage characteristic.

Impact of Drain-Side nWell Engineering on ESD Robustness in 0.35μm LV MOSTs

A multi-finger nMOST is widely used as an electrostatic discharge (ESD) protection device especially in the input/output pads. However, the contact-spiking leakage phenomenon in an MOST are seriously impacted the ESD capability. Therefore, one drain-side engineering is investigated in this paper, i.e., by adding a negative-type well (nWell) structure in the drain-side of device, hoping to avoid contact-spiking issues to enhance ESD reliability. The nWell width variations will be explored the influence on snapback parameters of ESD devices in a 0.35μm 3.3V low voltage (LV) process. However, after a systematic analysis, it is found that adding an nWell structure in the drain-side will lower ESD capability (It2 value) about 24% for this process. And, as compared with the original reference DUT, adding any nWell in the drain-side will make the Vh value slightly decreasing about 1%.