Analytic expressions describing electron and hole current flow in the metal/tunnel—oxide/ n-silicon structure are derived. In the particular approach that is taken, the tunneling barrier presented by the SiO 2 layer is treated using a “thick-oxide” MOS model; i.e. a trapezoidal tunneling barrier is used. Rather than assume a constant tunneling probability, the dependence of the tunneling barrier on applied bias and on the minority carrier density at the semiconductor surface is also included. Calculations based on the resultant equations are found to be in good agreement with experimental observations, and to correctly predict the “current-multiplication” effect that occurs under conditions of minority carrier injection to the SiSiO 2 interface [1]. The derived equations are used to simulate device behaviour under various experimental conditions, including the effects of minority carrier injection, non-zero flatband voltage, and changes in substrate doping concentration and temperature. In addition, device parameters such as barrier height and carrier effective mass are also investigated with regard to their effect on the resultant electron and hole tunneling currents.