III-V compound semiconductors are considered promising transistor channel materials to enable scaling beyond Si technology due to their high bulk electron mobility values. However, unlike Si, III-V materials have comparatively poor quality oxides and the interface between commonly utilized high-k dielectrics and the III-V channel surface is problematic. Engineering the high-k gate stack remains one of the main technical challenges to integration of III-V materials in Si-based CMOS technology. Silicon dioxide (SiO2) forms an extremely high quality interface with Si and features a high bandgap (9eV) which effectively screens channel electrons from the effects of oxide traps in bulk high-k materials (e.g., hafnium oxide) which degrade electron mobility. However, unlike Si, III-V materials possess poor quality native oxides with a very high density of oxide traps, which thus prove unsuitable as channel dielectrics due to the resultant high density of interface states (Dit). Formation of these oxides must be prevented, making surface preclean and chemical passivation techniques critical. In addition, an alternative IL is required prior to deposition of the primary high-k dielectric to reduce the impact of oxide traps while also maintaining a low Dit. Optimization of the primary high-k deposition process itself may also be required. Due to the ultra-thin layers and moisture / oxygen sensitive materials in question, in-situ processing without air exposure throughout the gate dielectric sequence is beneficial, if not mandatory. Various approaches have been introduced to passivate the III-V surface prior to dielectric deposition to achieve reduced interface states. Sulfur passivation via immersion in wet chemical (NH4)2S solutions has been the most studied, with demonstration of promising interface properties. However, this approach is difficult to integrate into a vacuum deposition system, resulting in unavoidable air exposure time following sulfur passivation. To address the limitations of wet chemical processing, an innovative in-situ sulfur passivation approach is described here. In this approach, the sulfur precursor is delivered in vapor form from either (NH4)2S solution or compressed H2S gas cylinder in-situ to a hot walled cross flow ASM Pulsar® 3000 ALD reactor such that the high-k layers can be deposited immediately following passivation without air exposure. In-situ vapor passivation treatments yield higher [S] than solution-based passivation techniques per XPS analysis. Passivated samples exhibit improved C-V characteristics, and lower dispersion values compared to the HCl etched reference for planar MOSCAPS. The Ditvalues for in-situ passivated samples were reduced to ~1-2x1012 /cm2eV, promising for application to high mobility transistors. SiO2 is a candidate IL for III-V gate stacks due to its high bandgap and low density of oxide traps, but a high quality atomic layer deposited SiO2 film without significant channel oxidation has not been demonstrated on Si, let alone III-V materials, to date. The incorporation of Si into another metal oxide (e.g., Al2O3) is thus an interesting approach for evaluation. Two H2O-based ALD processes for aluminum silicate (Al1-xSixO) were developed using an ASM Pulsar®. Trimethylaluminum (TMA) and aluminum chloride (AlCl3), have been compared as Al precursors with silicon tetrachloride (SiCl4) as the Si precursor. The TMA-based process exhibits a measureable level of C incorporation (2-3%), while [C] in the AlCl3-based process was below detection limits due to halide chemistries utilized. Parasitic C in the TMA-based IL is projected to be a contributor to oxide defects resulting in degraded electrical performance as compared to the pure halide-based process. The impact of other factors such as deposition temperature and pulsing sequence were also studied, and the ALD growth mechanisms for these two processes are discussed in further detail. Ultimately, Al2O3-based materials and other commonly investigated high-k metal oxides appear limited in ability to meet the performance requirements for a robust III-V channel transistor, although incremental improvements have been demonstrated. As such, alternative ALD materials have been extensively explored for application to III-V channel materials. Recent development has resulted in demonstration of a low temperature thermal ALD process of a novel material which exhibits strong potential for application as IL in III-V channel devices. The IL material is also deposited using an ASM Pulsar® reactor, following S passivation and prior to deposition of HfO2 high-k bulk dielectric. Dit values <1E12, low dispersion (<1%) and hysteresis (<30 mV) values have been demonstrated. Current device performance equals previously published benchmark device metrics for InGaAs channel devices. We projected that device performance can be further improved via optimization of the in-situ passivation and ALD process parameters for the novel interface layer and bulk high-k.
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Apr 1, 2016
A Dey + 4
Open Access
