Electromigration In Copper Interconnects Research Articles

(Invited) Electrochemical Metallization For Semiconductor Applications

Initially after the invention of electroplating in 1805 it was mostly for used decorative applications and making printing press plates. But the introduction of copper as a replacement for aluminum as a CMOS interconnect material in 1997 by IBM (1) was a breakthrough in silicon chip manufacturing. The replacement of aluminum by copper not only has the benefit of lower interconnect resistance, but also has enabled improved interconnect reliability. Cu is expected to show better reliability because it has a high melting temperature and much lower grain boundary- and lattice diffusivity than aluminum (2). since electroplating is a low-cost and reliable technique, the method is being used for a wide variety of metal deposition applications in the semiconductor industry that includes interconnect & packaging metallization, and compound semiconductor fabrication for low-cost solar cells. Since the late 1990's, after IBM introduced copper interconnects, the development of the copper damascene process (1,3) and the implementation of the copper-based interconnect has had a considerable impact in the electrochemical society and semiconductor industries. Copper metallization technology has become critical for CMOS back-end interconnect, embedded multi-chip interconnect bridges, and interposers for 2.5D and 3D applications.In this presentation, after a brief discussion of the history of metallization by electrochemistry for semiconductor applications, the development of Copper, Gallium, and Cobalt Metallization will be discussed with their application in the semiconductor technology. The discussion will focus on initial issues that arose and the various directions followed to properly address them. The presentation will then focus on the challenge of barrier and seed step coverage and their impact on defects in Cu damascene metallization. Topics of discussion will include the effect of additives, current density, bath aging, shelf life and their implication on product reliability.References R, Liu, C. Pai and E Martinez " Interconnect Technology Trend for Microelectronics", Solid state Electron. 43, 1003(1999)S. Hau-Riege and C. V. Thomson, " Electromigration in copper interconnects with very different grain structures" Appl. Phys. Lett. 78, 3451 (2001)K. Broadbent, E. J. McInerney, L. A. Gochberg, and R. L. Jackson, " Experimental and Analytical study of seed layer resistance for copper damascene electroplating" J Vac. Sci. Techonl. B17, 2584(1999)

Resistometric study on electromigration failure in copper interconnects

A resistometric model based on microscopic analysis of electromigration failure mechanism is built. An extraction method for failure parameters of electromigration in copper interconnects is proposed from resistometric characteristics including the slope and step height. The results show that the failure time can be considered as the time to deplete grains at the cathode line end under a given stressing current. Two dominant failure modes with resuling slit and trench voids are observed in electromigration induced failures. The resistance curve for the trench-voiding failure mode consists of two characteristic regions,i.e., a step jump and an oblique line. The grain size and the extracted critical void length are lognormally distributed with close parameters. The variation in the slop of the oblique line in resistance curve with temperature obeys an exponential law. Activation energy of approximately 0.9 eV obtained from the resisometric model is consistent with that from Black equation.

Chemical Nature of the Thin Films that Form on SiO2/Si(100) Surfaces Upon Manganese Deposition

There has been much interest in recent years in the use of manganese for the self-formation of diffusion barriers to prevent the electromigration of copper interconnects into the underlying silicon substrate during microelectronic fabrication. However, the films resulting from the deposition of manganese on silicon wafers, which are covered by a thin native silicon dioxide layer, are complex and have not been fully characterized to date. Here we report on X-ray photoelectron spectroscopy (XPS) studies on the nature of films prepared by chemical means using methylcyclopentadienylmanganese tricarbonyl as the precursor. It was found that at the temperatures typically used for deposition, between approximately 550 and 750 K, a manganese silicate layer grows first upon reaction with the top SiO2 surface, and a thin manganese silicide film develops latter at the SiO2/Si(100) interface. The performance of these structures, of the silicide in particular, in microelectronic applications is still to be determined.

Implications of a threshold failure time and void nucleation on electromigration of copper interconnects

Electromigration results are described for a dual damascene structure with copper metallization and a low-k dielectric material. The failure times follow a 3-parameter lognormal behavior, with a threshold failure time needed to represent the entire failure distribution. We found that the threshold failure time scales differently with current density from the median time to failure, which has significant implications for making reliability predictions. It is shown that the threshold failure time corresponds to damage (presumably voids) nucleation of the electromigration process. The observed current density dependency, along with scanning electron microscopy cross sections of stressed samples and Monte Carlo simulations of failure distributions, suggests that both void nucleation and void growth should be considered for accurate modeling of the electromigration lifetime.

Analysis of Al Doping Effects on Resistivity and Electromigration of Copper Interconnects

In this paper, we investigated the effect of impurity (aluminum; Al) doping on the resistivity of damascene copper (Cu) interconnects by categorizing it into surface, grain-boundary, and impurity-scattering factors by means of a comprehensive scattering model. Segregation of Al dopant atoms to the interface of the lines increases the resistivity through increased surface scattering. Electromigration (EM)-induced Cu drift is suppressed as the Al concentration increases. The EM lifetime is improved by the suppression of Cu diffusion due to the piled-up Al at the top surface of the Cu interconnects.

Effects of width scaling and layout variation on dual damascene copper interconnect electromigration

Electromigration versus line width in the 0.12–10 μm range and the configuration of the via/line contact in dual damascene Cu has been investigated. There are two scenarios for width scaling impact on electromigration. One is the width < 1 μm region, in which the MTF shows a weak width dependence, except for the via-limited condition. The other is the width > 1 μm region, in which the MTF shows a strong width dependence. A theory was proposed to explain the observed behavior. For polycrystalline lines (width > 1 μm), the dominant diffusion paths are a mixture of grain boundary and surface diffusion. The activation energy for the dominant grain boundary transport (width > 1 μm) is approximately 0.2 eV higher than that of the dominant surface transport (width ∼ 1 μm). The derived activation energies for grain-boundary and surface diffusion are obtained from Cu drift velocity under electromigration stressing. The mechanisms governing the electromigration lifetime of interconnects leads to via interconnect design rules for maximizing lifetime being identified.

Via-Depletion Electromigration in Copper Interconnects

Via-depletion electromigration was studied under a number of conditions in a 65-nm technology. Observed failure distributions were either single mode or bimodal, depending on the structural configuration. The distribution and the time to fail for the early-fail mode of the bimodal distributions varied with linewidth, via redundancy, and via current density. Additionally, it was observed that for bimodal failure distributions, the length of the extension of the line past the via determined the fraction of early fails in the via. The bimodal behavior was suppressed by optimization of the via liner deposition process

Copper Interconnect Electromigration Behavior in Various Structures and Precise Bimodal Fitting

Copper interconnect electromigration (EM) was examined in various structures and three low-k materials (k=2.65–3.6) using advanced back-end-of-line (BEOL) technology. Various structures for testing were designed to identify the EM failure modes, and extensive failure analysis was carried out to reveal failure in the test structures. A strong current dependence of the electromigration lifetime in three-level via-terminated metal lines was shown. Moreover, different processing approaches lead to different EM behaviors and related failure modes. The weak links of the interconnect system were identified by evaluating various test structures. Multimodality in the electromigration behavior of Cu dual-damascene interconnects was studied. Both superposition and weak-link models were used for the statistical determination of lifetimes of each failure model (statistical method). Results correlated to the lifetimes of the respective failure models physically identified according to resistance time evolution behavior (physical method). A good agreement was achieved. The activation energies of failure modes were calculated. Results of this study suggest that the interface of Cu interconnects is the key factor in EM performance.

Copper interconnect electromigration behaviors in various structures and lifetime improvement by cap/dielectric interface treatment

Copper interconnect electromigration performance was examined in various structures and three low- k materials ( k = 2.65–3.6) using advanced BEOL technology. Strong current dependence effect on electromigration lifetime in three levels via terminated metal lines structure was shown. Moreover, different process approach will lead to different EM behavior and related failure mode. Multi-modality electromigration behavior of Cu dual damascene interconnects were studied. Both Superposition and Weak-Link models were used for statistical determination of lifetimes of each failure models (Statistical method). Results were correlated to the lifetimes of respective failure models physically identified according to resistance time evolution behaviors (Physical method). Good agreement was achieved. Various testing structures are designed to identify the EM failure modes. Extensive failure analysis was carried out to understand the failure phenomena of various test structures. The activation energies of failure modes were calculated. The weak links of interconnect system were also identified. A significant improvement of electromigration (EM) lifetime is achieved by modification of the pre-clean step before cap-layer deposition and by changing Cu cap/dielectric materials. A possible mechanism for EM lifetime enhancement was proposed. Cu-silicide formation before cap-layer deposition and adhesion of Cu/cap interface were found to be critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to electromigration MTF and activation energy. Results of present study suggest that interface of Cu interconnects is the key factor for EM performance for advanced BEOL technology design rules.

Dependence of copper interconnect electromigration phenomenon on barrier metal materials

Dependence of copper interconnect electromigration phenomenon on barrier metal materials

Surface electromigration in copper interconnects

RF-magnetron sputter deposited copper films have been characterised in terms of microstructure, stress and resistivity. The electromigration behaviour of this copper has been compared to that of sputtered aluminium. Atomic Force Microscopy has been used to study the void sites. The morphology of the damaged regions, together with the microstructural information, has been used to gain an insight into the mechanism by which electromigration voiding proceeds. The observed void sites in copper are entirely different from those in aluminium; hence a different failure mechanism must be responsible. The voiding process for copper can be explained by a grain-boundary grooving model, and it was observed that surface impurities controlled the damage mechanism and the resulting void morphology.