Electrical Parasitics Research Articles

Impact of Device Topology on the Performance of High-Speed 1550 nm Wafer-Fused VCSELs

A detailed experimental analysis of the impact of device topology on the performance of 1550 nm VCSELs with an active region based on thin InGaAs/InAlGaAs quantum wells and a composite InAlGaAs buried tunnel junction is presented. The high-speed performance of the lasers with L-type device topology (with the largest double-mesa sizes) is mainly limited by electrical parasitics showing noticeable damping of the relaxation oscillations. For the S-type device topology (with the smallest double-mesa sizes), the decrease in the parasitic capacitance of the reverse-biased p+n-junction region outside the buried tunnel junction region allowed to raise the parasitic cutoff frequency up to 13–14 GHz. The key mechanism limiting the high-speed performance of such devices is thus the damping of the relaxation oscillations. VCSELs with S-type device topology demonstrate more than 13 GHz modulation bandwidth and up to 37 Gbps nonreturn-to-zero data transmission under back-to-back conditions at 20 °C.

Characterization of Alumina Ribbon Ceramic Substrates for 5G and mm-Wave Applications

A recently developed material technology at Corning Inc., namely, Alumina Ribbon Ceramic (ARC), is investigated as a potential substrate candidate for fifth generation (5G) and millimeter-wave (mm-wave) applications. In this article, we characterize an 80- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -thick ARC substrate material in the frequency range of 3–50 GHz using microstrip ring resonator (MRR) method and extract the loss of various planar transmission lines, such as microstrip and coplanar waveguide (CPW) lines on ARC substrate up to 50 GHz as well. Moreover, different test structures designed on an 80- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -thick ARC substrate are utilized to extract the electrical parasitics associated with a single-grounded through-alumina via (TAV) and transmission properties of ground–signal–ground (GSG) TAV of 40 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> diameter over the frequency range of 0.1–50 GHz. The semiadditive patterning (SAP) process is employed to metallize the top and bottom layers of ARC substrate to form the copper traces for the designed structures. Combined with the previous characterization results of a 40- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -thick ARC substrate in 30–170 GHz, the dielectric constant of ARC was extracted to be ~10.12 over 3–170 GHz, while its loss tangent varies in the range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.6\times 10^{-5}-1.3\times 10^{-3}$ </tex-math></inline-formula> over the same frequency band. The average measured insertion loss of CPW lines varied from 0.026 to 0.24 dB/mm over 3–170 GHz. For the microstrip lines, the average measured insertion loss over the same frequency range was extracted to be between 0.019 and 0.293 dB/mm. Furthermore, the parasitic inductance and resistance of a single-grounded TAV are extracted to be 24.41 pH and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.987~\Omega $ </tex-math></inline-formula> , respectively, at 50 GHz, and the insertion loss per a GSG-TAV extracted from CPW-TAV daisy chain measurements is found to be 0.056 dB at 50 GHz as well. In addition to an excellent performance of ARC-based interconnects, the TAV in ARC is shown to have lower transmission loss up to 50 GHz, while exhibiting low parasitics.

Parasitic Parameters Extraction of High-Speed Vertical-Cavity Surface-Emitting Lasers

Parasitic parameters, including electrical capacity and inductance, are the key limiting factors for bandwidth improvement of high-speed vertical-cavity surface-emitting lasers (VCSELs). The traditional parasitic extraction method, which uses a first-order low-pass filter transfer function, is oversimplified, and there are large deviations between the obtained data and the actual measured data. In this paper, we proposed a modified parasitic extraction method that described the extrinsic behaviour of the high-speed oxide-confined VCSELs well and easily extracted the values of all parasitic parameters. This method can also precisely fit microwave reflection coefficient S11 data even at high frequencies and provide design guidance for high-speed VCSELs. Using this method, a high-speed 850 nm VCSEL featuring a six-layer oxide aperture with −3 dB bandwidth up to 23.3 GHz was analysed. The electrical parasitics have been systematically extracted from VCSELs with different oxide apertures. The enhanced bandwidth based on the improvement of parasitic parameters was discussed. It was found that the critical parasitic factors that affect the −3 dB bandwidth of VCSELs are pad capacitance and inductance.

Embedded-Component Planar Fan-Out Packaging for Biophotonic Applications

Embedded-chip planar silver-elastomer interconnect technology is developed with flexible substrates and demonstrated for on-skin biophotonic sensor applications. This approach has several benefits and is also consistent with chip-thinning where the chip thickness is 100 microns and less. The key benefits from this approach arise because both the bottom and top sides are now available as flat surfaces for 3D integration of other components. It also results in the lowest electrical parasitics compared to flipchip with adhesives or printed-ramp interconnections with surface-assembled devices. Embedding of chips in flexible carriers was accomplished with direct screen-printed interconnects onto the chip pads in substrate cavities. Silver nanoflake-loaded polyurethane is utilized in the embedded-chip packages to provide the desired lower interconnect resistance and also reliability in flexible packages under deformed configurations. Viscoelastic models were utilized to model the interconnection stresses. Planar interconnects in flexible substrates are developed with conductive silver-loaded elastomer interconnects. This approach is compared to direct chip-on-flex assembly technology for reliability under bending and high-temperature storage. The embedded-chip technology is demonstrated through biophotonic sensor applications where light sources (LEDs) and photodetectors are embedded inside the package. Functional validation in bent configuration at low curvatures is shown by measuring pulse rate and muscle activity with human subjects. By extending this technology to nanowires in elastomers, further enhancement in electrical and reliability performance can be achieved.

Maximizing Performance of Microelectronic Thermoelectric Generators With Parasitic Thermal and Electrical Resistances

Microelectronic thermoelectric (TE) generators ( $\mu $ TEGs), which are one potential solution to powering energy autonomous integrated circuits (ICs), are often performance limited because of parasitic electrical and thermal resistances in the $\mu $ TEG circuit. Parasitic performance loss can be particularly severe for $\mu $ TEGs using materials with relatively low TE figure-of-merit, such as silicon (Si). In such cases, careful attention must be paid to optimizing the entire $\mu $ TEG circuit, not just the TE material properties. Here, a quantitative model of $\mu $ TEG device performance is developed that includes all significant electrical and thermal parasitics commonly encountered in IC-compatible $\mu $ TEGs. The model gives a pair of coupled quadratic equations that can be analytically or numerically solved to determine power generation and efficiency. For given parasitic resistance and material property values, the model shows that the ratio (called here the packing fraction) of cross-sectional area occupied by TE elements to total cross-sectional area for heat flow per thermopile can be designed to maximize either power or efficiency, but not both simultaneously. For realistic material and device parameters, the optimum packing fraction is often only 1%–10%, lower than what is used in many $\mu $ TEG designs. The model accounts for the reported power generation of some example $\mu $ TEGs and provides guidance toward significant performance improvement.

Large-Signal Equivalent Circuit for Datacom VCSELs

Increasing the baud rate in optical interconnects (OIs) will require the use of more sophisticated driver and receiver electronics. This will help overcome the stagnated bandwidth of the Vertical-Cavity Surface-Emitting Laser (VCSEL) and the pin-photodetector. Next generation OIs operating at single lane rates of 50+ Gbaud will therefore require careful co-optimization of the electronics and the optoelectronics. To facilitate this work there is a need of an accurate equivalent circuit for the optoelectronic components, functioning over a broad drive current and ambient temperature range. The VCSEL is the most important and complex to model due to its non-linear behavior and strongly varying characteristics with drive current and ambient temperature. For this purpose, a large-signal equivalent circuit dedicated for high-speed datacom VCSELs has been developed and is presented here. The distributed electrical parasitics in the device layout are carefully considered, the intrinsic speed limitation from carrier transport effects in the Separate-Confinement-Heterostructure (SCH) and the carrier-photon interaction in the Quantum Wells (QWs) are included, and self-heating effects in the device are monitored. The circuit is purposely based on physical instead of empirical models so that it can provide usable feedback to VCSEL designers. For circuit demonstration, it is implemented in Keysight's Advanced Design System (ADS) software and thereafter applied to replicate the performance of a state-of-the-art 28-GHz-bandwidth VCSEL at different temperatures and drive currents. Comparison is made between simulated and measured steady-state characteristics, small-signal behavior, and large-signal response under 28 Gbaud On-Off-Keying (OOK) and Pulse-Amplitude-Modulation 4 (PAM4) modulation, showing good agreement.

Mode-field switching of nanolasers

Due to their small sizes and low threshold, nanolasers play a pivotal role in the field of low-energy scalable photonic technologies. High-speed modulation of nanolasers is needed for their application in data communication, but its implementation has been hampered by the small scales involved, leading to large electrical parasitics. Here we experimentally demonstrate the proof-of-principle of a novel modulation technique, namely, mode-field switching, which unlocks the control of the laser operation via the modulation of the electromagnetic field. In particular, we show that stimulated emission can be inhibited by switching the lasing mode from bright to dark in a three-coupled cavity system. The experimental results are in good agreement with a model that combines coupled-mode theory and rate equations. Using this model, we show that time-dependent detuning schemes enable storage and release of energy under the form of short pulses, placing mode-field switching among the techniques for laser modulation and pulse generation. This scheme is general and can be implemented in every platform displaying coupled and tuneable resonances.

Overview of Digital Design and Finite-Element Analysis in Modern Power Electronic Packaging

Wide band gap (WBG) semiconductors require packaging with reduced parasitic inductance and capacitance. To achieve this, new packaging solutions are proposed that increase integration. This causes difficulty in measurement of voltages, currents, and device temperature, and therefore, designers must rely more heavily on simulations to gain insight in the operation of the developed prototypes. Additionally, the use of the digital design may reduce the number of physical prototype iterations, and thereby, reduces the development time. Gaining fidelity of three-dimensional multiphysics simulations, reduced order modeling, and system simulation aids in the design of working prototypes and pushes performance of new power modules based on WBG semiconductor devices. This article provides an overview and discusses the recent advances in the use of finite-element analysis and simulation tools within the topic of power module packaging. The main aspects covered are extraction of electrical parasitics, simulation of transient thermal response, and issues related to evaluation of electric fields. An example of a simulation software roadmap is presented that enables accurate electro-thermal simulation of new packaging structures that combine the conventional power module technology with integrated printed circuit boards. The future challenges for utilizing the potential of the digital design are discussed.

Deformable Interconnects with Embedded Devices in Flexible Fan-Out Packages

Abstract A new class of interconnects that exhibit resilience to mechanical deformation are demonstrated with flexible fan-out or embedded-die packages. Active device embedding in flexible substrates is accomplished with direct printed interconnects onto die pads. Such a planar fan-out interconnect technology with a low-cost manufacturable process-flow results in the lowest electrical parasitics compared to flipchip with adhesives or printed-ramp interconnections with surface-assembled devices. The interconnects are made with conductive flexible silver-elastomer composites to sustain elastic deformation. The process is also modified to realize flexible backside-assembled fan-out interconnections where the backside of the die is accessible.

Electro-Absorption Modulator Vertically Integrated on a VCSEL: Microstrip-Based High-Speed Electrical Injection on Top of a BCB Layer

Vertical-cavity surface-emitting lasers with vertically integrated electro-absorption modulators (EAM-VCSELs) potentially can reach higher modulation bandwidths than directly current-modulated VCSELs. The aforementioned device modulation capabilities are, however, currently restricted by their electrical contact parasitics. It, thus, becomes critical to optimize their access line to improve performance. In this paper, we numerically and experimentally demonstrate that a microstrip (MS) access line using a planarized benzocyclobutene (BCB) layer exhibits improved high-frequency characteristics compared to the coplanar waveguide (CPW) access line used to-date, since it reduces the losses induced by the doped substrates. We also use this opportunity to introduce an innovative technique for BCB layer planarization, which is not only compatible with the EAM-VCSEL double-mesa structure, but is also independent of the device pitch. The resulting BCB layer dielectric permittivity and losses are measured up to 100 GHz, and a side-by-side comparison of the electrical response of three-electrodes MS and CPW access lines is subsequently carried out. Finally, using the measured pad and access line RF responses and the EAM modulation characteristics, the devices with MS access are shown to be no longer limited by their electrode parasitics, but by the modulator internal impedance.

PowerSynth: A Power Module Layout Generation Tool

PowerSynth is a multiobjective optimization tool for rapid design and verification of power semiconductor modules. By using reduced order models for the calculation of electrical parasitics of the layout and thermal coupling between devices, optimal trace layout and die placement can be simultaneously achieved orders of magnitude faster than conventional finite element analysis (FEA) techniques. An overview of the tool, its modeling methods, model validation, and module layout optimization are presented. The electrical and thermal models are validated against FEA simulations and physical measurements of built modules generated from the tool. The FEA comparisons are performed with FastHenry and ANSYS Icepak to evaluate electrical parasitics and thermal behavior, respectively. A sample hardware prototype based on a half-bridge circuit topology is chosen for testing. Excellent agreement between the FEA simulations, experimental measurements, and PowerSynth predictions are demonstrated. Additionally, when compared with conventional simulation runtime and workflow, PowerSynth takes considerably less computation and user time to produce several candidate layout solutions from which a designer may easily balance selected tradeoffs.

A Compact Model for Si-Ge Avalanche Photodiodes Over a Wide Range of Multiplication Gain

Silicon-germanium (Si-Ge) avalanche photodiodes (APDs) have superior gain bandwidth product due to the low impact ionization ratio of silicon. To enable efficient optical transceiver systems, cosimulation environments are essential for optimization of optical devices and transceiver circuitry. A compact Si-Ge APD circuit model, which captures both electrical and optical dynamics over a wide range of multiplication gain, is presented. This model includes effects of carrier transit time, avalanche buildup time and electrical parasitics. Model parameters are extracted by small-signal measurement and impulse response measurement where three gain regimes are discussed corresponding to the different mechanisms of carrier transit time and electrical parasitics. Simulated and measured bandwidth versus gain have a good agreement for APD multiplication gains from M = 1 to M = 17. Excellent matching between simulated and measured 25 Gb/s eye diagrams at M = 2 and M = 5.9 is achieved.

Comprehensive vertical-cavity surface-emitting laser model for optical interconnect transceiver circuit design

Directly modulated vertical-cavity surface-emitting lasers (VCSELs) are commonly used in short-reach optical interconnect applications. To enable efficient optical interconnect transceiver systems operating at data rates up to 25 Gb/s and beyond, cosimulation environments, which allow for the optimization of driver circuitry with accurate compact VCSEL models, are necessary. A comprehensive VCSEL model, which captures thermally dependent electrical and optical dynamics and provides direct current, small-, and large-signal simulation capabilities with self-consistency, is presented. The device’s electrical behavior is described with an equivalent circuit, which captures both large-signal operation and electrical parasitics, while the optical response is captured with a rate-equation-based model. Bias and temperature dependencies are incorporated into both key electrical and optical model parameters. Experimental verification of the model is performed at 25 Gb/s with a 990-nm VCSEL to study the impact of bias current level and substrate temperature.

Mixed Array of Compliant Interconnects to Balance Mechanical and Electrical Characteristics

Various designs of compliant interconnects are being pursued in universities and industry to accommodate the coefficient of thermal expansion (CTE) mismatch between die and substrate or substrate and board. Although such interconnects are able to mechanically decouple the components, electrical parasitics of compliant interconnects are often high compared to the electrical parasitics of solder bump or solder ball interconnects. This increase in electrical parasitics is due to the fact that compliant interconnects typically having longer path lengths and smaller cross-sectional areas to provide compliance, which in turn, increases their electrical parasitics. In this paper, we present a mixed array of compliant interconnects as a tradeoff between mechanical compliance and electrical parasitics. In the proposed implementation, the die area is subdivided into three regions where high compliance, medium-compliance, and low-compliance interconnect variants are situated in the outer, middle, and inner regions of the die, respectively. By introducing the low-compliance variants into the assembly, interconnects with greatly reduced electrical parasitics can be used as power/ground interconnects, while the high-compliance interconnects, situated near the die edges, can be used as signal interconnects. This paper demonstrates the implementation of this configuration and also presents the experimental characterization of such heterogeneous array of interconnects.

Ultrasonic fingerprint sensor using a piezoelectric micromachined ultrasonic transducer array integrated with complementary metal oxide semiconductor electronics

This paper presents an ultrasonic fingerprint sensor based on a 24 × 8 array of 22 MHz piezoelectric micromachined ultrasonic transducers (PMUTs) with 100 μm pitch, fully integrated with 180 nm complementary metal oxide semiconductor (CMOS) circuitry through eutectic wafer bonding. Each PMUT is directly bonded to a dedicated CMOS receive amplifier, minimizing electrical parasitics and eliminating the need for through-silicon vias. The array frequency response and vibration mode-shape were characterized using laser Doppler vibrometry and verified via finite element method simulation. The array's acoustic output was measured using a hydrophone to be ∼14 kPa with a 28 V input, in reasonable agreement with predication from analytical calculation. Pulse-echo imaging of a 1D steel grating is demonstrated using electronic scanning of a 20 × 8 sub-array, resulting in 300 mV maximum received amplitude and 5:1 contrast ratio. Because the small size of this array limits the maximum image size, mechanical scanning was used to image a 2D polydimethylsiloxane fingerprint phantom (10 mm × 8 mm) at a 1.2 mm distance from the array.

Recent advances in electromagnetic compatibility of 3D-ICs &amp;2013; Part I

Electromagnetic interference (EMI) issues are becoming crucial for three-dimensional integrated components which combine multi-core Systems-On-Chip, multi-band radio frequency circuits (RF), Giga-bit memories, as well as advanced analog circuits. In this first paper, the technology roadmap towards 3D-ICs is illustrated and the associated EMC challenges are described. This first paper also focuses on the role of interposers, associated electrical parasitics, and addresses concerns about signal and power integrity.

High temperature thermoreflectance imaging and transient Harman characterization of thermoelectric energy conversion devices

Advances in thin film growth technology have enabled the selective engineering of material properties to improve the thermoelectric figure of merit and thus the efficiency of energy conversion devices. Precise characterization at the operational temperature of novel thermoelectric materials is crucial to evaluate their performance and optimize their behavior. However, measurements on thin film devices are subject to complications from the growth substrate, non-ideal contacts, and other thermal and electrical parasitic effects. In this manuscript, we determine the cross-plane thermoelectric material properties in a single measurement of a 25 μm InGaAs thin film with embedded ErAs (0.2%) nanoparticles using the bipolar transient Harman method in conjunction with thermoreflectance thermal imaging at temperatures up to 550 K. This approach eliminates discrepancies and potential device degradation from the multiple measurements necessary to obtain individual material parameters. In addition, we present a strategy for optimizing device geometry to mitigate the effect of both electrical and thermal parasitics during the measurement. Finite element method simulations are utilized to analyze non-uniform current and temperature distributions over the device area as well as the three dimensional current path for accurate extraction of material properties from the thermal images. Results are compared with independent in-plane and 3ω measurements of thermoelectric material properties for the same material composition and are found to match reasonably well; the obtained figure of merit matches within 15% at room and elevated temperatures.

Investigation of Dual Electrical Paths for Off-Chip Compliant Interconnects

This paper presents a study on a dual-path compliant interconnect design which attempts to improve the balance between mechanical compliance and electrical parasitics by using multiple electrical paths in place of a single electrical path. The high compliance of the parallel-path compliant interconnect structure will ensure the reliability of low-K dies. Implementation of this interconnect technology can be cost effective by using a wafer-level process and by eliminating the underfill process. Although an underfill is not required for thermomechanical reliability purposes, an underfill may be used for reducing contamination and oxidation of the interconnects and also to provide additional rigidity against mechanical loads. Therefore, this paper also examines the role of an underfill on the thermomechanical reliability of a dual-path compliant interconnect.

THIN FILM THERMOELECTRIC CHARACTERIZATION TECHNIQUES

The key thin film thermoelectric characterization techniques are described. Due to the small dimensions, a careful examination of electrical and thermal paths in the device is necessary. We describe both in-plane and cross-plane measurement methodologies. Sample requirements for four-probe and van der Pauw methods for in-plane electrical conductivity measurement are discussed. The in-plane Seebeck coefficient is characterized under a temperature gradient which generates a voltage. Precise measurements of temperature and voltage at the same location in the sample are very important. For the cross-plane electrical conductivity, the modified transmission line method is evaluated. To eliminate parasitic contact and substrate resistances, several samples with varying thicknesses are required. Two approaches, a DC method and the 3ω method, are described in detail for the cross-plane Seebeck coefficient characterization. Next, we focus on the transient Harman method to directly measure the cross-plane thermoelectric figure of merit of a thin film. The device requirements for reducing parasitic heat losses and current nonuniformity are presented. Thermoreflectance imaging can be used together with transient Harman in order to extract electrical and thermal conductivities and the Seebeck coefficient simultaneously. Finally, Z-meters are described for directly determining the figure of merit and efficiency of a thermoelectric element or module under a large temperature gradient. Recent developments have significantly reduced thermal and electrical parasitics, as well as radiation heat loss in the system, enabling ZT measurement of legs as thin as one hundred microns.

Thermally and Electrically Enhanced Wirebond BGA

Next-generation processors continue to demand more thermal and electrical performance from the package. Frequently, devices are designed into Flip Chip (FC) packages where the previous generations were in Wire Bond (WB) because FC typically provides superior thermal dissipation and lower package electrical parasitics than WB packages. However, FC packages usually have higher costs for mid-range IO (500–800). An Enhanced WB BGA package has been designed with improved thermal and electrical performance compared to the industry standard TEPBGA-2 (Thermally Enhanced PBGA type 2). The 500μm barrier of mold compound between the die and heatspreader in the TEPBGA-2 is a major impediment to heat flow out of the package. By contrast, the Enhanced WB package uses post-mold attachment of a heat spreader that is adhesively bonded to the mold cap and thermally coupled to the die using a 40μm TIM (thermal interface material). Improvements to substrate design rules and the die attach process that enabled the Enhanced WB design to shorten bond wires by 40% and improved electrical performance. Package thermal resistance, Theta-Ja, was verified by simulation and measurement to be 3C°/W lower than TEPBGA-2, that dissipates up to 15W in some end-use applications, approximately 2× the performance of TEPBGA-2. DDR set-up and hold time showed 30ps improvement by both simulation and measurement. This paper will present the package design, thermal and electrical simulation and measurement results.