Electrical Failure Analysis Research Articles

Gate breakdown induced stuck bits in sub-20 nm FinFET SRAM

This paper discusses the stuck bits induced by the gate breakdown of PMOS in the sub-20 nm FinFET static random access memory (SRAM) device. After the heavy-ion experiment, several stuck bits are in the FinFET SRAM matrix, which cannot be set or reset. To investigate the factors that caused the stuck bit, we perform the electrical failure analysis (EFA) to measure the electric characteristics of the transistors in the stuck bits and normal cells separately. The measurement results show a clear gate breakdown at the PMOS pull-up (PPU) transistor in all of the measured SRAM cells. Meanwhile, the SPICE simulation based on the EFA results verifies the impact of the damaged PPU. Finally, considering all of the phenomena, the charge deposition from single events is the major mechanism that causes the stuck bits in FinFET SRAM. The experiment results alert a potential gate breakdown risk in the ultra-high-density FinFET SRAM applied in the space environment.

Research on cascading effect analysis of civil aircraft electrical power system failures

Abstract Cascade effect analysis is a qualitative analytical method recommended by SAE ARP 4761A [1] for evaluating complex integrated civil aircraft systems. The Electrical Power System (EPS) is one of the critical onboard systems. It can provide electrical power to the avionics system, flight control system, and other critical systems on the aircraft, and it has a wide range of failure effects. The consequences of EPS failure effects are difficult to determine. This paper applies the cascading effect analysis method to carry out the qualitative safety assessment of the EPS on the aircraft and finally confirms that the architectural design of the EPS met the safety design requirements. It also gives the engineering method (such as test, MBSA) suggestion to further check and verify the correctness and completeness of the theoretical analysis of CEA.

Failure mechanism of 4H-SiC junction barrier Schottky diodes under harsh thermal cycling stress

The concern in the long-term reliability of the SiC power devies is raised lately in power electronic field due to its brief history and limited data. In this work, discrete 1200 V/20A SiC JBS diodes have been intensively investigated by HTRB, HAST, and TCT. 2 % samples have failed in the harsh thermal cycling test, showing that the failure mechanism is attributed to field-oxide cracking. The electrical and physical failure analysis pointed out that a gradual degradation occurred at the termination structure, causing non-recoverable damages and provoking a significant increase in the leakage current. The FIB cut and SEM analysis showed the delamination existence between field oxide layer and silicon carbide layer in the degraded devices. The observed leakage current after the TCT could be well correlated with the formation of the delamination, which created a current leaking path between active and termination region. These findings emphasize the importance of SiO2/SiC interface quality in the long-term highly reliable SiC power devices, and indicate further optimized design of SiO2 passivation layer or other alternative materials is urgently needed to overcome this structural weakness.

New Erratic Program Disturbance Mechanism of 2T-SONOS Embedded Nonvolatile Memory

We developed a 32 kB embedded nonvolatile memory (NVM) intellectual property (IP) using 2T-SONOS cells. Although SONOS cells possess intrinsic defect immunity, we discovered abnormal memory cell failure during the probe test of the IP. The major failed items are checkerboard (CKBD), inverse CKBD, and gate-with-source (G-S) disturbance at the erased state. The threshold voltage distributions and electrical failure analysis (FA) reveal that all major failures occurred because of an abnormally weak G-S disturbance immunity. In addition, the temperature dependency of the G-S disturbance implies that the failure mechanism is related to Co-spike rather than midgap trap-induced junction leakage. Although abnormal defects are not detected through physical FA, by using simple failure modeling and a process split test, we verified the root cause of a new type of erratic failure. The single-bit disturbance failure can be explained as electrons generated in the floating junction area being accelerated in the G-S stress mode, resulting in soft programming by the channel hot electron (CHE) injection mechanism.

Low Voltage Time-Resolved Emission (TRE) Measurements of VLSI Circuit

Advanced technology nodes with small feature sizes and increased design complexity make it increasingly time-consuming to determine the root cause of yield loss. Several of the defects also occur inside a circuit making physical failure analysis (PFA) and electrical failure analysis (EFA) much more challenging. EFA has been instrumental in driving product yield and reliability for consumer products such as mobile phones and computer chips. It involves the use of state-of-the-art tools and techniques. One of the main changes EFA analyses is an enhancement of dynamic EFA in circuit failed in functional test. We propose a technique for advanced Electrical Failure Analysis (EFA) tool with a Superconducting Nanowire Single Photon Detector (SnSPD) system and its application to low voltage Time-Resolved Emission (TRE) measurements (also known as Picosecond Imaging Circuit Analysis, PICA) of scaled VLSI circuits with enhanced sensitivity for discussing Time Resolved Emission (TRE). In order to understand the figures of advantage that a single-photon detector should have to enable the acquisition of time resolved emission waveforms for low voltage applications. We will provide that measurements down to a low 1 V supply voltage were made possible by a careful optimization of the detector front-end electronics. We also characterized the emission from devices with different threshold voltages in order to understand how the emission contributions depend on this parameter and how this affects the resulting waveform. we hope to be able to show soon even better results that should allow continued application of the non-invasive TRE and PICA technology towards future scaled nodes with smaller gates and lower supply voltages.

Novel failure traces beyond the barrier on the floating device

Failure Analysis (FA) on Fully Depleted Silicon on Insulator (FDSOI) device is challenging due to its unique structure with buried oxide layer. Typical failure analyses for the bulk device are not viable to isolate the fault location as the first step for the defect finding any more in such a FDSOI environment. Based on the in-depth study on structural limitation of the FDSOI device, this paper firstly reports novel approaches for the physical and electrical FA methodologies with the success stories for yield learning. Furthermore, we demonstrate the improvements of FA methods compared to the conventional ones and how new ideas are applied to the analysis procedure including the minute soft defect FA.

Cost-Effective and Time-Efficient Failure Analysis Method for Yield Enhancement Utilizing Picked Sawn Wafer

Electrical and physical failure analyses have played a key role in the yield enhancement of large-scale integrated circuits. However, the growing cost of product wafers has progressively hindered their use for analysis, depending on the shrinkage of device dimensions. To overcome these difficulties, we propose a new analytical style that uses the remaining dies on a sawn wafer after all the good dies have been picked and taken for assembly. We call the resulting structure a “skeleton-wafer”. In the present study, we have developed a testing system that can handle a skeleton-wafer in the same manner as a conventional wafer. Basically, skeleton-wafer testing is performed at room temperature, given that commonly used dicing tapes have low heat-resistance. We have also developed a sophisticated method that enables analytical testing on the remaining dies at high temperature. A case example achieves high throughput and good contact characteristics, enabling the developed system to be of practical use in high-volume electrical failure analysis. We illustrate how our analytical testing system has improved cost-effectiveness and time-efficiency in yield enhancement activity.

Comparative electrical performance and failure analysis of air-annealed ruthenium Schottky contacts on 6H-SiC and 4H-SiC

Thin films of ruthenium (Ru) on 6-hexagonal silicon carbide (6H-SiC) and 4-hexagonal silicon carbide (4H-SiC) were analysed by Rutherford backscattering spectroscopy (RBS) at various annealing temp...

Analysis of electrical lead failures in patients referred for transvenous lead extraction procedures

We evaluated the influences of selected factors on electrical lead failure (ELF) occurrence in patients referred for transvenous lead extraction (TLE) procedures. The study cohort consisted of 432 patients referred for TLE procedures due to various indications (42 - lead-dependent infective endocarditis, 47 - pocket infection, 343 - noninfectious indications) with a total of 804 endocardial leads. In the analyzed group, there were 192 patients with ELF, denoted as group ELF(+) (200 malfunctioning endocardial leads). The percentage of women was higher in the ELF(+) group than in the ELF(-) group (42.7%vs 30.0%; P=0.006). The ELF(+) patients had more endocardial leads implanted via subclavian vein puncture (80.0%vs 72.4%; P=0.032), had more indwelling leads in the cardiovascular system (1.94vs 1.8; P=0.03), were older (68.9vs 66.0 years old; P=0.028), and had better left ventricular ejection fractions than the ELF(-) patients (48.0%vs 40.7%; P<0.001). The time interval to ELF occurrence was significantly longer for pacing leads than for cardioverter-defibrillator leads (95.7vs 65.7 months; P=0.016). The most important factor associated with ELF was subclavian vein puncture, increasing the risk of ELF occurrence by 2.5-fold and 2.7-fold in the univariate and multivariate Cox proportional hazards regression models, respectively. The presence of a cardioverter-defibrillator lead increased the risk of ELF by 1.9-fold and 2.7-fold in the univariate and multivariate models, respectively. The most significant factors predisposing patients to ELF are the lead implantation approach and the presence of a cardioverter-defibrillator lead.

Analysis of electrical motor mechanical failures due to bearings

Regardless of the high operational reliability of modern ball and roller bearings and advanced methods for their selection and durability calculation, a significant proportion of the failures in the electric motors, about 51% [1], are of mechanical nature. Often, mechanical damage leads to irreversible engine states and costly replacement. Careful theoretical analysis of bearing failures may indicate the root causes of their defects mainly from external for the bearings surface factors and to recommend proper preventive actions. Damage cause can undoubtedly refer to the way in which significant mechanical energy generated in the rotor is transmitted, most often through belt drives or elastic couplings, while the bearings themselves withstand the significant reaction forces that have occurred. A model analysis will be performed to reveal the interconnection of the mechanical power output of an electric motor via belt drive or an elastic coupling to the internal loads and friction of supporting ball or roller bearings. In addition, a suitable lubrication regime for bearings will be examined according to different types of bearings, shaft speed and temperatures.

Efficient defect identification of soft failures induced by device local mismatch for nano-scale SRAM yield improvement

As the device size continues shrinking to nano-scale region, tiny defects induced device local mismatch in SRAM array becomes a major yield limiter. It is often quite time consuming and challenging to identify such kind of invisible defects through conventional FA techniques. This paper presents an efficient methodology on device local mismatch fault isolation with the combination of test features, advanced Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA) techniques. A successful case study involving this advanced methodology will be also discussed.

Cross-sectional nanoprobing fault isolation technique on submicron devices

With continuous scaling on CMOS device dimensions, it is becoming increasingly challenging for conventional failure analysis (FA) methods to identify the failure mechanism at the circuit level in an integrated chip. Scanning Electron Microscopy (SEM) based nanoprobing is becoming an increasingly critical tool for identifying non-visual failures via electrical characterization in current electrical FA metrology for fault isolation since 2006 Toh et al. (2007), Shen et al. (2007), Ng et al. (2012) . Currently, most of the nanoprobing fault isolation is nanoprobe in top-down planar direction, such as nanoprobe on via, contact and metal line. This paper focused on fault isolation of sub-micron devices by nanoprobing on a cross-sectional plane. This is a new application area; it is very useful for sample that cannot perform fault isolation with conventional top-down planar nanoprobing, especially on non-volatile memory that with single transistor memory array that arrange in a vertical direction, such as Magnetic Random Access Memory (MRAM), Phase-Change Random Access Memory (PC-RAM), flash memory and etc.

A Marginal Isolation Failure Caused by Thin Film Quality Issue Analysis in a 45nm Logic Process

On a 45nm logic product that suffered special pattern function failure, electrical failure analysis identified the failure as soft failure and localized the failure addresses. PVC (Passive Voltage Contrast) was used to narrow down suspected process steps to M1 or below layers, FIB (Focus Ion Beam) and TEM (Transmission Electronic Microscope) approaches were used to identify the actual root cause and failure mechanism.

Contoured device sample preparation technique for ±5 μm remaining silicon thicknesses that meets solid immersion lens requirements

Electrical failure analysis toolsets continue to develop at a pace significantly faster than sample preparation techniques. New solid immersion lenses (SIL) have been developed that require tighter requirements in remaining silicon thickness (RST) variation. Due to the SIL requirements, well established sample preparation techniques are quickly becoming ineffective, and new techniques/tools are required. In this paper, we will present a new methodology for preparing contoured devices by utilizing a contour capable milling system with an incorporated spectral reflectance measurement tool to enable contour correction milling based on remaining silicon thickness. This technique has demonstrated the capability of meeting 50μm (or other desired target thickness) ±5μm remaining silicon thickness requirement as requested by the SIL manufacturers.

Foundry workflow for dynamic-EFA-based yield ramp

The increasing demand for electrical failure analysis (EFA) in yield enhancement [1] has created new challenges for foundries and their clients. Dynamic EFA techniques, more in demand with the smaller technology nodes, have largely been the domain of the design-house failure analysis (FA) lab. In 2010 on 40nm packaged parts, a new laser-based technology, laser voltage imaging (LVI) was applied to shift debug and drove physical failure analysis (PFA) success rate to >90%. This is still the case in 2011 on 28nm ICs. The methodology was validated at the foundry on 32nm wafers and again drove the PFA success rate to >90%. This paper offers a foundry-friendly methodology made possible by LVI and its fast track to the wafer level.

Single pulse energy capability and failure modes of n- and p-channel LDMOS with thick copper metallization

Electro-thermal destruction of n- and p-channel lateral double-diffused MOS in smart power ICs is investigated by electrical pulse experiments, simulations and failure analysis. It was observed experimentally and by TCAD simulation that the location of the hot spot plays very important role for single pulse energy capability. Damage both in silicon and copper metallization was observed. The n-DMOS exhibits better energy capability compared to p-DMOS due to better cooling efficiency of silicon area by the copper metallization. Effect of drift region length, doping profile and of copper metal thickness on energy capability is also analyzed.

Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration

A wide range of requests coming from customer appears to demonstrate the feasibility of the TSV for a large range of via size and via AR either for process point of view or for performances point of view. The main application in the market is the CMOS image sensor with the integration of via at AR1. Now based on this first wafer level package of CMOS Image Sensor (CIS), the integration on the z axe will continue by the wafer lens integration for a continuous form factor and low cost module. First 3Di applications with TSV is entering the market with the via-last approach, more simply to be developed in semiconductor manufacturing in order to secure the 3Di technologies and to promote the 3Di to customers. Then specific design and electrical models will be developed and optimized allowing a fast and prosperous development of the via-first approach. A challenge in the modelisation of the TSV is the understanding of the mechanical impact of the trench and the metal filling on the behavior of the CMOS components and the reliability. These types of researches are progressing in various institutes and are essential for an increasing integration of TSV. Because actually, the technology continues to drive the 3D roadmap, the mechanical and thermal modelisation and 3D design tool need to be more activated to be developed faster in order to optimize the 3D module. Then the electrical testing will be a real challenge to be able to distinguish drift in the right strata, to be able to isolate a via within more than 10000 via in a module. The electrical testing will be strictly linked to mechanical and electrical failure analysis to get feed-back in technology, actual drawback of the 3D development. The cost of the 3Di and the TSV integration is more and more important and looks as a primary driver even if the functionalities increase faster than cost! Some steps have been already identified to be more costly steps: bonding and via filling. Indeed, throughput and material used have a direct impact on the final price. Continuous perspectives of TSV integration are progressing in order to optimise actual applications or to develop new integration. First challenging integration is the interposers with 3D interconnection allowing devices mounting on both side, like passive device integration or building of micro-cooling channels. The main interest of the 3D silicon interposer is the fact that it can connect chips at different locations and sizes, as example memory over digital IC. The usage of silicon as an interposer leads to an increase in the cost, but it will boost performances and reduce power consumption. One other advantage of the introduction of 3D interposer is the simplification of the required substrate implying a better mismatch of CTE lowering the packaging failure. In the wafer level package, TSV is now introduced to reduce the package footprint and mainly simplify the capping of device, similar to that for the MEMS. Indeed by integrating TSV, the capping must only protect the device against external environment, and not also take into account the electrical path in the bond layer degrading the hermiticity performance. To finish this paper, the sentence of Yann Guillou is the right situation: “The (3D) roadmaps need to be based on application requirements and not driven by technology ONLY. 3D Integration with TSV is not a scaling based concept Does it make sense today to think about submicron via diameter or dice thinner than 30 μm for example?” Applications need to take a risk by using 3D TSV technology!

TCAD Methodology for ESD Robustness Prediction of Smart Power ESD Devices

This paper presents a new method to predict the electrostatic-discharge (ESD) protection robustness of a device with technology-in-computer-aided-design (TCAD) simulations. Tested on different devices and two Smart Power technologies, the results are validated through electrical measurement and failure analysis. Failure current is always predicted with a good accuracy compared to technology spreading. In addition, the methodology provides a significant simulation time speedup compared to classical methods based on a temperature criterion

Packaging of Copper/Low-k IC Devices: A Novel Direct Fine Pitch Gold Wirebond Ball Interconnects Onto Copper/Low-k Terminal Pads

The trend toward finer pitch and higher performance devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. Compared to the commonly used aluminum metallization scheme on the traditional silicon dioxide and/or silicon nitride passivation, a Cu/low-k combination offers higher on-chip communication speed and a lower overall device cost. However, the process of packaging Cu/low-k devices has been proven to be difficult, relying either on additional lithography and deposition steps or on costly new process tools. Thus, this paper presents a novel methodology to bond fine pitch Au wire directly onto the Cu/low-k pad structure using the industry standard tool set. A Cu/low-k test vehicle is designed with the required slotted low-k fillings for dual damascene chemical mechanical polishing (CMP) process need. In addition, a thin organic passivation film is developed for coating the exposed Cu/low-k pad temporarily from copper oxidation and to provide a wirebondable surface to form the proper interconnects. A design of experiment is performed to optimize wirebonding parameters [power, time, and ultrasonic gauge (USG) bleed], along with key physical contributors from wafer sawing and die attaching steps that impact the interconnect shear strength and quality. In addition, electrical and optical characterization and surface failure analysis are performed to confirm the feasibility of the technology. Finally, reliability results of the pad structure design and recommendations for further process optimization are presented.

Lift-out techniques coupled with advanced TEM characterization methods for electrical failure analysis

Lift-out techniques coupled with advanced TEM characterization methods for electrical failure analysis