Efficient Gate Research Articles

STAM: A SpatioTemporal Attention Based Memory for Video Prediction

Video prediction has always been a very challenging problem in video representation learning due to the complexity in spatial structure and temporal variation. However, existing methods mainly predict videos by employing language-based memory structures from the traditional Long Short-Term Memories (LSTMs) or Gated Recurrent Units (GRUs), which may not be powerful enough to model the long-term dependencies in videos, consisting of much more complex spatiotemporal dynamics than sentences. In this paper, we propose a SpatioTemporal Attention based Memory (STAM), which can efficiently improve the long-term spatiotemporal memorizing capacity by incorporating the global spatiotemporal information in videos. In the temporal domain, the proposed STAM aims to observe temporal states from a wider temporal receptive field to capture accurate global motion information. In the spatial domain, the proposed STAM aims to jointly utilize both the high-level semantic spatial state and the low-level texture spatial states to model a more reliable global spatial representation for videos. In particular, the global spatiotemporal information is extracted with the help of an Efficient SpatioTemporal Attention Gate (ESTAG), which can adaptively apply different levels of attention scores to different spatiotemporal states according to their importance. Moreover, the proposed STAM are built with 3D convolutional layers due to their advantages in modeling spatiotemporal dynamics for videos. Experimental results show that the proposed STAM can achieve state-of-the-art performance on widely used datasets by leveraging the proposed spatiotemporal representations for videos.

Functional Analysis of Plant Monosaccharide Transporters Using a Simple Growth Complementation Assay in Yeast.

The study of genes and their products is an essential prerequisite for fundamental research. Characterization can be achieved by analyzing mutants or overexpression lines or by studying the localization and substrate specificities of the resulting proteins. However, functional analysis of specific proteins in complex eukaryotic organisms can be challenging. To overcome this, the use of heterologous systems to express genes and analyze the resulting proteins can save time and effort. Yeast is a preferred heterologous model organism: it is easy to transform, and tools for genomics, engineering, and metabolomics are already available. Here, we describe a well-established and simple method to analyze the activity of plant monosaccharide transporters in the baker's yeast, Saccharomyces cerevisiae, using a simple growth complementationassay. We used the famous hexose-transport-deficient yeast strain EBY.VW4000 to express candidate plant monosaccharide transporters and analyzed their transport activity. This assay does not require any radioactive labeling of substrates and can be easily extended for quantitative analysis using growth curves or by analyzing the transport rates of fluorescent substrates like the glucose analog 2-NBDG. Finally, to further simplify the cloning of potential candidate transporters, we provide level 0 modular cloning (MoClo) modules for efficient and simple Golden Gate cloning. This approach provides a convenient tool for the functional analysis of plant monosaccharide transporters in yeast. Key features Comprehensive, simple protocol for analysis of plant monosaccharide transporters in yeast Includes optional MoClo parts for cloning with Golden Gate method Includes protocol for the production and transformation of competent yeast cells Does not require hazardous solutions, radiolabeled substrates, or specialized equipment.

Room-Temperature Gate-Tunable Nonreciprocal Charge Transport in Lattice-Matched InSb/CdTe Heterostructures.

Symmetry manipulation can be used to effectively tailor the physical order in solid-state systems. With the breaking of both the inversion and time-reversal symmetries, nonreciprocal magneto-transport may arise in nonmagnetic systems to enrich spin-orbit effects. Here, the observation of unidirectional magnetoresistance (UMR) in lattice-matched InSb/CdTe films is investigated up to room temperature. Benefiting from the strong built-in electric field of 0.13 Vnm-1 in the heterojunction region, the resulting Rashba-type spin-orbit coupling and quantum confinement result in a distinct sinusoidal UMR signal with a nonreciprocal coefficient that is 1-2 orders of magnitude larger than most non-centrosymmetric materials at 298 K. Moreover, this heterostructure configuration enables highly efficient gate tuning of the rectification response, wherein the UMR amplitude is enhanced by 40%. The results of this study advocate the use of narrow-bandgap semiconductor-based hybrid systems with robust spin textures as suitable platforms for the pursuit of controllable chiral spin-orbit applications.

A Monolithic GaN Power IC With On-Chip Gate Driving, Level Shifting, and Temperature Sensing, Achieving Direct 48-V/1-V DC–DC Conversion

To unlock the full potential of monolithic gallium nitride (GaN) power integrated circuits, this article explores the feasibility of developing efficient and reliable on-chip gate driving and level shifting solutions, which fundamentally facilitate the on-chip implementation of GaN power circuits. As results, a self-bootstrapped hybrid (SBH) gate driving scheme and its circuitry are developed, which achieve rail-to-rail dynamic gate driving in normal operation and robust static gate driving in large transient moments. Meanwhile, an auto-lock auto-break (A2) level shifting technique is proposed to convert the gate driving control signals from low-voltage (LV) to high-voltage (HV) domains, without requiring any p-type devices. This enables the on-chip operation of high-side power switches and makes synchronous rectification possible. On-chip temperature sensing is implemented to monitor junction temperature directly at low circuit complexity and power and cost overheads, facilitating thermal protection at high power density. Furthermore, on-die dead-time control is presented to optimize zero voltage switching (ZVS) for high efficiency. All the techniques and circuits are demonstrated in a monolithic asymmetrical half-bridge (AHB) power converter on a GaN-on-SOI process. It achieves direct 48V/1V dc–dc conversion with a maximum load current of 5 A and a current density of 1.1 A/mm2. Among the existing monolithic GaN power ICs capable of on-chip synchronous rectification, it achieves the shortest rising- and falling-edge gate driving delays of 11.6 and 14.0 ns. Despite running doubled numbers of on-chip power transistors and gate drivers, it only consumes 70-mW static power.

An efficient field programmable gate arrays based real‐time implementation of smooth variable structure filter to estimate the state of charge of Li‐ion battery in electric vehicle application

The computational efficiency is a challenging task in the real-time implementation of battery State of Charge (SoC) estimation algorithms in Electric Vehicle (EV) application. This study proposes for the first time a pure hardware architecture of a Smooth Variable Structure Filter (SVSF) to estimate the SoC of a lithium-ion battery in an EV. The proposed embedded architecture is implemented on a Xilinx Zynq-7000 field programmable gate arrays board without using any soft-core, and validated with real-time tests carried out on a 20 Ah NMC battery with nominal voltage about 3.65 V. The whole embedded architecture of the SVSF needs a reduced execution time in the range of 921 ns, and it consumes only 466 mW. The average estimation errors of the SoC and battery voltage at different temperatures are kept within 4.95% and 2.35% respectively. The successful convergence of the algorithm and the accurate results obtained in different circumstances, prove the practicability and computational efficiency of the proposed hardware architecture.

Subthreshold Schottky-contacted carbon nanotube network film field-effect transistors for ultralow-power electronic applications

Ultralow-power electronics is critical to wearable, portable, and implantable applications where the systems could only have access to very limited electrical power supply or even be self-powered. Here, we report on a type of Schottky barrier (SB) contacted single-walled carbon nanotube (SWCNT) network film field-effect-transistors (FETs) that are operated in the subthreshold region to achieve ultralow-power applications. The thin high-k gate dielectric and the overlap between the gate and the source electrodes offer highly efficient gate electrostatic control over the SWCNT channel and the SB at the source contact, resulting in steep subthreshold switching characteristics with a small subthreshold swing (∼67 mV dec−1), a large current on/off ratio (∼106), and a low off-state current (∼0.5 pA). A p-channel metal-oxide-semiconductor inverter built with the subthreshold SB-SWCNT-FETs exhibits a well-defined logic functionality and small-signal amplification capability under a low supply voltage (∼0.5 V) and an ultralow power (∼0.05 pW μm−1). The low-voltage and deep subthreshold operations reported here could lay an essential foundation for high-performance and ultralow-power SWCNTs-based electronics.

Multi-Objective Gate Allocation Problem Based on Multi-Commodity Network Flow Model

Gate allocation has always been a fundamental but critical issue in the daily operation of airports, which is related to service quality and schedule efficiency. In order to obtain reasonable and efficient gate allocation results, in this paper, a multi-commodity network flow model is proposed to describe the gate allocation process in flight flow, based on which a multi-objective optimization model is constructed. It not only comprehensively considers the flight information of aircraft arrivals and departures, but also integrates the broader interests of passengers, airlines, and airports. To solve it, a linear weighting technique is applied. In addition, K-means cluster analysis is used to explore different weight combinations, and on this basis, the idle time of the gate is introduced as a performance evaluation index to guide the selection of the final weight. By analyzing the optimization results of actual operation data, the proposed model significantly balances the interests of multiple parties and the number of flights at each gate and has a relatively high gate-utilization rate. It can provide rich decision support and a reasonable allocation scheme for airport management to a certain extent.

Implementation of Quantum Algorithms via Fast Three-Rydberg-Atom CCZ Gates

Multiqubit CCZ gates form one of the building blocks of quantum algorithms and have been involved in achieving many theoretical and experimental triumphs. Designing a simple and efficient multiqubit gate for quantum algorithms is still by no means trivial as the number of qubits increases. Here, by virtue of the Rydberg blockade effect, we propose a scheme to rapidly implement a three-Rydberg-atom CCZ gate via a single Rydberg pulse, and successfully apply the gate to realize the three-qubit refined Deutsch–Jozsa algorithm and three-qubit Grover search. The logical states of the three-qubit gate are encoded to the same ground states to avoid an adverse effect of the atomic spontaneous emission. Furthermore, there is no requirement for individual addressing of atoms in our protocol.

Design and analysis of an efficient reversible hybrid new gate using silicon micro-ring resonator-based all-optical switch

Design and analysis of an efficient reversible hybrid new gate using silicon micro-ring resonator-based all-optical switch

Prolonging valley polarization lifetime through gate-controlled exciton-to-trion conversion in monolayer molybdenum ditelluride

Monolayer 2D semiconductors provide an attractive option for valleytronics due to valley-addressability. But the short valley-polarization lifetimes for excitons have hindered potential valleytronic applications. In this paper, we demonstrate a strategy for prolonging the valley-polarization lifetime by converting excitons to trions through efficient gate control and exploiting the much longer valley-polarization lifetimes for trions than for excitons. At charge neutrality, the valley lifetime of monolayer MoTe2 increases by a factor of 1000 to the order of nanoseconds from excitons to trions. The exciton-to-trion conversion changes the dominant depolarization mechanism from the fast electron-hole exchange for excitons to the slow spin-flip process for trions. Moreover, the degree of valley polarization increases to 38% for excitons and 33% for trions through electrical manipulation. Our results reveal the depolarization dynamics and the interplay of various depolarization channels for excitons and trions, providing an effective strategy for prolonging the valley polarization.

Quantum dot Cellular Automata based Fault Tolerant Fingerprint Authentication Systems using Reversible Logic Gates

The limits and difficulties looked by CMOS innovation in the nano system has prompted the exploration of other potential advancements which can work with same functionalities anyway with lower power scattering and higher speed. One such technology is Quantum dot Cellular Automata (QCA). In this paper, QCA is explored to design the authentication system. This paper first presents the basic operating principle of a Fingerprint Authentication System (FAS) followed by fault tolerance analysis of four efficient XOR gate designs in the literature. The XOR gate is then used in the proposed four fault tolerant designs of reversible FAS in QCA, which are based on different reversible gates. Based on the evaluation of different performance parameters, it is seen that the proposed FAS designs are cost efficient and achieve improvement up to 59.46% in terms of number of cells, 67.16% improvement in cell area, 67.14% improvement in total area, 66.67% improvement in latency and 90.51% improvement in terms of circuit cost from the existing design Furthermore, the energy dissipation examination of the proposed designs is also additionally introduced. Subsequently, the proposed designs can be effectively used in biometric applications demanding ultra-low power consumption, higher operating speed and minimal area utilization.

Efficient and Compact Optical NOR Gate based on Photonic Crystal Platform

Efficient and Compact Optical NOR Gate based on Photonic Crystal Platform

High-sensitive phototransistor based on vertical HfSe2/MoS2 heterostructure with broad-spectral response

Van der Waals heterostructures based on the two-dimensional (2D) semiconductor materials have attracted increasing attention due to their attractive properties. In this work, we demonstrate a high-sensitive back-gated phototransistor based on the vertical HfSe2/MoS2 heterostructure with a broad-spectral response from near-ultraviolet to near-infrared and an efficient gate tunability for photoresponse. Under bias, the phototransistor exhibits high responsivity of up to 1.42×103 A/W, and ultrahigh specific detectivity of up to 1.39×1015 cm⋅Hz1/2⋅W−1. Moreover, it can also operate under zero bias with remarkable responsivity of 10.2 A/W, relatively high specific detectivity of 1.43×1014 cm⋅Hz1/2⋅W−1, ultralow dark current of 1.22 fA, and high on/off ratio of above 105. These results should be attributed to the fact that the vertical HfSe2/MoS2 heterostructure not only improves the broadband photoresponse of the phototransistor but also greatly enhances its sensitivity. Therefore, the heterostructure provides a promising candidate for next generation high performance phototransistors.

High-fidelity three-qubit iToffoli gate for fixed-frequency superconducting qubits

The development of noisy intermediate-scale quantum (NISQ) devices has extended the scope of executable quantum circuits with high-fidelity single- and two-qubit gates. Equipping NISQ devices with three-qubit gates will enable the realization of more complex quantum algorithms and efficient quantum error correction protocols with reduced circuit depth. Several three-qubit gates have been implemented for superconducting qubits, but their use in gate synthesis has been limited due to their low fidelity. Here, using fixed-frequency superconducting qubits, we demonstrate a high-fidelity iToffoli gate based on two-qubit interactions, the so-called cross-resonance effect. As with the Toffoli gate, this three-qubit gate can be used to perform universal quantum computation. The iToffoli gate is implemented by simultaneously applying microwave pulses to a linear chain of three qubits, revealing a process fidelity as high as 98.26(2)%. Moreover, we numerically show that our gate scheme can produce additional three-qubit gates which provide more efficient gate synthesis than the Toffoli and iToffoli gates. Our work not only brings a high-fidelity iToffoli gate to current superconducting quantum processors but also opens a pathway for developing multi-qubit gates based on two-qubit interactions.

Efficient golden gate assembly of DNA constructs for single molecule force spectroscopy and imaging.

Single-molecule techniques such as optical tweezers and fluorescence imaging are powerful tools for probing the biophysics of DNA and DNA-protein interactions. The application of these methods requires efficient approaches for creating designed DNA structures with labels for binding to a surface or microscopic beads. In this paper, we develop a simple and fast technique for making a diverse range of such DNA constructs by combining PCR amplicons and synthetic oligonucleotides using golden gate assembly rules. We demonstrate high yield fabrication of torsionally-constrained duplex DNA up to 10 kbp in length and a variety of DNA hairpin structures. We also show how tethering to a cross-linked antibody substrate significantly enhances measurement lifetime under high force. This rapid and adaptable fabrication method streamlines the assembly of DNA constructs for single molecule biophysics.

Hydrogen-Terminated Diamond MOSFETs Using Ultrathin Glassy Ga2O3 Dielectric Formed by Low-Temperature Liquid Metal Printing Method

The p-type surface conductivity of hydrogen-terminated diamond (H-diamond) provides a viable approach toward diamond-based wide-bandgap metal-oxide-semiconductor field-effect transistors (MOSFETs) for high-power and high-frequency electronics. A facile, low-cost, and low-temperature method to form gate dielectrics on diamond that also preserves the integrity of hydrogen-termination is highly desirable for high-performance diamond surface electronics with process flexibility and high yield. In this work, we demonstrate a p-channel diamond MOSFET with an ultrathin glassy Ga2O3 dielectric layer derived from liquid metal. A liquid metal printing method was employed to transfer an amorphous Ga2O3 layer over the desired active p-channel region of H-diamond at low temperature, allowing the protection and preservation the hydrogen-terminated surface while also forming an efficient gate dielectric. The results of this work suggest that the liquid metal method can provide an efficient, low-cost, and high-yield pathway to form high-quality dielectrics for diamond-based transistors.

High-Performance 1-Bit Full Adder With Excellent Driving Capability for Multistage Structures

In this letter, a low-power 1-bit full-adder (FA) cell is proposed based on the transmission gate (TG) to attain a special module for generating full-swing Carry output. The cell benefits from the high driving capability for both Sum and Carry outputs when embedding in multistage structures like ripple-carry adders (RCAs), compressors, and multipliers. The proposed TG-based FA has a total die area of 60.02 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}^{2}$ </tex-math></inline-formula>, while the average power, delay, and power-delay-product (PDP) are 10.829 <inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula>, 3.1954 ns, and 34.603 fJ, respectively. The results introduce the FA cell as an efficient gate for integrated circuits (ICs).

Field Programmable Gate Array based elliptic curve Menezes‐Qu‐Vanstone key agreement protocol realization using Physical Unclonable Function and true random number generator primitives

The trust, authenticity and integrity of Internet-of-Things (IoT) systems are heavily reliant on Physical Unclonable Functions (PUFs) and True random number generators (TRNGs). The PUF and TRNG produce device intrinsic digital signatures and random binary sequences, which are used for cryptographic key generation, key agreement/exchange, device authentication, cloning prevention etc. This article reports an efficient Field Programmable Gate Array (FPGA)-based realization of elliptic curve Menezes-Qu-Vanstone (ECMQV)-authenticated key agreement protocol using PUF and TRNG with very competitive area-throughput trade-offs. The key agreement protocols, which establish a shared secret key between two IoT devices, make use of PUF and TRNG primitives for the long- and short-term secret keys generation while the elliptic curve is employed for public key generated from the corresponding secret key. The performance of the protocol is investigated on FPGAs. The authors' implementation of the ECMQV protocol takes 1.802 ms using 18852 slices on Artix-7 FPGA.

Synergistic‐engineered van der Waals photodiodes with high efficiency

AbstractVan der Waals (vdW) heterostructures based on two‐dimensional transition‐metal dichalcogenides have provided unprecedented opportunities for photovoltaic detectors owing to their strong light‐matter interaction and ultrafast interfacial charge transfer. Despite continued advancement, insufficient control of photocarrier behaviors still limits the external quantum efficiency (EQE) and operation speed of such detectors. Here, we propose a synergistic strategy of contact‐configuration design and thickness‐modulation to construct high‐performance vdW photodiodes based on the typical type II heterostructure (MoS2/WSe2). Through integrating three contact architectures into one device to exclude other factors, we solid the superiority of designed 1L‐MoS2/WSe2/graphene heterostructures incorporating efficient photocarrier collection and gate modulation. Together with leveraging the layer‐number‐dependent properties of WSe2, we observe the critical thickness of WSe2 (11 layers) for the highest EQE, which verifies the thickness‐dependent competition between photocarrier generation, dissociation, and collection. Finally, we demonstrate the synergistic‐engineered vdW heterostructure can trigger record‐high EQE (61%) and manifest ultrafast photoresponse (4.1 μs) at the atomically thin limit (8 nm). The proposed strategy enables architecture‐design and thickness‐engineering to unlock the potential to realize high‐performance optoelectronic devices.

Analysis of &lt;i&gt;InN/La&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt;&lt;/i&gt; Twosome for Double-Gate MOSFETs for Radio Frequency Applications

The channel material of a gate describes the operating condition of the MOSFET. A suitable operating condition prevails in MOSFETs if the transistors are quite enough to observe and control at the nanometer regime. An efficient gate and channel material have been proposed in this work which is based on the electrical properties they exhibit at the temperature of 300K. The doping concentration for the electrons and holes is maintained to be 1Χ1019cm-3 for the entire electronic simulator. The simulation results show that using La2O3 along with Indium Nitride (InN) material for the designing of Double-Gate (DG) MOSFETs provides better controllability over the transistor at a channel length of 50nm. This proposed DG-MOSFET is more compliant than the conventional coplanar MOSFETs based on Silicon.