Efficient Gate Research Articles

Design of an Efficient Memristor-based Dynamic Exclusive-OR gate.

In this paper, an efficient memristor-based dynamic logic design for an Exclusive-OR gate is proposed. The proposed realization reduces the number of cascaded stages and component count thereby providing an overall performance improvement. The performance of the proposed design is compared with the most recent existing design through LTspice software simulations at 32 nm technology node in terms of total power consumption, average propagation delay, and number of components used in the implementation. The outcomes depict that the proposed design consumes 57 % reduced power and provides faster operation with 5.09 % improvement in propagation delay in comparison to its existing counterpart. Further, the robustness of the proposed design is verified by performing technology and capacitance variation. The results show the impeccable performance of proposed design across different load capacitance and technology nodes.

Emulating Switching From Short-Term to Long-Term Plasticity of Bio-Synapse Using Split Gate MOSFET

For the development of brain-inspired neuromorphic hardware with high integration density and connectivity in this work, we have proposed a fully planar, CMOS compatible, and energy efficient (inference energy &#x003D; 7.4x10^-17 J) tunable-split gate synaptic transistor (T-SGST) with correlation-based plasticity. Valence band offset (VBO) in the device due to SiGe region and charge trapping&#x002F;de-trapping in the nitride layer are found to be effective for synaptic learning (short-term potentiation (STP), long-term potentiation (LTP), and long-term depression (LTD)) at low trapping&#x002F;de-trapping voltage (<inline-formula><tex-math notation="LaTeX">${V}_{G2S} = | {3.5} |V$</tex-math></inline-formula>). Furthermore, the switching from STP to LTP is governed by repeated input pulses (correlation-based plasticity) and the bias potential on gate 1 (G1). The proposed T-SGST offers a switching at the 8^th input pulse when G1 is tuned at <i>V_G</i>₁<i>_S</i> &#x003D; 0 V, whereas for <i>V_G</i>₁<i>_S</i> &#x003D; -0.2 V there is no switching. In addition, we have also reported the strong dependence of the interval time between input pulses on switching. These findings in our proposed T-SGST device make it a promising candidate for application in the neuromorphic technology.

The airport gate assignment problem: A Branch-and-Price Approach for improving utilization of jetways

With the development of the civil aviation industry, airports' parking space resources, especially those with jetways, become increasingly scarce. The airport gate assignment problem (AGAP) is a critical issue in airport operation management. When the number of flights is large, solving this situation is challenging. Therefore, designing an efficient gate assignment methodology is very important. This paper considers several significant constraints and aims to maximize the number of passengers using jetways, which is not fully considered in the existing research. A model with gate plans (possible scheme combinations) as decision variables is established, which effectively reduces the number of constraints. However, considering that the scale of this problem is still quite large, the Branch- and-Price algorithm (BAPA) is used to solve the model. The solving speed is improved by adding a heuristic search with a certain probability in each search node. The model's performance is verified by using the actual flight data of Kunming Changshui International Airport, China. The experimental results show that the method of this paper can achieve a 12.71 % increase in the optimization goal compared to the current computer-assisted manual allocation. In terms of finding the optimal and satisfactory solution, the feasibility and effectiveness of this method are verified by comparing with the commercial solver CPLEX, Tabu Search (TS) algorithm, improved Adaptive Parallel Genetic (APGA) algorithm, and Greedy algorithm (GA).

Non‐Local Electrostatic Gating Effect in Graphene Revealed by Infrared Nano‐Imaging

AbstractElectrostatic gating lies in the heart of field effect transistor (FET) devices and modern integrated circuits. To achieve efficient gate tunability, the gate electrode has to be placed very close to the conduction channel, typically a few nanometers. Remote control of a FET device through a gate electrode located far away is highly desirable, because it not only reduces the complexity of device fabrication, but also enables the design of novel devices with new functionalities. Here, a non‐local electrostatic gating effect in graphene devices using scanning near‐field optical microscopy (SNOM)—a technique that can probe local charge density in graphene—is reported. Remarkably, the charge density of the graphene region tens of micrometers away from a local gate can be efficiently tuned. The observed non‐local gating effect is initially driven by an in‐plane electric field induced by the quantum capacitance of graphene, and further largely enhanced by adsorbed polarized water molecules. This study reveals a non‐local phenomenon of Dirac electrons, provides a deep understanding of in‐plane screening from Dirac electrons, and paves the way for designing novel electronic devices with remote gate control.

An efficient field-programmable gate array-based hardware oriented block motion estimation algorithm based on diamond adaptive rood pattern search algorithm for multi-standard video codec

Motion estimation and motion compensation techniques are effectively used for removing temporal redundancy between adjacent frames during video compression, but video quality will be degraded with the traditional pixel-based matching algorithms. To overcome this issue, diamond adaptive rood pattern search algorithm-based block-matching motion estimation algorithms are proposed in this manuscript for multi-stranded codec hardware design, which provide a high compression rate with less computational complexity. In this work, a diamond adaptive rood pattern search algorithm is used, which is a combination of a diamond-search algorithm and adaptive rood pattern search. In addition, the proposed algorithm applies multiple search strategies and terminates unnecessary searching while reserving high data regularity. The proposed diamond adaptive rood pattern search algorithm-based block-matching motion estimation algorithm for multi-stranded codec hardware design provides good performance in terms of complex calculations reduction and reaches a high speed in comparison to traditional search algorithms. The proposed architecture is implemented in Xilinx ISE design 14.5 suite and the implemented results are compared to the existing motion estimation techniques on field-programmable gate array devices. Simulation results shows that the diamond adaptive rood pattern search algorithm for multi-stranded codec hardware design provides a very good improvement in terms of computations overhead reduction, with 96.4%, 97.3% latency and 98.7% throughput and achieves a high compression rate without video quality degradation.

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the Look-Up Table (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

Efficient quantum gates and algorithms in an engineered optical lattice

In this work, trapped ultracold atoms are proposed as a platform for efficient quantum gate circuits and algorithms. We also develop and evaluate quantum algorithms, including those for the Simon problem and the black-box string-finding problem. Our analytical model describes an open system with non-Hermitian Hamiltonian. It is shown that our proposed scheme offers better performance (in terms of the number of required gates and the processing time) for realizing the quantum gates and algorithms compared to previously reported approaches.

An efficient field programmable gate array based hardware architecture for efficient motion estimation with parallel implemented genetic algorithm

SummaryThe main idea of this article is to propose a hardware design of block matching (BM) algorithm for an efficient motion estimation (ME) strategy in a field programmable gate array platform based on a parallel implemented genetic algorithm (GA). Easiness and the effectiveness of the BM algorithm while implementing have a major drawback of low quality and computationally cost expensive during the process of ME. Therefore, here in this article, we suggest GA based BM for a quick and cost‐effective computation of motion vectors, without negotiating the quality factor. The ME carried out for various video sequences is implemented by using Xilinx ISE Design Suite 14.1. Delay, time, area, power, PSNR, MSE, SNR, SSIM, and NRMSE are the metrics used for analyzing the performance, and the simulation outcome shows that this parallel implemented BM architecture design shows an exotic improvement in time, quality and in utilization of power on estimating the motion than that of the conventional designs.

Efficient FPGA Implementation of a Dual-Frequency GNSS Receiver with Robust Inter-Frequency Aiding.

Multiple frequency global navigation satellite system (GNSS) has become more complex due to the existence of extra channels. Typically, auxiliary methods are used to synchronize the second signals at other bands by aiding the acquired channel parameters. However, there are critical limitations because the reception of GNSS signals is subject to uncertainties due to noise carrier injection or circuit interference. The relationship between the two Doppler frequencies can be affected by uncertainties. Therefore, we aimed to implement an efficient dual-frequency field-programmable gate array (FPGA), performing a direct aid tracking method for the secondary channel to achieve resource efficiency and inner aid robustness. A robust estimator that directly links two loops in the two bands is proposed. In this scheme, (1) a robust estimator able to cope with uncertainty; (2) a primary tracking scheme to obtain the error boundary, and (3) a tracked bit-boundary for the initial code phase of the second channel are used. Based on experiments on the FPGA, the robust channel link can achieve direct aid tracking, and 31.02% of the original hardware resources from the aided acquisition module were released satisfactorily.

Efficient quantum gate teleportation in higher dimensions

The Clifford hierarchy is a nested sequence of sets of quantum gates critical to achieving fault-tolerant quantum computation. Diagonal gates of the Clifford hierarchy and ‘nearly diagonal’ semi-Clifford gates are particularly important: they admit efficient gate teleportation protocols that implement these gates with fewer ancillary quantum resources such as magic states. Despite the practical importance of these sets of gates, many questions about their structure remain open; this is especially true in the higher-dimensional qudit setting. Our contribution is to leverage the discrete Stone–von Neumann theorem and the symplectic formalism of qudit stabilizer theory towards extending the results of Zeng et al . (2008) and Beigi &amp; Shor (2010) to higher dimensions in a uniform manner. We further give a simple algorithm for recursively enumerating all gates of the Clifford hierarchy, a simple algorithm for recognizing and diagonalizing semi-Clifford gates, and a concise proof of the classification of the diagonal Clifford hierarchy gates due to Cui et al . (2016) for the single-qudit case. We generalize the efficient gate teleportation protocols of semi-Clifford gates to the qudit setting and prove that every third-level gate of one qudit (of any prime dimension) and of two qutrits can be implemented efficiently. Numerical evidence gathered via the aforementioned algorithms supports the conjecture that higher-level gates can be implemented efficiently.

Photonic Curing of Solution-Processed Oxide Semiconductors with Efficient Gate Absorbers and Minimal Substrate Heating for High-Performance Thin-Film Transistors.

In this study, photonic curing is used to rapidly and effectively convert metal-oxide sol–gels to realize high-quality thin-film transistors (TFTs). Photonic curing offers advantages over conventional thermal processing methods such as ultrashort processing time and compatibility with low-temperature substrates. However, previous work on photonically cured TFTs often results in significant heating of the entire substrate rather than just the thin film at the surface. Here, sol–gel indium zinc oxide (IZO)-based TFTs are photonically cured with efficient gate absorbers requiring as few as five pulses using intense white light delivering radiant energy up to 6 J cm–2. Simulations indicate that the IZO film reaches a peak temperature of ∼590 °C while the back of the substrate stays below 30 °C. The requirements and design guidelines for photonic curing metal-oxide semiconductors for high-performance TFT applications are discussed, focusing on the importance of effective gate absorbers and optimized pulse designs to efficiently and effectively cure sol–gel films. This process yields TFTs with a field-effect mobility of 21.8 cm2 V–1 s–1 and an Ion/Ioff ratio approaching 108, which exceeds the performance of samples annealed at 500 °C for 1 h. This is the best performance and highest metal-oxide conversion for photonically cured oxide TFTs achieved to date that does not significantly heat the entire thickness of the substrate. Importantly, the conversion from sol–gel precursors to the semiconducting metal-oxide phase during photonic curing is on par with thermal annealing, which is a significant improvement over previous pulsed-light processing work. The use of efficient gate absorbers also allows for the reduction in the number of pulses and efficient sol–gel conversion.

An Efficient FPGA-Based Hardware Accelerator for Convex Optimization-Based SVM Classifier for Machine Learning on Embedded Platforms

Machine learning is becoming the cornerstones of smart and autonomous systems. Machine learning algorithms can be categorized into supervised learning (classification) and unsupervised learning (clustering). Among many classification algorithms, the Support Vector Machine (SVM) classifier is one of the most commonly used machine learning algorithms. By incorporating convex optimization techniques into the SVM classifier, we can further enhance the accuracy and classification process of the SVM by finding the optimal solution. Many machine learning algorithms, including SVM classification, are compute-intensive and data-intensive, requiring significant processing power. Furthermore, many machine learning algorithms have found their way into portable and embedded devices, which have stringent requirements. In this research work, we introduce a novel, unique, and efficient Field Programmable Gate Array (FPGA)-based hardware accelerator for a convex optimization-based SVM classifier for embedded platforms, considering the constraints associated with these platforms and the requirements of the applications running on these devices. We incorporate suitable mathematical kernels and decomposition methods to systematically solve the convex optimization for machine learning applications with a large volume of data. Our proposed architectures are generic, parameterized, and scalable; hence, without changing internal architectures, our designs can be used to process different datasets with varying sizes, can be executed on different platforms, and can be utilized for various machine learning applications. We also introduce system-level architectures and techniques to facilitate real-time processing. Experiments are performed using two different benchmark datasets to evaluate the feasibility and efficiency of our hardware architecture, in terms of timing, speedup, area, and accuracy. Our embedded hardware design achieves up to 79 times speedup compared to its embedded software counterpart, and can also achieve up to 100% classification accuracy.

Ferroelectric α‐In2Se3 Wrapped‐Gate β‐Ga2O3 Field‐Effect Transistors for Dynamic Threshold Voltage Control

AbstractIndium selenide (α‐In2Se3), which is a recently emerging ferroelectric semiconductor, can solve a major hindrance to applications of an ultra‐wide bandgap beta‐gallium oxide (β‐Ga2O3) semiconductor. Here, ferroelectric α‐In2Se3 wrapped‐gate β‐Ga2O3 field‐effect transistors (FETs) for dynamic threshold voltage (VTH) control is demonstrated. The dry‐transferred α‐In2Se3 layer is wrapped around β‐Ga2O3 channel, which allows efficient electrostatic gate modulation. Thus, the ferroelectricity of α‐In2Se3 and a thin native oxide interlayer formed at the interface between β‐Ga2O3 and α‐In2Se3 can provide effective VTH control. Applying a positive voltage pulse to the gate electrode induces positive VTH shift; hence, the device can be even changed from depletion to enhancement (E‐) mode. The E‐mode β‐Ga2O3 FET exhibits steep‐subthreshold slope with a negligible hysteresis. The VTH of E‐mode can be further modulated by applying back‐gate bias, and electrical performance can be enhanced via dual‐gate operation. The approach demonstrates an energy efficient β‐Ga2O3‐based switching device architecture integrated with ferroelectric van der Waals 2D materials.

Multiple Magnetic Phases in Van Der Waals Mn‐Doped SnS2 Semiconductor

Abstract2D van der Waals magnetic semiconductors have emerged along with the possibilities of achieving an efficient gate tunability and a proximity effect with a high magnetic anisotropy compared with 3D counterparts. Little explored are multiple magnetic phases with a single crystallographic phase. Herein, the multiple magnetic phases in a Mn‐doped SnS2 single crystal with different doping concentrations using a one‐step self‐flux method are reported. Two ferromagnetic phases with a canted spin direction exist regardless of the Mn‐doping concentration at up to 5 at%. Antiferromagnetism coexists with the ferromagnetic order and strengthens at high Mn‐doping concentrations. A magnetoresistance measurement conducted on a 2 at% Mn‐SnS2 flake exhibits a positive‐to‐negative crossover with a value of as high as 50% and clear anisotropy, confirming the presence of ferromagnetic order in the material. By revealing multiple magnetic phases in Mn‐doped SnS2, the study broadens the scope of state‐of‐the‐art research on layered magnetic semiconductors.

Efficient FPGA-Based Real-Time Implementation of Model Predictive Control for Single-Phase Direct Matrix Converter

Finite control set model predictive control (FCS-MPC) is an optimal control strategy that solves user-defined objective functions to determine the best control action for the next time interval. Real-time implementations of model predictive control techniques are quite challenging for certain topologies due to computation complexities. In this paper, key aspects of achieving robust, reliable, and efficient field programmable gate arrays (FPGAs) based model predictive control are presented for single-phase direct matrix topology. The effectiveness of FPGA-based model predictive control is validated experimentally using an ALTERA Cyclone IV FPGA. Experimental results show that an effective load current control performance is obtained by taking advantage of pipelining capability of the FPGA device. The tradeoff between control bandwidth, FPGA resources, and hardware utilization is discussed.

Automatic offloading method of loop statements of software to FPGA

With Moore's law coming to an end, using hardware other than central processing units (CPUs), such as more energy efficient field-programmable gate arrays (FPGAs), has recently been increasing. However, when using heterogeneous hardware other than CPUs, barriers of technical skills, such as in using Open Computing Language (OpenCL), are high. Therefore, I previously proposed environment-adaptive software that enables automatic conversion, configuration, and high-performance operation of once-written code according to the hardware to be placed. Offloading of some applications to graphics processing units (GPUs) was automated previously. In this paper, I proposed an automatic offloading method of appropriate target loop statements of applications as the first step in offloading to FPGAs. I evaluated the effectiveness of the proposed method by applied it to multiple applications.

An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation

Cryptography systems have become inseparable parts of almost every communication device. Among cryptography algorithms, public-key cryptography, and in particular elliptic curve cryptography (ECC), has become the most dominant protocol at this time. In ECC systems, polynomial multiplication is considered to be the most slow and area consuming operation. This article proposes a novel hardware architecture for efficient field-programmable gate array (FPGA) implementation of Finite-field multipliers for ECC. Proposed hardware was implemented on different FPGA devices for various operand sizes, and performance parameters were determined. Comparing to state-of-the-art works, the proposed method resulted in a lower combinational delay and area-delay product indicating the efficiency of design.

Ultrafast and Energy-Efficient Ferrimagnetic XNOR Logic Gates for Binary Neural Networks

Ultrafast current-driven domain wall (DW) motions have been realized in ferrimagnetic (FiM) nanowires. However, the FiM dynamics can be significantly affected by the Joule-heating. In this work, we propose a highly efficient XNOR logic gate by properly leveraging the thermal effect on the FiM DW motions. Its functionality and advantageous performance have been confirmed by the micromagnetic simulations. Moreover, majority logic and full adder functions can also be reconfigured based on the proposed scheme. Lastly, a fully FiM DW based binary neural network (BNN) is built, which provides low energy consumption, short delay and excellent accuracy.

Exponential speedup in measuring out-of-time-ordered correlators and gate fidelity with a single bit of quantum information

Out-of-time-ordered correlators (OTOC) are a quantifier of quantum information scrambling and are useful in characterizing quantum chaos. We propose an efficient quantum algorithm to measure OTOCs that provides an exponential speed-up over the best known classical algorithm provided the OTOC operator to be estimated admits an efficient gate decomposition. We also discuss a scheme to obtain information about the eigenvalue spectrum and the spectral density of OTOCs as well as an efficient algorithm to estimate gate fidelities.

Options for increasing Boro rice production in the saline coastal zone of Bangladesh

Abstract Increasing Boro (irrigated dry season) rice production in the saline coastal zone (CZ) is part of the Bangladesh Government strategy for meeting its Sustainable Development Goals (SDG’s). However salinity and fresh water shortages during the Rabi (dry) season result in large areas of land remaining uncropped and under-utilised in the CZ, with crop yields below potential. We evaluated a range of options for increasing Boro rice production and farmer profit in this region. These included changes to sowing dates in combination with different polder sluice-gate management strategies aimed at increasing irrigation water supply and cropping area. We employed a case-study approach, using a combination of field experimentation, APSIM cropping systems modelling, and economic analysis, focussing on Satkhira District, Khulna Division. We found the most profitable strategies were to establish Boro rice crops in mid-November, around a month earlier than current farmer practice, on larger portions of land irrigated using river water supplied via the polder canal network. This offers significant increases in both farmer profit and regional production (up to 4x). The reasons for the gains are dual – (1) potential rice yields are higher; and (2) early sowing unleashes the potential of extensive fresh-water availability to greatly increase cropping area, because at that time river salinity levels are low and unlimited amounts of suitable irrigation water are available. Under current practices with later sowing dates (around mid-December), these early-season water resources are hardly used. To achieve the advantages of early-sowing, certain system changes are necessary. Firstly, farmers must adopt early-maturing transplanted Aman (T. Aman) rice cultivars in the monsoon season. Secondly, they must synchronise agronomic timings with fellow farmers in polder sluice-gate management zones to allow efficient gate operation and timely drainage of stagnant monsoon waters from fields in October, followed by early-season establishment of Boro rice crops. The applicability of our findings will vary geographically in the CZ, as a function of prevailing dynamics of river salinity, water tables, soils and climate. To understand the economics at a national scale, our analysis should be extended on a regional basis to estimate regional production gains possible, as well as to assess environmental health risks – particularly related to increased salinization of polder soils. Our analysis suggests that substantial investment in further research and achieving the required social and agronomic changes may be warranted.