Effective Threshold Voltage Research Articles

Influence of the Contact Thickness on Electrical Performance of Staggered and Planer <i>p</i>-Channel Organic Field Effect Transistors

The influence of contact thickness on electrical performance of bottom gate Organic Field Effect Transistor (BG-OFET) with staggered and planer structures is studied in this paper. Two dimensional device simulation is performed with identical dimensions for both devices which show a good agreement between simulated and measured results. Contact thickness is varied from 0nm to 20nm for planer and staggered structures. The electrical characteristics are strongly affected by the contact thickness variation. With increasing contact thickness, the threshold voltage shifts from negative to positive. The simulation results indicate that saturation current value of staggered structure is higher than that of planer. Although the current does not increase in staggered structure due to its increasing contact thickness, while the current in planer structure increases up to three times. However, current in planer is still below the current in staggered structure. The extracted field effect mobility and current on-off ratio at 20nm electrode thickness for staggered structure is 0.67 cm2/V.s and 108, respectively. It has been observed that the field effect mobility, threshold voltage, sub-threshold slope, transconductance and current on-off ratio can be modified by varying contact thickness. Analysis of the results clearly demonstrates the significance of controlling the contact thickness in planer and staggered OFETs. It even offers a way to control OFETs parameters.

A simple compact model for long-channel junctionless Double Gate MOSFETs

This paper presents a simple explicit compact model for the drain current of long channel symmetrical junctionless Double Gate MOSFETs. Our approach leads to very simple equations compared to other models, while retaining high accuracy and physical consistency. Explicit and analytical solutions are also given. Compared to TCAD simulations, the model gives excellent results in accumulation regime. Although the accuracy decreases in depletion regime for very high doping and semiconductor thicknesses, it still remains very good and it is shown that this issue can be neglected because it can only be seen on devices with both high doping and semiconductor thicknesses, that are unlikely to be used as a real device, because of their negative threshold voltage. Finally, it is shown that the model reproduces the two observed different conduction modes, related to accumulation and depletion regimes and that the effective gate capacitance and threshold voltage are different in those regimes, which explains the change of slope observed in the Id(Vg) characteristics.

Effective threshold voltage control in GaN nanowire field-effect transistors with a dual-gate structure

To control the gate threshold voltages of nano-devices, we fabricated a GaN nanowire field-effect transistor with a sandwich-type dual-gate structure in which the top- and the bottom-gate electrodes could independently apply a gate voltage bias to the nanowire conducting channel. The fabricated device showed a clear n-type gate response. The gate threshold voltage of the nanowire field-effect transistor could be effectively tuned over a wide range, from −13 V to +1 V, by scanning the topor the bottom-gate voltages between −10 and +10 V, respectively. As the top-gate voltage was varied from −10 V to +10 V, the carrier mobility increased from 16 to 56 cm2/Vs, and the channel conductance increased. The turn-on position of the channel conductance could be tuned precisely by varying the voltage at one of the gates.

A High-Efficiency Low-Voltage CMOS Rectifier for Harvesting Energy in Implantable Devices

We present, in this paper, a new full-wave CMOS rectifier dedicated for wirelessly-powered low-voltage biomedical implants. It uses bootstrapped capacitors to reduce the effective threshold voltage of selected MOS switches. It achieves a significant increase in its overall power efficiency and low voltage-drop. Therefore, the rectifier is good for applications with low-voltage power supplies and large load current. The rectifier topology does not require complex circuit design. The highest voltages available in the circuit are used to drive the gates of selected transistors in order to reduce leakage current and to lower their channel on-resistance, while having high transconductance. The proposed rectifier was fabricated using the standard TSMC 0.18 μm CMOS process. When connected to a sinusoidal source of 3.3 V peak amplitude, it allows improving the overall power efficiency by 11% compared to the best recently published results given by a gate cross-coupled-based structure.

Gate Insulator Effects on the Electrical Performance of ZnO Thin Film Transistor on a Polyethersulphone Substrate

Low temperature processing for fabrication of transistor backplane is a cost effective solution while fabrication on a flexible substrate offers a new opportunity in display business. Combination of both merits is evaluated in this investigation. In this study, the ZnO thin film transistor on a flexible Polyethersulphone (PES) substrate is fabricated using RF magnetron sputtering. Since the selection and design of compatible gate insulator is another important issue to improve the electrical properties of ZnO TFT, we have evaluated three gate insulator candidates; SiO2, SiNx and SiO2/SiNx. The SiO2 passivation on both sides of PES substrate prior to the deposition of ZnO layer was effective to enhance the mechanical and thermal stability. Among the fabricated devices, ZnO TFT employing SiNx/SiO2 stacked gate exhibited the best performance. The device parameters of interest are extracted and the on/off current ratio, field effect mobility, threshold voltage and subthreshold swing are 10(7), 22 cm2/Vs, 1.7 V and 0.4 V/decade, respectively.

Statistical Timing and Power Optimization of Architecture and Device for FPGAs

Process variation in nanometer technology is becoming an important issue for cutting-edge FPGAs with a multimillion gate capacity. Considering both die-to-die and within-die variations in effective channel length, threshold voltage, and gate oxide thickness, we first develop closed-form models of chip-level FPGA leakage and timing variations. Experiments show that the mean and standard deviation computed by our models are within 3% from those computed by Monte Carlo simulation. We also observe that the leakage and timing variations can be up to 3X and 1.9X, respectively. We then derive analytical yield models considering both leakage and timing variations, and use such models to evaluate the performance of FPGA device and architecture considering process variations. Compared to the baseline, which uses the VPR architecture and device setup based on the ITRS roadmap, device and architecture tuning improves leakage yield by 10.4%, timing yield by 5.7%, and leakage and timing combined yield by 9.4%. We also observe that LUT size of 4 gives the highest leakage yield, LUT size of 7 gives the highest timing yield, but LUT size of 5 achieves the maximum leakage and timing combined yield. To the best of our knowledge, this is the first in-depth study on FPGA architecture and device coevaluation considering process variation.

Modified Polyvinyl Alcohol Layer with Hydrophobic Surface for the Passivation of Pentacene Thin-Film Transistor

We modified the surface of a polyvinyl alcohol (PVA) layer by self assembly monolayer technique using a fluorine substituted silane compound (1H,1H,2H,2H-perfluorooctyl-trichlorosilane: FTS) to protect a pentacene thin-film transistor (TFT) from O2 and H2O. Surface modified PVA showed very low surface energy with water contact angle of 106.2 degrees. Surface treatment of PVA layer on pentacene TFT device was done in toluene solvent and we did not observe any damage to the PVA layer or pentacene TFT devices during surface modification process. Pentacene TFT with surface modified PVA passivation layer exhibited very stable TFT operation with almost no field effect mobility drop or threshold voltage shift up to 400 hrs. The performance of unpassivated OTFTs exponentially degraded and almost failed in 290 hrs. We propose that modified PVA layer can be used as a good passivation layer for oxygen and water in OTFT.

An electromagnetic energy harvesting system for low frequency applications with a passive interface ASIC in standard CMOS

This paper presents a compact energy harvesting system, which consists of an electromagnetic (EM) generator converting ambient low frequency vibrations to DC voltage by using a highly efficient full-wave rectifier in a System-on-Package (SoP). Frequency Up-Conversion technique has been utilized by the in-house EM transducer to harvest energy from very low frequency vibrations (<5Hz). The interface ASIC is a passive rectifier based on the boot-strap rectification (BSR) technique to decrease the effective threshold voltage of the utilized diodes, attaining a high AC/DC conversion efficiency in a standard 0.35μm CMOS process. The energy harvesting system has been tested within a frequency range of 2–10Hz. The autonomous system with a volume of 21cm3, delivers 128μW DC power to an 80μA load at an external vibration frequency of 2Hz and 72mg peak acceleration while a 1.6V DC voltage is generated. The maximum overall power density is measured as 6.1μW/cm3. Furthermore, the reliable operation of a commercially available temperature sensor, as a realistic load, has also been demonstrated by using the energy harvester as a DC supply.

Infrared semiconductor laser irradiation used for crystallization of silicon thin films

We report the rapid thermal crystallization of silicon films using infrared semiconductor laser. Carbon films were used on silicon films to absorb the laser light. Uniform crystalline regions were achieved by a line shape laser beam with a length of 20μm. Polycrystalline silicon thin film transistors were fabricated in crystallized regions. The effective electron carrier mobility and threshold voltage were achieved to be 130cm2/Vs and 0.4V, respectively, when the crystalline volume ratio of the silicon films was 0.95.

Improved Performance of Pentacene Organic Field-Effect Transistors by Inserting a V2O5 Metal Oxide Layer

We fabricate pentacene-based organic field effect transistors (OFETs), inserting a transition metal oxide (V2O5) layer between the pentacene and Al source-drain (S/D) electrodes. The performance of the devices with V2O5/Al S/D electrodes is considerably improved compared to the pentacene-based OFET with only Al S/D electrodes. After the 10-nm V2O5 layer modification, the effective field-effect mobility of the devices increases from 2.7 × 10−3 cm2 /V·s to 8.93× 10−1 cm2/V·s. Owing to the change of the injection property, the effective threshold voltage (Vth) is changed from −7.5 V to −5 V and the on/off ratio shifts from 102 to 104. Moreover, the dispersion of sub-threshold current in the devices disappears. These performance improvements are ascribed to the low carrier injection barrier and the reduction of contact resistance. It is indicated that V2O5 layer modification is an effective approach to improve pentacene-based OFET performance.

Room temperature fabricated transparent amorphous indium zinc oxide based thin film transistor using high-κ HfO2 as gate insulator

We report here the performance of amorphous oxide transparent thin film transistors (TFTs) fabricated using DC magnetron sputter techniques at room temperature. Amorphous indium zinc oxide (a-IZO, In2O3:ZnO, 90:10wt.%) and high dielectric constant hafnium oxide (HfO2) films were deposited for the semiconducting channel and gate insulator under a mixture of ambient argon and oxygen gas, respectively. The reported transparent TFT structure was a bottom-gate type, consisting of indium-tin-oxide and aluminium as gate electrode and source/drain electrodes, respectively. The optical transmittance of a-IZO films in the visible region was greater than 84%. The a-IZO TFTs showed that the field effect saturation mobility, Ion/Ioff ratio, sub-threshold swing, and threshold voltage were extracted to give 13.09cm2/V-s, 4×105, 0.42V/decade, and 3.54V, respectively. The reported a-IZO TFT with high dielectric constant HfO2 gate dielectric sputtered at room temperature presents high quality characteristics, which can be used as good candidate for the application of low-temperature fabricated optoelectronic devices on organic flexible substrates.

Electrically-driven metal-insulator transition with tunable threshold voltage in a VO2-SmNiO3 heterostructure on silicon

We fabricate a heterostructure of SmNiO3 and VO2 on silicon wherein both correlated oxides undergo a metal-insulator transition at different threshold temperatures. It is demonstrated that the threshold voltage for electrically switching the VO2 from insulating to metallic can be tuned depending on the conducting state of the SmNiO3 layer. An electrically triggered SmNiO3 phase transition induces a resistance modification in the layer, which alters the field distribution and shifts the effective threshold voltage for VO2 switching in a non-volatile manner. The ability to tune the switching characteristics in such heterostructures could be relevant for emerging correlated oxide adaptive electron devices.

Comprehensive Study on the Total Dose Effects in a 180-nm CMOS Technology

The effects of total ionizing on a 180-nm CMOS technology are comprehensively studied. Firstly, we show new results on the hump effect which has strong relationship to the STI corner oxide thickness. Secondly, the leakage current degradation in various devices after radiation is investigated. For the intra-device leakage, both body doping concentration and STI corner thickness play very important roles. For the inter-device leakage, due to the low electric field at the STI bottom, it is found to be insensitive to ionizing radiation. Thirdly, a method for extracting the effective threshold voltage of the sidewall parasitic transistor is proposed by studying the leakage output characteristics. Finally, we find that the drain saturation current increases in NMOS transistors after radiation, especially in the narrow-channel ones.

Temperature dependence of the resistance switching effect studied on the metal/YBa2Cu3O6+x planar junctions

The resistive switching (RS) effect observed in capacitorlike metal/insulator/metal junctions belongs to the most promising candidates for next generation of memory cell technology. It is based on a sudden change of the junction resistance caused by an electric field applied to the metal electrodes. The aim of this work was to study this effect on the structure metal/YBCO6/YBCO7, where YBCO7 is a metallic phase and YBCO6 is an insulator phase that arises spontaneously by outdiffusion of oxygen from a few nanometers wide YBCO surface layer. Oriented YBa2Cu3O7 thin films were prepared by the method of magnetron sputtering and consequently planar structures with metal-YBCO junction were made by the means of the optical lithography, ion etching, and vacuum evaporation. On these junctions, the authors have studied the temperature dependence of the RS effect with I-V and dI/dV-V transport measurements down to liquid He temperature. They have determined the temperature dependence of the RS effect threshold voltage in the temperature range 100–300 K and showed that this dependency is compatible with common idea of oxygen ion migration under electric field within the YBCO surface layer.

A Compact Electromagnetic Vibration Harvesting System with High Performance Interface Electronics

A compact vibration-based electromagnetic (EM) energy harvesting system utilizing high performance interface electronics, has been presented. The energy harvester module consists of an AA-battery sized cylinder tube with an external coil winding, a fixed magnet at the bottom of the tube, and a free magnet inside. The transducer is able to operate at low external vibration frequencies between 9.5 and 12Hz. The generated AC voltage is converted to DC using a custom rectifier circuit that utilizes a gate cross coupled (GCC) input stage. This decreases the effective threshold voltage of the utilized diodes, while increasing the DC output power delivered to the load. The autonomous system, composed of an EM energy harvester module and a 0.35μm CMOS IC, delivers 11.6μW power to a 41μA load at an external vibration frequency of 12Hz. The volume of the total system is 4.5cm3, and the overall system power density is 2.6μW/cm3.

Ammonia-free chemically deposited CdS films as active layers in thin film transistors

In this work we have grown CdS thin films using an ammonia-free chemical bath deposition process for the active layer in thin film transistors. The CdS films were deposited substituting sodium citrate for ammonia as the complexing agent. The electrical characterization of the as-deposited CdS-based thin film transistors shows that the field effect mobility and threshold voltage were in the range of 0.12–0.16 cm 2V −1 s −1 and 8.8–25 V, respectively, depending on the channel length. The device performance was improved considerably after thermal annealing in forming gas at 250 °C for 1 h. The mobility of the annealed devices increased to 4.8–8.8 cm 2V −1 s −1 and the threshold voltage decreased to 8.4–12 V. I on / I off for the annealed devices was approximately 10 5–10 6.

Fabrication and characterization of ink jet processed organic thin film transistors with poly-4-vinylphenol gate dielectric

Organic thin film transistors (OTFTs) were fabricated on polyethersulphone substrate using 6,13-bis(triisopropylsilylethynyl) (TIPS) pentacene as an active layer and cross-linked poly-4-vinylphenol (PVP) as a gate dielectric. Prior to adoption of PVP as a gate dielectric, the PVP print condition was optimized using a metal-insulator-metal structure and making a comparison with spin coated devices in terms of the leakage current, breakdown voltage, and dielectric constant. Then, OTFTs were fabricated with an optimized PVP gate dielectric and a TIPS pentacene active layer using an ink jet printer. The electrical properties such as the field effect mobility, Ion/Ioff ratio, and threshold voltage had values of 0.055 cm2/V s, 103, and −2.6 V, respectively. The smaller Ion/Ioff ratio can be attributed to the smaller coverage of the TIPS pentacene layer due to the plateletlike crystalline structures.

Organic transistor model with nonlinear injection: Effects of uneven source contact on apparent mobility and threshold voltage

This work addresses nonlinear characteristics observed in organic field effect transistors due to uneven injection at the source contact. A self-consistent OFET model has been developed for bottom-contact organic transistor, and is described in detail. Most relevant contact parasitics are taken into account, such as source and drain series resistances, leakage source/drain resistance, and of course nonlinear charge injection at the source contact, being the focus of this work. The drain current calculation is fully self-consistent and implemented in an original manner. First, results are compared with literature and internal data on poly(3-hexylthiophene) bottom contact transistors presenting nonlinear behavior. In both cases, a single constant parameter set is used to fit all the transistor characteristic with good agreement. All extracted parameters, such as mobility or internal source contact voltage drop, are coherent with the device physics, showing the model capability to be used as a characterization tool. Following, it is shown that, in presence of series resistances and nonlinear injection, the usual mobility extraction procedure may become highly unreliable, showing a pronounced apparent mobility dependence with gate bias. Also the effective threshold voltage is shown to shift towards higher values due to the potential drop at the source contact. This is quantitatively described. Finally, the link between nonlinear injection and instabilities and breakdown conditions is established. It is shown that for a source/channel barrier height greater than 0.5–0.6 eV, the 5–6 MV cm −1 breakdown limit is reached even at very low drain bias.

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70°C) on either 100 nm HfO 2 or SiO 2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS-based thin film transistors shows a field effect mobility and threshold voltage of 25 cm 2 V -1 s -1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO 2 .

Energy–Performance Tunable Logic

We propose a new logic family that enables the user to tune the transistor's effective threshold voltage after fabrication for higher speed or lower power. This technique along with dynamic voltage scaling allows simultaneous optimization of static and dynamic power based on the application/workload requirements. Programmable interconnect from an FPGA was implemented using this logic family on a 90 nm CMOS test chip. Measurements show that this topology provides twice the tuning range in the energy-performance space compared to a conventional interconnect utilizing only supply voltage scaling. For most of the performance range, this circuit consumes 35% less energy compared to a state-of-the-art design. The circuit is an externally static, internally pulse-mode topology which can replace static circuits without requiring significant changes to the system.