Effective Electron Mobility Research Articles

Carrier transport and its variation of laser-lateral-crystallised poly-Si TFTs

Carrier transport in continuous-wave laser lateral-crystallised (CLC) poly-Si thin film transistors (TFTs) has been investigated. Large Si grains formed by the laser crystallisation, enhanced electron mobility of the CLC poly-Si TFT. It was found that the effective electron mobility was free from grain boundary scattering and was mainly governed by phonon scattering; its variation, however, was governed by the number of grains in the channel region.

Phosphorous passivation of the SiO 2/4H–SiC interface

We describe experimental and theoretical studies to determine the effects of phosphorous as a passivating agent for the SiO 2/4H–SiC interface. Annealing in a P 2O 5 ambient converts the SiO 2 layer to PSG (phosphosilicate glass) which is known to be a polar material. Higher mobility (approximately twice the value of 30–40 cm 2/V s obtained using nitrogen introduced with an anneal in nitric oxide) and lower threshold voltage are compatible with a lower interface defect density. Trap density, current–voltage and bias-temperature stress (BTS) measurements for MOS capacitors are also discussed. The BTS measurements point to the possibility of an unstable MOSFET threshold voltage caused by PSG polarization charge at the O–S interface. Theoretical considerations suggest that threefold carbon atoms at the interface can be passivated by phosphorous which leads to a lower interface trap density and a higher effective mobility for electrons in the channel. The roles of phosphorous in the passivation of correlated carbon dangling bonds, for SiC counter-doping, for interface band-tail state suppression, for Na-like impurity band formation and for substrate trap passivation are also discussed briefly.

Influence of source and drain contacts on the properties of the indium-zinc oxide thin-film transistors based on anodic aluminum oxide gate dielectrics

Thin-film transistors (TFTs) based on indium-zinc oxide (IZO) active layer and anodic aluminum oxide (Al2O3) gate dielectric layer were fabricated. The influence of source and drain (S/D) contacts on TFT performance was investigated by comparing IZO–TFTs with different S/D electrodes. The TFT with Mo S/D electrodes had higher output current and lower threshold voltage, but had poorer subthreshold swing and lower effective electron mobility compared to that with ITO S/D electrodes. By using x-ray photoelectron spectroscopy (XPS) depth profile analyzing method, it was observed that Mo was diffusing seriously into IZO, resulting in the variation of the effective channel length, thereby causing serious short-channel effect, poor subshreshold swing, and bad uniformity of the TFTs with Mo S/D electrodes.

Quantum Confinement Effects in Nanoscale-Thickness InAs Membranes

Nanoscale size effects drastically alter the fundamental properties of semiconductors. Here, we investigate the dominant role of quantum confinement in the field-effect device properties of free-standing InAs nanomembranes with varied thicknesses of 5-50 nm. First, optical absorption studies are performed by transferring InAs "quantum membranes" (QMs) onto transparent substrates, from which the quantized sub-bands are directly visualized. These sub-bands determine the contact resistance of the system with the experimental values consistent with the expected number of quantum transport modes available for a given thickness. Finally, the effective electron mobility of InAs QMs is shown to exhibit anomalous field and thickness dependences that are in distinct contrast to the conventional MOSFET models, arising from the strong quantum confinement of carriers. The results provide an important advance toward establishing the fundamental device physics of two-dimensional semiconductors.

Comparative study of CNT, silicon nanowire and fullerene embedded multilayer high-k gate dielectric MOS memory devices

Here, we present a comparative theoretical study on stacked (multilayer) gate dielectric MOS memory devices, having a metallic/semiconducting carbon nanotube (CNT), silicon nanowire (Si NW) and fullerene (C60) embedded nitride layer acting as a floating gate. Two types of devices, one with HfO2–SiO2 stack (stack-1) and the other with La2O3–SiO2 stack (stack-2) as the tunnel oxide were compared. We evaluated the effective barrier height, the dielectric constant and the effective electron mobility in the composite gate dielectric with the Maxwell–Garnett effective medium theory. Thereafter applying the WKB approximation, we simulated the Fowler–Nordheim (F–N) tunnelling/writing current and the direct tunnelling/leakage current in these devices. We evaluated the I–V characteristics, the charge decay and also the impact of CNT/Si NW aspect ratio and the volume fraction on the effective barrier height and the write voltage, respectively. We also simulated the write time, retention time and the erase time of these MOS devices. Based on the simulation results, it was concluded that the metallic CNT embedded stack-1 device offered the best performance in terms of higher F–N tunnelling current, lower direct tunnelling current and lesser write voltage and write time compared with the other devices. In case of direct tunnelling leakage and retention time it was found that the met CNT embedded stack-2 device showed better characteristics. For erasing, however, the C60 embedded stack-1 device showed the smallest erase time. When compared with earlier reports, it was seen that CNT, C60 and Si NW embedded devices all performed better than nanocrystalline Si embedded MOS non-volatile memories.

Probing Drain Current with Vertical and Horizontal Electrical Fields under Temperature Stress on CLC TFTs

Thin-film transistors (TFT) usually exhibit non-uniform electrical characteristics fabricated by the identical process because of the formation of the grain boundary traps, bulk grain traps, interface states and some defects on channel region. All the traps and defects affecting the electrical characteristics of TFTs can be thermally and electrically activated. In this study, the temperature effect accompanying the horizontal and vertical electric fields stressing on continuous-wave green laser-crystallized (CLC) single-grain-like poly silicon TFTs (poly-Si TFTs), presenting the excellent effective electron mobility, up to 530 cm^2/V-s, was firstly investigated.

Inversion type InP metal oxide semiconductor field effect transistor using novel atomic layer deposited BeO gate dielectric

We present results on n-channel inversion-type indium phosphide (InP) metal-oxide-semiconductor field-effect transistors (MOSFETs) with atomic layer deposited (ALD) beryllium oxide (BeO) gate dielectric using the gate-last process. InP MOSFETs with the BeO gate stack were realized with high performance including the improved drive current, subthreshold swing, and a peak effective electron mobility. The transmission electron microscopy and x-ray photoemission spectroscopy measurements demonstrate an interface between BeO and InP substrates with high quality and efficient thermal stability. The use of ALD BeO as a gate dielectric may be a potential solution for future III-V MOS device fabrication.

A multi-level capacitor-less memory cell fabricated on a nano-scale strainedsilicon-on-insulator

A multi-level capacitor-less memory cell was fabricated with a fully depletedn-metal–oxide–semiconductor field-effect transistor on a nano-scale strained silicon channelon insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the siliconchannel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ∼ 1.7 times that with an unstrained silicon channel. This thereby enables both front- and back-gate celloperations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and12 µA memory margin. This is a step toward achieving a terabit volatile memory cell.

Room temperature device performance of electrodeposited InSb nanowire field effect transistors

InSb nanowires have been formed by electrodeposition in porous anodic alumina templates and employed as transistor channels. The 100 nm diameter nanowires had a zinc blende crystal structure. Single-nanowire field-effect transistors (NW-FETs) with a channel length of 500 nm exhibited on-currents of ∼40 μA, on/off ratios of ∼16–20, drain conductances of ∼71 μS and field-effect electron mobility of ∼1200 cm2 V−1 s−1. Compared with reported NW-FETs, the on-current is large and the current saturation occurs at low source-drain voltages. These characteristics can be understood in terms of velocity saturation effects with enhanced scattering.

On the calculation of effective electric field in In0.53Ga0.47As surface channel metal-oxide-semiconductor field-effect-transistors

The effective electron mobility of In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors with HfO2 gate oxide was measured over a wide range of channel doping concentration. The back bias dependence of effective electron mobility was used to correctly calculate the vertical effective electric field. The effective electron mobility at moderate to high vertical effective electric field shows universal behavior independent of substrate impurity concentration.

Strain-Induced Back Channel Electron Mobility Enhancement in Polycrystalline Silicon Thin-Film Transistors Fabricated by Continuous-Wave Laser Lateral Crystallization

Four-terminal (4T) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) having both front and back gates were fabricated to investigate the effect of the internal tensile strain induced by continuous-wave (CW) laser lateral crystallization (CLC) on the carrier mobility. The tensile strain values at the surfaces and back interfaces were estimated to be approximately 0.3% and over 0.4%, respectively. In both front and back channel operations, the successful operation of a variable threshold voltage (Vth) scheme was confirmed. Front and back channel effective electron mobilities of 4T CLC poly-Si TFTs were evaluated under bias conditions so as not to form an inversion layer on the Vth-control gate side. Because of the larger tensile strain at the back interface, the back channel effective electron mobility was 1.2 times larger than the front channel effective mobility.

Interface state densities, low frequency noise and electron mobility in surface channel In 0.53Ga 0.47As n-MOSFETs with a ZrO 2 gate dielectric

This paper reports on an investigation of interface state densities, low frequency noise and electron mobility in surface channel In 0.53Ga 0.47As n-MOSFETs with a ZrO 2 gate dielectric. Interface state density values of D it ∼ 5 × 10 12 cm −2 eV −1 were extracted using sub-threshold slope analysis and charge pumping technique. The same order of magnitude of trap density was found from low frequency noise measurements. A peak effective electron mobility of 1200 cm 2/Vs has been achieved. For these surface channel In 0.53Ga 0.47As n-MOSFETs, it was found that η parameter, an empirical parameter used to calculate the effective electric field, was ∼0.55, and is to be comparable to the standard value found in Si device.

Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs

Low-temperature electrical characteristics of n-type gate-all-around vertically-stacked silicon nanowire (SNW) field-effect transistors (FETs) with high- k/metal gate have been investigated and are compared to those with Fin and fully-depleted silicon-on-insulator (FD SOI) FETs. In particular, the effective electron mobilities behaviors are discussed. Nanowires with a rectangular cross section of 15 nm in width and 19 nm in height have shown a strongly degraded mobility as compared to those with Fin and FD SOI FETs. Low-temperature measurements have revealed that the mobility degradation is due to higher surface-roughness limited mobility. On the other hand, no significant difference in the interface trap densities among the kinds of FETs measured in the study have been observed from the temperature dependence in the subthreshold slope.

Manifestation of light and heavy electrons in the galvanomagnetic characteristics of Te-doped n-Bi0.88Sb0.12 single crystals

The components of resistivity (ρij), Hall coefficient (Rijk), and magnetoresistance (ρij, kl) of n-Bi0.88Sb0.12 single crystals doped with tellurium to 0.01, 0.1, and 0.2 at % have been measured in the temperature range of 77–300 K. It is concluded that light and heavy electrons are involved in transport processes. The energy spacing between the bands of light and heavy electrons is found to be 40 meV, and the ratios of the effective masses and electron mobilities are estimated as m2*/ml* = 3 and b ≈ 0.16, respectively.

Tuning the electronic effective mass in double-dopedSrTiO3

We present an approach to tune the effective mass in an oxide semiconductor by a double doping mechanism. We demonstrate this in a model oxide system Sr$_{1-x}$La$_x$TiO$_{3-\delta}$, where we can tune the effective mass ranging from 6--20$\mathrm{m_e}$ as a function of filling or carrier concentration and the scattering mechanism, which are dependent on the chosen lanthanum and oxygen vacancy concentrations. The effective mass values were calculated from the Boltzmann transport equation using the measured transport properties of thin films of Sr$_{1-x}$La$_x$TiO$_{3-\delta}$. Our method, which shows that the effective mass decreases with carrier concentration, provides a means for understanding the nature of transport processes in oxides, which typically have large effective mass and low electron mobility, contrary to the tradional high mobility semiconductors.

Transient and Steady State Currents of Bisphenol A Corncobs Sample

Transient current (I-t), current-voltage (I-V) characteristics, and dc conductivity ln(σ) for bisphenol A corn-cobs (BPACC) sample were investigated. At higher temperatures, I-V characteristics reveal that the dc cur-rent for the sample undergoes two regions one due to ohmic conduction and the other has been attributed to Space charge limited current (SCLC). The activation energy (Ea), the electron mobility μo), effective electron mobility ?μe), the concentration of the charge’s concentrations in conduction band, trapping factor (θ) and the trap concentration (Nt) were calculated. At lower temperatures, the dc current exhibits a peculiar behavior for I-t regime and I-V characteristics. Transient current of BPACC sample exhibits approximately constant value at constant electric field and it has saturation value for I-V characteristics. The attained results suggest strongly the applicability of this material in the electrical applications.

Vinyl-type polynorbornene with 9,9′-(1,1′-biphenyl)-4,4′-diylbis-9H-carbazole side groups as a host material for highly efficient green phosphorescent organic light-emitting diodes

The soluble polynorbornene (P1) bearing 9,9′-(1,1′-biphenyl)-4,4′-diylbis-9H-carbazole (CBP) side groups was investigated as a host material for green emitters in phosphorescent OLED devices. The vinyl addition polymerization of norbornene monomers using Pd(II) catalyst efficiently produces P1 in combination with 1-octene chain transfer agent. P1 exhibits high thermal stability with high decomposition (Td5 > 451 °C) and glass transition temperatures (Tg > 361 °C). The HOMO (ca. −5.5 eV) and LUMO (ca. −2.1 eV) levels with the triplet energy of ca. 2.60 eV suggest that P1 is suitable for a host material for green emitters. The solution-processed devices based on the emissive layers containing P1host doped with various concentration of fac-Ir(ppy)3 (1–6 wt%) display stable green emission of fac-Ir(ppy)3 with high device performances. The external quantum efficiency and power efficiency reach 7.2% and 11 lm/W, respectively, at the optimum doping concentration of fac-Ir(ppy)3 (2 wt%). The device performances are found to be slightly lower than those of PhOLED with molecular CBP host but higher than those of a PVK-based device. It is shown that in conjunction with the good processability of polynorbornene backbones, the high levels of the effective hole and electron mobilities of P1 (ca. 10−3 and 10−5 cm2/Vs, respectively) as well as large triplet energy inherited from CBP side groups are mainly responsible for the high performance of the phosphorescent OLEDs with solution-processed P1host:emitter layers.

Direct attachment of DNA to semiconducting surfaces for biosensor applications

In this work we propose a novel method of immobilizing nucleic acids for field effect or high electron mobility transistor-based biosensors. The naturally occurring 5′ terminal phosphate group on nucleic acids was used to coordinate with semiconductor and metal oxide surfaces. We demonstrate that DNA can be directly immobilized onto ZrO 2, AlGaN, GaN, and HfO 2 while retaining its ability to hybridize to target sequences with high specificity. By directly immobilizing the probe molecule to the sensor surface, as opposed to conventional crosslinking strategies, the number of steps in device fabrication is reduced. Furthermore, hybridization to target strands occurs closer to the sensor surface, which has the potential to increase device sensitivity by reducing the impact of the Debye screening length.

Analysis of trapping effects in AlGaN/GaN HEMTs based on near zero bias output conductance

AbstractA simple model is developed for characterization of current collapse caused by electron trapping in AlGaN/GaN HEMTs. Threshold voltages are extracted from near‐zero drain bias output conductance characteristics with respect to gate bias based on 0.2 μs pulsed I –V characteristics at different quiescent bias points. Other device parameters such as effective gate length and electron mobility are also estimated by fitting to a model equation. The results show that a higher negative electric field between gate and drain contacts cause a higher threshold voltage shift in the positive direction and a longer effective gate length, resulting in a larger current dispersion due to trapping of more electrons. (© 2010 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Ingrain and grain boundary scattering effects on electron mobility of transparent conducting polycrystalline Ga-doped ZnO films

Transparent conducting polycrystalline Ga-doped ZnO (GZO) films with different thicknesses were deposited on glass substrates at a substrate temperature of 200 °C by ion-plating deposition with direct current arc-discharge. The dependences of crystal structure, electrical, and optical properties of the GZO films on thickness have been systematically studied. Optical response due to free electrons of the GZO films was characterized in the photon energy range from 0.73 to 3.8 eV by spectroscopic ellipsometry (SE). The free electron response was expressed by the simple Drude model combined with the Tauc–Lorentz model. From the SE analysis and the results of Hall measurements, electron effective mass, m∗, and optical mobility, μopt, of the GZO films were determined, based on the assumptions that the films are homogeneous and optically isotropic. By comparing the μopt and Hall mobility, μHall, an indication on the effect of ingrain and grain boundary scattering limiting the electron mobility has been obtained. Moreover, the variation in scattering mechanism causing thickness dependence of μHall was correlated with the development of polycrystalline grain structure.