Interface Trap Effects Research Articles

Analysis of metal and zinc oxide semiconductor interface resistance using transmission line method

The transmission line method (TLM) is modified to analyze the contact resistance between the metal and zinc oxide semiconductor considering interface resistance. TCAD is used to simulate an ideal defect-less state and compare it with experimental result. It is found that the current transfer length can be overestimated in conventional TLM measurement. The importance of interface resistance is shown through interface trap and Schottky contact effect analysis: Resistance comparison between different metal used device, and the activation energy shift measurement after O2 pre-annealing. Based on these, the conventional resistance equation for TLM is corrected by separating channel resistance and non-ideal contact resistance. The mobility and temperature coefficient of resistance (TCR) of ZnO channel are extracted using the suggested method. This shows the importance of metal/semiconductor interface resistance in devices using semiconductor channel.

Research Progress of Polymers/Inorganic Nanocomposite Electrical Insulating Materials.

With the rapid development of power, energy, electronic information, rail transit, and aerospace industries, nanocomposite electrical insulating materials have been begun to be widely used as new materials. Polymer/inorganic nanocomposite dielectric materials possess excellent physical and mechanical properties. In addition, numerous unique properties, such as electricity, thermal, sound, light, and magnetic properties are exhibited by these materials. First, the macroscopic quantum tunneling effect, small-size effect, surface effect, and quantum-size effect of nanoparticles are introduced. There are a few anomalous changes in the physical and chemical properties of the matrix, which are caused by these effects. Second, the interaction mechanism between the nanoparticles and polymer matrix is introduced. These include infiltration adsorption theory, chemical bonding, diffusion theory, electrostatic theory, mechanical connection theory, deformation layer theory, and physical adsorption theory. The mechanism of action of the interface on the dielectric properties of the composites is summarized. These are the interface trap effect, interface barrier effect, and homogenization field strength effect. In addition, different interfacial structure models were used to analyze the specific properties of nanocomposite dielectric materials. Finally, the research status of the dielectric properties of nanocomposite dielectric materials in the electrical insulation field is introduced.

Research Progress on Polymeric Inorganic Nanocomposites Insulating Materials

With the rapid development of power energy, electronic information, rail transit, and aerospace industries, nanocomposite dielectric materials have been widely used as new materials. Polymer/inorganic nanocomposite dielectric materials possess excellent physical and mechanical properties. In addition, numerous unique properties such as electricity, thermal, sound, light, and magnetic properties are exhibited by these materials. First, the macroscopic quantum tunneling effect, small‐size effect, surface effect, and quantum‐size effect of nanoparticles are introduced. There are a few anomalous changes in the physical and chemical properties of the matrix, which are caused by these effects. Second, the interaction mechanism between the nanoparticles and polymer matrix is introduced. These include infiltration adsorption theory, chemical bonding, diffusion theory, electrostatic theory, mechanical connection theory, deformation layer theory, and physical adsorption theory. The mechanism of action of the interface on the dielectric properties of the composites is summarized. These are the interface trap effect, interface barrier effect, and homogenization field strength effect. In addition, different interfacial structure models were used to analyze the specific properties of nanocomposite dielectric materials. Finally, the research status of the dielectric properties of nanocomposite dielectric materials is introduced.

Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance

Recently, in accordance with the demand for development of low-power semiconductor devices, a negative capacitance field-effect-transistor (NC-FET) that integrates ferroelectric material into a gate stack and utilizes negative capacitive behavior has been widely investigated. Furthermore, gate-all-around (GAA) architecture to reduce short-channel effect is expected to be applied after Fin-FET technology. In this work, we proposed a compact model describing current–voltage (I–V) relationships of an NC GAA-FET with interface trap effects for the first time, which is a simplified model by taking proper approximation in each operating region. This is a surface potential-based compact model, which is suitable for evaluating the I–V characteristics for each operating region. It was validated that the proposed model shows good agreement with the results of implicit numerical calculations. In addition, by using the proposed model, we explored the electrical properties of the NC GAA-FET by varying the basic design parameters such as ferroelectric thickness (tfe), intermediate insulator thickness (tox), silicon channel radius (R), and interface trap densities (Net).

Effect of Interface Traps on the RTS Noise Behavior of Junctionless Nanowires

This work presents a study on the effects of single interface traps throughout the Junctionless Nanowire Transistor (JNT). The results are obtained by analyzing the Random Telegraph Signal noise of the device, which consists of an exception of the generation-recombination noise. The results obtained are mostly from numerical simulation, validated through experimental data. As in physical devices, it is impossible to obtain a single trap in specific locations, we have used a distribution of traps with similar characteristics in a way that they behave like a single trap. The results show the behave considering a set of traps distributions, using an exponential model. The traps are distributed from the conduction band to the valence band.
 Keywords– JNT; RTS Noise; G-r Noise; Interface Traps.

Interface and border trapping effects in normally-off Al2O3/AlGaN/GaN MOS-HEMTs with different post-etch surface treatments**Project supported by the National Natural Science Foundation of China (Grant Nos. 61704124, 11690042, and 61634005).

Trapping effect in normally-off Al2O3/AlGaN/GaN metal–oxide–semiconductor (MOS) high-electron-mobility transistors (MOS-HEMTs) with post-etch surface treatment was studied in this paper. Diffusion-controlled interface oxidation treatment and wet etch process were adopted to improve the interface quality of MOS-HEMTs. With capacitance–voltage (C–V) measurement, the density of interface and border traps were calculated to be 1.13 × 1012 cm−2 and 6.35 × 1012 cm−2, effectively reduced by 27% and 14% compared to controlled devices, respectively. Furthermore, the state density distribution of border traps with large activation energy was analyzed using photo-assisted C–V measurement. It is found that irradiation of monochromatic light results in negative shift of C–V curves, which indicates the electron emission process from border traps. The experimental results reveals that the major border traps have an activation energy about 3.29 eV and the change of post-etch surface treatment process has little effect on this major activation energy.

Effect of Interface Traps on the Device Performance of InGaAs-Based Gate-All-Around Tunneling Field-Effect Transistors.

The effect of interface traps on InGaAs-based vertical gate-all-around (GAA) tunneling field-effect transistors (TFETs) has been investigated using technology computer-aided design (TCAD) simulation. The interface traps distributed within different energy levels (Et) in the energy bandgap of a semiconductor material exhibit various influences on the device performances. In this work, InGaAs-based TFETs are simulated to analyze the effects on the on-state current (Ion), off-state current (Ioff), threshold voltage (Vth), subthreshold swing (SS), and the ambipolar characteristics according to Et and type of the interface traps. We have confirmed that Ioff and SS are degraded by the interface traps. Further, it can be shown that Ion is mainly affected by the acceptor-like traps and ambipolar behavior is affected by the donor-like traps. All the effects increase as Et becomes closer to the midgap. The effects of the interface traps with gate underlap and overlap at the source-channel region also have been investigated, considering the device fabrication. Additionally, the analysis of the effect of junction trap created at the source-channel junction has been performed.

Temperature and SiO2/4H-SiC interface trap effects on the electrical characteristics of low breakdown voltage MOSFETs

The temperature and carrier-trapping effects on the electrical characteristics of a 4H silicon carbide (4H-SiC) metal–oxide–semiconductor field effect transistor (MOSFET) dimensioned for a low breakdown voltage (BVDS) are investigated. Firstly, the impact of the temperature is evaluated referring to a fresh device (defects-free). In particular, the threshold voltage (Vth), channel mobility (µch), and on-state resistance (RON) are calculated in the temperature range of 300 K to 500 K starting from the device current–voltage characteristics. A defective MOSFET is then considered. A combined model of defect energy levels inside the 4H-SiC bandgap (deep and tail centers) and oxide-fixed traps is taken into account referring to literature data. The simulation results show that the SiO2/4H-SiC interface traps act to increase RON, reduce µch, and increase the sensitivity of Vth with temperature. In more detail, the deep-level traps in the mid-gap have a limited effect in determining RON once the tail traps contributions have been introduced. Also, for gate biases greater than about 2Vth (i.e., VGS > 12 V) the increase of mobile carriers in the inversion layer leads to an increased screening of traps which enhances the MOSFET output current limiting the RON increase in particular at low temperatures. Finally, a high oxide-fixed trap density meaningfully influences Vth (negative shifting) and penalizes the device drain current over the whole explored voltage range.

Interface trapping effects on the charge transport characteristics of LDPE/ZnO nanocomposites

This paper intends to reveal the interface trapping effect on the charge transport characteristics of LDPE/ZnO nanocomposite by combined study of the nanocomposite structures, trap level distributions, space charge distributions, conduction current and charge mobility. Experimental results show that nanofillers in the nanocomposites significantly altered the microstructure of the polymer matrix by introducing lots of smaller spherulites and increasing the crystallinity, leading to a significant increase in the interface areas between amorphous and crystalline regions. The trap density in the nanocomposites is about 2–6 times that in LDPE. The traps are essentially cavities, located at the interface areas between nanofillers and polymer matrix and interface areas between amorphous and crystalline regions. A new method was proposed to evaluate the carrier mobility as a function of discharge time and trap depth from the IDC results directly. The carrier mobility of LDPE is about 4–20 times higher than that of the nanocomposites. Compared with LDPE, bulk space charge accumulation is significantly suppressed in the nanocomposites. An interesting discovery is that there is a clear correspondence between the space charge accumulation and current increase in I-t characteristics under high electric field. The study indicates that the low charge carrier mobility and space charge suppression in LDPE/ZnO nanocomposites and the I-t behavior are all closely related to the interface trapping effects in the nanocomposites.

Characterization of Scaling in Ultra-Thin Poly-Si and Analysis of the Scaling Limit of Thin Film Thickness

Ultra-thin poly-Si channel has been widely studied and has already been adopted commercially by semiconductor manufacturers due to its short channel effect suppression and sub-threshold swing improvement. It is well known that the threshold voltage, VTH, increase as the poly-Si thickness, ts, is scaled below 10nm, due to quantum-mechanical (QM) effects. Although experiment results of VTH demonstrated identical behavior of increasing as ts was scaled, but the measured absolute VTH show significantly larger value than the expectation. The major problem of abrupt VTH increase is that it degenerate VTH distribution, which would cancel out merits of ultra-thin poly-Si device on high speed performance. Simulation results show the abrupt VTH increase is caused by a combined effect of bulk and front/back interface trap charges. As scaled down, yet the bulk trap density decrease, VTH is increased as it is overturned by front and back interface trap charge effects. Compared to front interface trap charges, back interface trap charges have larger influence on VTH. Since device with ts below 10nm is fully depleted before the gate voltage reaches VTH, the additional electric field formed across the poly-Si channel parallel shifts the band downwards. So the more parallel shifted the band is, the more additional portion of the front and back interface is filled with negative charge. As a result back interface charges increase VTH. The closer it gets to the channel, greater the influence become. It is quite clear why back interface trap charges contribute more to the VTH, compared with front interface trap charges. The simulation results considering bulk and front/back interface trap effects showed a good match experiment results. Considering the abrupt VTH increase and variation of poly-Si deposition process, the fundamental criterion of poly-Si thickness scaling limit should be no lower than 5nm.

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations**Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601), the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129), and the Opening Project of Key Laboratory of Microelectronics Devices

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown (TDDB) characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper. Based on experimental results, it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer. From the charge pumping measurement and secondary ion mass spectroscopy (SIMS) analysis, it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density. In addition, the influences of interface and bulk trap density ratio Nit/Not are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo (kMC) method. The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.

An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects

An improved analytical model for the current—voltage (I–V) characteristics of the 4H-SiC metal semiconductor field effect transistor (MESFET) on a high purity semi-insulating (HPSI) substrate with trapping and thermal effects is presented. The 4H-SiC MESFET structure includes a stack of HPSI substrates and a uniformly doped channel layer. The trapping effects include both the effect of multiple deep-level traps in the substrate and surface traps between the gate to source/drain. The self-heating effects are also incorporated to obtain the accurate and realistic nature of the analytical model. The importance of the proposed model is emphasised through the inclusion of the recent and exact nature of the traps in the 4H-SiC HPSI substrate responsible for substrate compensation. The analytical model is used to exhibit DC I–V characteristics of the device with and without trapping and thermal effects. From the results, the current degradation is observed due to the surface and substrate trapping effects and the negative conductance introduced by the self-heating effect at a high drain voltage. The calculated results are compared with reported experimental and two-dimensional simulations (Silvaco®-TCAD). The proposed model also illustrates the effectiveness of the gate—source distance scaling effect compared to the gate—drain scaling effect in optimizing 4H-SiC MESFET performance. Results demonstrate that the proposed I–V model of 4H-SiC MESFET is suitable for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

The Research of Trap Level Distribution of PI/AlN (Treated)-MMT Films with Different Contents Based on Decay Charge Theory

Through the theoretical deviation based on charge decay theory a trap level distribution function relative to the isothermal discharge current is given in this paper. Based on that, the effect of AlN(treated)-MMT nanoparticles with different contents of 1wt%, 3wt%, 5wt% on surface trap level distribution is researched. The experimental results show that the trap level density is significantly increased compared with traditional IDC and TSC methods. Trap level density and the number of trap charges increase due to the doping AlN (treated)-MMT nanoparticles, and increase with doping contents. The maximum trap energy level density of AlN(treated)-MMT film with 5wt% is 9.14×1024/(eV·m3), which is 3.3 times compared with the PI film corresponding to the trap level in the range of 1.0~1.1eV. The trap level density is affected by the interface trap effect caused by the AlN(treated)-MMT nanoparticles and different contents.

In situ SiNx gate dielectric by MOCVD for low‐leakage‐current ultra‐thin‐barrier AlN/GaN MISHEMTs on Si

In situ SiNx grown by metal‐organic chemical vapor deposition (MOCVD) was employed as the gate dielectric for ultra‐thin‐barrier AlN/GaN metal‐insulator‐semiconductor high electron mobility transistors (MISHEMTs) on Si substrates. Despite the ultra‐thin barrier of 1.5 nm, low reverse leakage current of below 10−7 A cm−2 was obtained with a 7 nm in situ SiNx gate dielectric. The good surface passivation effects of in situ SiNx were also demonstrated by the enhanced source/drain (S/D) current density and the reduced drain current degradation. Furthermore, interface trapping effects in the in situ SiNx/AlN/GaN heterostructures were investigated by double‐mode capacitance–voltage (C–V) measurements and frequency dependent conductance analysis. A trap states density of 1.9–3.4 × 1012 cm−2 eV−1 with a time constant of 0.8–17 µs were deduced.

Frequency and voltage-dependent electrical and dielectric properties of Al/Co-doped PVA/p-Si structures at room temperature

In order to investigate of cobalt-doped interfacial polyvinyl alcohol (PVA) layer and interface trap (Dit) effects, Al/p-Si Schottky barrier diodes (SBDs) are fabricated, and their electrical and dielectric properties are investigated at room temperature. The forward and reverse admittance measurements are carried out in the frequency and voltage ranges of 30 kHz–300 kHz and −5 V–6 V, respectively. C–V or ε′–V plots exhibit two distinct peaks corresponding to inversion and accumulation regions. The first peak is attributed to the existence of Dit, the other to the series resistance (Rs), and interfacial layer. Both the real and imaginary parts of dielectric constant (ε′ and ε″) and electric modulus (M′ and M″), loss tangent (tan δ), and AC electrical conductivity (σac) are investigated, each as a function of frequency and applied bias voltage. Each of the M′ versus V and M″ versus V plots shows a peak and the magnitude of peak increases with the increasing of frequency. Especially due to the Dit and interfacial PVA layer, both capacitance (C) and conductance (G/w) values are strongly affected, which consequently contributes to deviation from both the electrical and dielectric properties of Al/Co-doped PVA/p-Si (MPS) type SBD. In addition, the voltage-dependent profile of Dit is obtained from the low–high frequency capacitance (CLF−CHF) method.

Characterization of in situ SiNx thin film grown on AlN/GaN heterostructure by metal-organic chemical vapor deposition

We report an investigation of in situ SiNx gate dielectric grown on AlN/GaN heterostructures by metal-organic chemical vapor deposition. It is revealed that the in situ SiNx is Si-rich, with a N/Si ratio of 1.21 and a relatively high effective dielectric constant of ∼8.3. The 7 nm in situ SiNx film exhibited a large resistivity of >1014 Ω · cm and a breakdown field of 5.7 MV/cm. Furthermore, interface trapping effects in the in situ SiNx/AlN/GaN heterostructures were investigated by frequency dependent conductance analysis.

Numerical and Experimental Assessment of Charge Control in III–V Nano-Metal-Oxide-Semiconductor Field-Effect Transistor

III-V Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with a gate stack based on high-kappa dielectric appears as an appealing solution to increase the performance of either microwave or logic circuits with low supply voltage (V(DD)). The main objective of this work is to provide a theoretical model of the gate charge control in III-V MOS capacitors (MOSCAPs) using the accurate self-consistent solution of 1D and 2D Poisson-Schrödinger equations. This study allows us to identify the major mechanisms which must be included to get theoretical calculations in good agreement with experiments. Actually, our results obtained for an Al2O3/In0.53Ga0.47As MOSCAP structure are successfully compared to experimental measurements. We evaluate how III-V MOS technology is affected by the density of interface states which favors the Fermi level pinning at the Al2O3/In0.53Ga0.47As interface in both depletion and inversion regimes, which is a consequence of the poor gate control of the mobile inversion carrier density. The high energy valleys (satellite valleys) contribution observed in many theoretical calculations appears to be fully negligible in the presence of interface states. The enhancement of doping density in the channel is shown to improve the short-channel effect (SCE) immunity but to the price of higher sensitivity to the interface trap effect which manifests through a low Fermi level movement efficiency at interface in OFF-state and a low inversion carrier density in ON-state, even in the long channel case.

Controllable p–n Switching Behaviors of GaAs Nanowires via an Interface Effect

Due to the extraordinary large surface-to-volume ratio, surface effects on semiconductor nanowires have been extensively investigated in recent years for various technological applications. Here, we present a facile interface trapping approach to alter electronic transport properties of GaAs nanowires as a function of diameter utilizing the acceptor-like defect states located between the intrinsic nanowire and its amorphous native oxide shell. Using a nanowire field-effect transistor (FET) device structure, p- to n-channel switching behaviors have been achieved with increasing NW diameters. Interestingly, this oxide interface is shown to induce a space-charge layer penetrating deep into the thin nanowire to deplete all electrons, leading to inversion and thus p-type conduction as compared to the thick and intrinsically n-type GaAs NWs. More generally, all of these might also be applicable to other nanowire material systems with similar interface trapping effects; therefore, careful device design considerations are required for achieving the optimal nanowire device performances.

Interface-Trap Effects in Inversion-Type Enhancement-Mode $\hbox{InGaAs/ZrO}_{2}$ N-Channel MOSFETs

Interface-trap effects are analyzed in inversion-type enhancement-mode In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> /ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As/In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.2</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.8</sub> As/ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> n-channel MOSFETs by comparing the measurements and the numerical device simulations of dc transfer characteristics. Device simulations can reproduce measured threshold voltages under the hypothesis that interface traps are donorlike throughout the InGaAs band gap, allowing for strong inversion operation regardless of the relatively high interface-trap density. The effects induced by the donorlike interface traps in MOSFETs having a thin cap layer interposed between gate dielectric and channel are qualitatively different from those observed in standard MOSFETs (without the cap). Increasing the donorlike trap density decreases the threshold voltage in capped devices, whereas it leaves it unchanged in uncapped ones. As a result, donorlike interface traps can explain the threshold-voltage difference observed in MOSFETs with and without the cap.

Effect of Interface Traps and Oxide Charge on Drain Current Degradation in Tunneling Field-Effect Transistors

In this letter, we report for the first time the degradation mechanism of drain current in tunneling field-effect transistors (TFETs). Using positive-bias and hot-carrier (HC) stress experiments and TCAD simulation, we show that the drain current degradation is mainly induced by the interface traps and/or oxide charge located above the tunneling region, causing reduction of tunneling field and tunneling current. The interface traps mainly induce the degradation in transconductance, while the oxide charge essentially causes a threshold-voltage shift in TFETs. The results show that the interface-trap generation is dominant under a positive-bias stress, while the oxide-charge creation is important under an HC stress in n-TFETs.