Dynamic Warpage Research Articles

A full-field warpage characterization measurement method coupled with infrared information

The thermomechanical properties of microelectronic packages can serve as important indicators of reliability. Indeed, it is of great interest in dynamic warpage measurement of deformation and temperature of the local package structure to explore the evolutionary mechanism. In this paper, a full-field warpage characterization measurement method coupled with the infrared information is proposed to quantitatively evaluate the thermomechanical properties of microelectronic devices. A heat source is used to illuminate the calibration board of the infrared image to facilitate multi-camera calibration. After performing a series of image processing procedures, a clear grayscale infrared image of the calibration board was easily obtained, and the calibration between the infrared camera and the optical camera was realized. The thermomechanical properties of the copper thermoelectric cooler were explored after fully verifying the accuracy and error of the measurement. There is an obvious positive correlation between the full-field temperature and warpage of the cooler. The feasibility and validity of the measurement system were validated.

Preparation and performance of Sn-based composite solder joints by solid-liquid low-temperature solder bonding technology

In the era of big data, the advantages of 3D packaging are becoming increasingly significant. In addition, the mismatch between the coefficient of thermal expansion (CTE) of the PCB and BGA components leads to dynamic warpage of the system, and the expansion and innovation of low-temperature soldering have been a new trend. We developed a fully mixed solder joint of a SAC305(Sn-3.0Ag-0.5Cu wt.%) solder ball and Sn–58Bi(wt.%) solder paste by solid-liquid low-temperature solder bonding technology. The mixing degree and diffusion process of the two were calculated and simulated by mathematical calculation and COMSOL Multiphysics. The results show that a completely mixed solder joint can be obtained after reflow at 210 °C for 5 min. The average shear strength of the composite solder joints was 63.68 ± 1.12 MPa, which was about twice that of the single SAC305 and Sn58Bi solder joints, and the shear fracture was a composite mode of brittle and ductile fracture, which appeared in the IMC and the solder, respectively. After complete mixing, the solder wettability angle was less than 26.68°, with outstanding wetting properties. No phase transition occurred after aging, the distribution of each phase remained uniform, and no enrichment of the brittle phase was observed at the interface. The shear strength decreased slightly with aging time, and the reduction value was less than 10 MPa, which has good reliability.

Dynamic warpage simulation of molded PCB under reflow process

PurposeThis study aims to simulate molded printed circuit board (PCB) warpage behavior under reflow temperature distribution. Simulation models are used to estimate dynamic warpage behavior for different form factor sizes.Design/methodology/approachThis study analyzes warpage during the reflow process. The shadow moiré experiment methodology is used to collect data on the dynamic warpage performance of a model with a form factor of 10mm × 10mm × 1mm. The temperature profile with heating from 25°C to 300°C at intervals of 50°C is used, and the sample is made to undergo a cooling process until it reaches the room temperature. Subsequently, ANSYS static structural simulation is performed on similar form factor models to ascertain the accuracy of the simulation results.FindingsResults show that the deformation and total force induced by coefficient of thermal expansion (CTE) mismatch are examined based on the warpage performance of models with different sizes, that is, 45mm × 45mm × 1mm and 45mm × 15mm × 1mm. Compared with the experimental data, the simulated modeling accuracy yields a less than 5% deviation in the dynamic warpage prediction at a reflow temperature of 300°C. Results also reveal that the larger the model, the larger the warpage changes under the reflow temperature.Research limitations/implicationsThe simulated warpage is limited to the temperature and force induced by CTE mismatch between two materials. The form factor of the ball-grid array model is limited to only three different sizes. The model is assumed to be steady, isothermal and static. The simulation adopts homogenous materials, as it cannot accurately model nonhomogeneous multilayered composite materials.Practical implicationsThis study can provide engineers and researchers with a profound understanding of molded PCB warpage, minimal resource utilization and the improved product development process.Social implicationsThe accurate prediction of molded PCB warpage can enable efficient product development and reduce resources and production time, thereby creating a sustainable environment.Originality/valueThe literature review points out that warpage in various types of PCBs was successfully examined, and that considerable efforts were exerted to investigate warpage reduction in PCB modules. However, PCB warpage studies are limited to bare PCBs. To the best of the authors’ knowledge, the examination of warpage in a molded PCB designed with a molded compound cover, as depicted in Figure 3, is yet to be conducted. A molded compound provides strong lattice support for PCBs to prevent deformation during the reflow process, which is a topic of considerable interest and should be explored.

Head-on-Pillow Defect Detection: X-Ray Inspection Limitations

Abstract Both the number and the variants of ball grid array packages (BGAs) are tending to increase on network printed board assemblies with sizes ranging from a few millimeter die size wafer level packages with low ball count to large multidie system-in-package (SiP) BGAs with 60–70 mm side lengths and thousands of I/Os. One big challenge, especially for large BGAs, SiPs, and for thin fine-pitch BGA assemblies, is the dynamic warpage during the reflow soldering process. This warpage could lead to solder balls losing contact with the solder paste and its flux during parts of the soldering process, and this may result in solder joints with irregular shapes, indicating poor or no coalescence between the added solder and the BGA balls. This defect is called head-on-pillow (HoP) and is a failure type that is difficult to determine. In this study, x-ray inspection was used as a first step to find deliberately induced HoP defects, followed by prying off of the BGAs to verify real HoP defects and the fault detection correlation between the two methods. The result clearly shows that many of the solder joints classified as potential HoP defects in the x-ray analysis have no evidence at all of HoP after pry-off. This illustrates the difficulty of determining where to draw the line between pass and fail for HoP defects when using x-ray inspection.

Recent progress on the development of Sn–Bi based low-temperature Pb-free solders

With the implementation of legislations on inhibiting the usage of Sn–Pb solder in consumer electronic products, Sn–Ag–Cu series solder has been gotten the most application. However, there are some stimulations from electronic manufacturers to adopt low temperature soldering such as the economic driver from the reduction in manufacturing assembly cost and the reliability driver to avoid the dynamic warpage of area array components caused from Sn–Ag–Cu solder. Sn–Bi series solder is one of the promising candidates, which met the requirements for low melting point, low cost and environment friendly. However, the disadvantage of brittleness characteristic prevented its wide practical application. In order to promote the better application of Sn–Bi based solders, many efforts have been made to improve the wettability, mechanical properties and reliability of Sn–Bi based solders. This paper will summarize the related results about Sn–Bi solder alloys from wettability, interfacial reaction, mechanical properties of Sn–Bi solder and reliabilities of Sn–Bi solder joints. Moreover, in order to improve the properties of Sn–Bi solders, researchers have done lots of works on effect of addition of element dopants. The corresponding works of effect of alloying elements on the properties of Sn–Bi solder were also focused. According to the existing research results, it provides an important basis of understanding the current development of Sn–Bi solders.

Impact of processing conditions and solder materials on surface mount assembly defects

The conversion to lead-free solder alloys and increasing dynamic warpage due to the coefficient of thermal expansion (CTE) mismatch and thinner microelectronic packaging technology has resulted in a significant increase in the risk of solder joint defects for ball grid array (BGA) components. This paper will review head-and-pillow (HnP) defects observed after surface mount assembly with specific focus on fine-pitch BGA technology on motherboards. The mechanisms related to various aspects of design and materials characteristics that affect the creation of these defects within the solder joints will be discussed. Finally, potential material solutions for eliminating these defects will be reviewed.

Measurement of Dynamic Warpage During Thermal Cycling of Dielectric Coated SS Substrates for Large Area MCM-D Packaging

Potential application of stainless steel (SS) as a base substrate material for a large area MCM-D packaging is reported in this paper. A test vehicle was fabricated using 0.008 in. thick and 12 in.×12 in. SS panel with laser drilled 0.01 in. vias. A dielectric material (Parylene N) was deposited on the SS panel and around the inside via walls in order to electrically isolate the via filling material from the body of the SS substrate and also making the SS surface non-conductive. Vias were filled using a commercially available conductive via-plug material. The test structure was exposed to elevated temperatures to simulate the thermal excursion the substrate would be subjected to during the MCM-D thin film process. The end objective of this work is to be able to fabricate large area (24 in.×24 in.) SS substrates for next generation MCM-D packaging with reduced warpage. This paper reports results of the dynamic warpage measurement during thermal cycling of a 12 in.×12 in. Parylene N coated SS substrate. [S1043-7398(00)00602-2]