Dynamic Reconfiguration Scheme Research Articles

Automatic PV Array Reconfiguration under Partial Shading Conditions

Photovoltaic (PV) arrays have been recognized as one of the main clean renewable sources of electrical energy. In practice, PV arrays are subject to unavoidable non-uniform partial shading (PS) due to clouds, buildings, dust, etc. PS causes the hot spot problem, mismatch losses, and output power degradation. A widely used approach to mitigate the effect of PS is dynamic reconfiguration, where, the interconnection of PV panels is modified according to the shading condition to achieve maximum output. Dynamic reconfiguration techniques use sensors, a programmable controller, and a switch matrix for optimal operation. However, they have drawbacks such as system complexity and scalability issues. For instance, reducing the number of switches limits the flexibility of the reconfiguration algorithm. In this paper, an automatic dynamic reconfiguration scheme is proposed in which PV panel irradiation activity controls the interconnection of switches, without the need for a programmable controller. A modular building block is proposed from which easily scalable PV arrays can be constructed in a hierarchical manner. Experimental and analytic results have verified the effectiveness of the proposed reconfiguration scheme.

A Dynamic Reconfiguration Scheme for Embedded System Based on Multi-core DSP

High-performance embedded system is needed in high-speed and accurate avionics control systems, but its hardware resources are limited. It is of great significance to reuse hardware resource through static or dynamic reconfiguration. A dynamic local reconfiguration scheme is designed based on c6678 isomorphic multi-core DSP to realize the dynamic reconfiguration of software on a single core under the premise of ensuring the normal operation of the whole system. This reconfiguration scheme can realize the complete switching of software on the whole core and realize the time division multiplexing of multiple algorithms in the same memory space. Experimental results show that the scheme can fully meet the requirements of real-time.

The Cloud-edge-based Dynamic Reconfiguration to Service Workflow for Mobile Ecommerce Environments

The emergence of mobile service composition meets the current needs for real-time eCommerce. However, the requirements for eCommerce, such as safety and timeliness, are becoming increasingly strict. Thus, the cloud-edge hybrid computing model has been introduced to accelerate information processing, especially in a mobile scenario. However, the mobile environment is characterized by limited resource storage and users who frequently move, and these characteristics strongly affect the reliability of service composition running in this environment. Consequently, applications are likely to fail if inappropriate services are invoked. To ensure that the composite service can operate normally, traditional dynamic reconfiguration methods tend to focus on cloud services scheduling. Unfortunately, most of these approaches cannot support timely responses to dynamic changes. In this article, the cloud-edge based dynamic reconfiguration to service workflow for mobile eCommerce environments is proposed. First, the service quality concept is extended. Specifically, the value and cost attributes of a service are considered. The value attribute is used to assess the stability of the service for some time to come, and the cost attribute is the cost of a service invocation. Second, a long short-term memory (LSTM) neural network is used to predict the stability of services, which is related to the calculation of the value attribute. Then, in view of the limited available equipment resources, a method for calculating the cost of calling a service is introduced. Third, candidate services are selected by considering both service stability and the cost of service invocation, thus yielding a dynamic reconfiguration scheme that is more suitable for the cloud-edge environment. Finally, a series of comparative experiments were carried out, and the experimental results prove that the method proposed in this article offers higher stability, less energy consumption, and more accurate service prediction.

Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches

By using through-silicon-vias (TSV), three dimension integration technology can stack large memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory access and enhance system performance. However, the integration of more on-chip caches increases chip power density, which might lead to temperature-related issues in power consumption, reliability, cooling cost, and performance. An effective thermal management scheme is required to ensure the performance and reliability of the system. In this study, a fuzzy-based thermal management scheme (FBTM) is proposed that simultaneously considers cores and stacked caches. The proposed method combines a dynamic cache reconfiguration scheme with a fuzzy-based control policy in a temperature-aware manner. The dynamic cache reconfiguration scheme determines the size of the cache for the processor core according to the application that reaches a substantial amount of power consumption savings. The fuzzy-based control policy is used to change the frequency level of the processor core based on dynamic cache reconfiguration, a process which can further improve the system performance. Experiments show that, compared with other thermal management schemes, the proposed FBTM can achieve, on average, 3 degrees of reduction in temperature and a 41% reduction of leakage energy.

Dynamic partial reconfiguration scheme for fault‐tolerant FFT processor based on FPGA

The fast Fourier transform FFT processor is an important part of the space real-time signal processing system based on field programmable gate array (FPGA). Since occupying a large amount of logical resources and storage resources, FFT processor is more vulnerable to high-energy particles in space, resulting in single event upset (SEU). This paper presents a novel FPGA scrubbing framework base on dynamic partial reconfiguration technique for a FFT processor to mitigate SEU. The proposed scheme is compared with the blind scrubbing, the reconfiguration time is reduced by 78%. Then, the resource utilisation is 61.5% less than triple modular redundancy scheme. This paper also presents a DPR controller for FFT processor, which is evaluated in terms of hardware resources and reconfiguration time. A comparison to the Xilinx PRC IP shows that multipath delay feedback FFT controller saves 38.6% resources.

Towards Dynamically Reconfigurable IoT Camera Virtualization for Video Analytics Edge Cloud Services

Video analytics edge computing exploiting IoT cameras has gained high attention. Running such tasks on the network edge is very challenging since video and image processing are bandwidth-hungry and computationally intensive. IoT cameras are heavily dependent on environmental factors such as the brightness of the view. In this paper, we propose an edge IoT camera virtualization architecture that enables an IoT camera to accommodate multiple application operation semantics and dynamically adjust its configuration to preserve them in the presence of environment context changes. For this, we develop an ontology-based application description model, a virtualization architecture with the container technology, and a context-aware dynamic reconfiguration scheme.

AN OPTIMIZED ARCHITECTURE FOR DYNAMIC RECONFIGURABLE FIR FILTER IN SPEECH PROCESSING

In this paper, we have proposed a Dynamic Reconfiguration Scheme (DRS) for the FIR filter in which the existing multiplier of the FIR filter is replaced by the proposed Estimation Distribution Multiplier Blocks (EDMB). The important aspect of the proposed DRS is that it provides an efficient area and power optimization while implementing in hardware. To ensure the versatility of the proposed method and to further evaluate the performance and correctness of the structure in terms of area and power consumption, we have implemented the hardware in Xilinx Virtex 7 Field Programmable Gate Array (FPGA) device and synthesized with Cadence RTL Compiler using TSMC 180 nm standard cell library. The experimental analysis of the proposed reconfigurable design approach takes speech signal as the benchmark input. The analysis shows that the proposed technique is better when compared to the existing reconfiguration techniques with 43.60% power savings and 6.34% area reduction.

Scheduling for Time-Constrained Big-File Transfer Over Multiple Paths in Cloud Computing

Enormous increase in the scale of big-file generated by cloud computing has brought many challenges to both computational and transfer infrastructures. For large file transfer in cloud computing, the scheduling with intelligent routing is indispensable to improve the efficiency of network resource, especially when file transfer over multiple paths is allowed. However, it is a non-trivial task to efficiently select a set of feasible paths for file transfer under a tight delay constraint. In this paper, we consider two kinds of file transfer scheduling problems: single-file transfer scheduling (SFTS) and multi-file transfer scheduling (MFTS), both of which require the file transfer to be conducted under a delay constraint. To address the SFTS problem, a heuristic algorithm together with an exact algorithm SFTS-A is proposed. Comparing with the exact algorithm, the heuristic algorithm takes less running time and is able to address the SFTS problem efficiently although the solution may not be optimal, which is adequately illustrated by simulation results. For the MFTS problem, we propose a heuristic algorithm MFTS-H with dynamic reconfiguration scheme for addressing the transfer scheduling problem for multiple concurrent files. The corresponding simulation results demonstrate that the proposed algorithm can efficiently support multiple file transfer over multiple paths in terms of delay and bandwidth utilization.

Multi-period Reconfiguration of the Distribution Network Based on the Improved EM Algorithm

Developing with the time, the distribution network technology has become increasingly perfect and mature. But with the improvement of people's living standards, the variety of the load is changing, the amount of the load is increasing, such as the electric vehicle as one of the members has gradually come into our life. Large-scale electric cars access to distribution network, the randomness and dispersion of electric cars put forward new requirements to management of the distribution network, and give challenges to the load capacity of transmission lines. In order to make the distribution network that contains electric vehicles run under the condition of safe, economic and steady, this paper make the distribution network into period divisions according to the characteristics of electric vehicle and the similarity of load, put forward a kind of distribution network dynamic reconfiguration scheme that based on the improved EM algorithm to solve distribution network optimal operation state.

Reconfiguración Dinámica de Sistemas Distribuidos en Tiempo-Real Basada en Agentes

Currently distributed systems are present in several applications in industry and research, such systems are restricted to time conditions. The presence of failures in these time critical systems requires decision making to avoid loss of deadlines, performance, instability or total suspension of the system. A strategy for achieving this is the dynamic reconfiguration of the structure of the system aimed at counteracting the effect of such failures. This article presents a proposal for dynamic and distributed reconfiguration considering each element of the distributed system as an agent with communication and cooperation capabilities to act joint with other agents to generate a reconfiguration action. These actions are the modification of sampling periods of sensors agents, decreased activity of the agents with fails and/or use of voting algorithms. For each type of system failure correspond a particular type of reconfiguration which is reached based on exchange of information between agents and the agreement they reached. The proposed dynamic reconfiguration scheme is implemented in the flight control of a prototype helicopter with two propellers through the inclusion in the closed loop control of a distributed system that uses a common communication media. The results of the reconfigured system response are obtained through numerical simulations carried out using Matlab and Simulink, as Real- Time simulation tool was used TrueTime.

Molecule: An adaptive dynamic reconfiguration scheme for sensor operating systems

In wireless sensor networks, sensor nodes are located on remote-site and thus it is very difficult to re-gather them. To update or add a program at run-time of the sensor nodes, sensor operating system must support a dynamic reconfiguration. Many kinds of different mechanisms for reconfiguring sensor nodes have been developed ranging from full image replacement to virtual machines. In previous schemes, dynamic linker supports only indirect linking between modules, and the linking is performed on the sensor nodes. Those may increase overhead of the execution time and energy consumption. In this paper, we present an adaptive and dynamic reconfiguration scheme called Molecule for sensor nodes. In Molecule, applications, kernel features, and device drivers are managed as a form of module. By using the cost analysis of the expected execution time of each module, Molecule selects an appropriate method between direct and indirect linking to link modules. It also supports remote linker to exclude the linking overhead from the sensor nodes. Our experimental results show that Molecule performs efficiently in terms of the energy consumption and execution time compared with the existing dynamic reconfiguration schemes.

Deadlock-free dynamic reconfiguration schemes for increased network dependability

Network-based parallel computing systems often require the ability to reconfigure the routing algorithm to reflect changes in network topology if and when voluntary or involuntary changes occur. The process of reconfiguring a network's routing capabilities may be very inefficient and/or deadlock-prone if not handled properly. We propose efficient and deadlock-free dynamic reconfiguration schemes that are applicable to routing algorithms and networks which use wormhole, virtual cut-through, or store-and-forward switching, combined with hard link-level flow control. One requirement is that the network architecture use virtual channels or duplicate physical channels for deadlock-handling as well as performance purposes. The proposed schemes do not impede the injection, transmission, or delivery of user packets during the reconfiguration process. Instead, they provide uninterrupted service, increased availability/reliability, and improved overall quality-of-service support as compared to traditional techniques based on static reconfiguration.

A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse‐grain Parallelism

A dynamically reconfigurable scheme for video encoder to switch among many different applications is presented. The scheme is suitable for FPGA implementation and conforms to JPEG, MPEG‐1, MPEG‐2, and H.263 standards. The scheme has emerged as an efficient and cost‐effective solution for video compression as a result of innovative design using well‐partitioned algorithms, highly pipelined architecture and coarse‐grain parallelism. The reconfiguration time of the video encoder is less than 320 μs while switching from one standard to another. Although the dynamic reconfiguration scheme is presented for a video encoder, the same design methodology may be applied effectively for any other application.

Dynamic reconfiguration schemes for megabit BiCMOS SRAMs and performance evaluation

In this paper two dynamic configuration schemes are discussed for megabit BiCMOS static random access memories (SRAMs). Dynamic reconfiguration schemes allows failure detection at the chip level and automatic reconfiguration to fault free memory cells within the chip. The first scheme is a standby system approach where the I/O lines of the memory can be dynamically switched to spare bit slices in the SRAM. This scheme is implemented through a switching network at the memory interface. Every memory access is controlled by a fault status table (FST) which memorizes the fault conditions of each memory block. This FST is implemented outside the memory system. A second dynamic reconfiguration scheme for BiCMOS SRAMs is addressed through a graceful degradation approach. Basic design considerations and performance evaluation of megabit BiCMOS SRAMs using dynamic reconfiguration schemes are presented. The basic properties of the proposed schemes and a prototype VLSI chip implementation details are discussed. BiCMOS SRAM access time improvement of about 35%, chip area of 25%, and chip yield of 10% are achieved, respectively, as compared to conventional methods. A comparison of reliability improvement of 1 Mb BiCMOS SRAMs using dynamic configuration schemes is presented. These two dynamic reconfiguration schemes have considerable importance in reliability improvement when compared to conventional methods. The major advantage is that the size of reconfiguration of the system can be considerably reduced.

A dynamic reconfiguration scheme for mega bit Static Random Access Memories

The objective of this paper is to present a novel dynamic reconfiguration scheme for mega bit Static Random Access Memories (SRAMs). Most of the conventional reconfiguration methods are implemented using two-way switching elements. The proposed scheme is based on on-chip word failure detection and reconfiguration to spare word cell using multi-valued logic elements. The physical concept of the dynamic reconfiguration scheme and implementation details are discussed. Based on the SRAM dynamic reconfiguration implementation a reliability model is develoed. Dyanamic reconfiguration scheme reliability comparisons with other existing methods are presented. The advantages of the proposed dyanamic reconfiguration scheme are highlighted.

Topology design and bandwidth allocation in ATM nets

The design of a P/S network embedded into a backbone facility network is discussed. The problem is formulated as a network optimization problem where a congestion measure based on the average packet delay is minimized, subject to capacity constraints posed by the underlying facility trunks. The variables in this problem are the routing on the express pipes (i.e. the channels that interconnect the P/S modes) and the allocation of bandwidth to such pipes. An efficient algorithm is presented for the solution of the above problem and it is applied to some representative examples. It is shown that for some test cases the congestion measure is substantially reduced with respect to the values obtained when the embedded topology is kept identical to the backbone topology. Dynamic reconfiguration schemes where the embedded topology is periodically adjusted to track the fluctuations in traffic requirements are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>