Dynamic Reconfiguration Capabilities Research Articles

Multi-criteria Optimization of Real-time DAGs on Heterogeneous Platforms under P-EDF

This article tackles the problem of optimal placement of complex real-time embedded applications on heterogeneous platforms. Applications are composed of directed acyclic graphs of tasks, with each directed-acyclic-graph (DAG) having a minimum inter-arrival period for its activation requests and an end-to-end deadline within which all of the computations need to terminate since each activation. The platforms of interest are heterogeneous power-aware multi-core platforms with Dynamic Voltage and Frequency Scaling (DVFS) capabilities, including big.LITTLE Arm architectures and platforms with GPU or FPGA hardware accelerators with Dynamic Partial Reconfiguration capabilities. Tasks can be deployed on CPUs using partitioned EDF-based scheduling. Additionally, some of the tasks may have an alternate implementation available for one of the accelerators on the target platform, which are assumed to serve requests in non-preemptive FIFO order. The system can be optimized by minimizing power consumption, respecting precise timing constraints, maximizing the applications’ slack, respecting given power consumption constraints, or even a combination of these, in a multi-objective formulation. We propose an off-line optimization of the mentioned problem based on mixed-integer quadratic constraint programming (MIQCP). The optimization provides the DVFS configuration of all the CPUs (or accelerators) capable of frequency switching and the placement to be followed by each task in the DAGs, including the software-vs.-hardware implementation choice for tasks that can be hardware accelerated. For relatively big problems, we developed heuristic solvers capable of providing suboptimal solutions in a significantly reduced time compared to the MIQCP strategy, thus widening the applicability of the proposed framework. We validate the approach by running a set of randomly generated DAGs on Linux under SCHED_DEADLINE, deployed onto two real boards, one with Arm big.LITTLE architecture, the other with FPGA acceleration, verifying that the experimental runs meet the theoretical expectations in terms of timing and power optimization goals.

Turning on hotspots: supracolloidal SERS probes made brilliant by an external activation mechanism.

We achieved external activation of local hot-spot sites in supracolloidal assembly structures. The concept was demonstrated by boosting surface-enhanced Raman scattering (SERS) efficiency by one order of magnitude through a heating-induced process. Our approach involves assembling gold nanoparticles with distinct dimensions, i.e. 16 and 80 nm, into well-defined planet-satellite-type arrangement structures using thermoresponsive (poly(N-isopropylacrylamide)) star polymer linkers. Insights into the assembly process were obtained by calculations within the Derjaguin-Landau-Verwey-Overbeek (DLVO) theory framework. We observe one order of magnitude increase in SERS enhancement by a heating-induced volume-phase transition. This magnification aligns with simulations run using the finite-difference time-domain (FDTD) method. The implications of this adaptive supracolloidal concept are twofold: Firstly, our approach bypasses limitations of existing systems that are associated with the limited accessibility of electromagnetic hot-spot sites in strongly coupled, static assemblies of plasmonic nanoparticles, by providing the capability of dynamic hot-spot re-configuration. Second, these externally activated probes offer promising opportunities for the development of messenger materials and associated sensing strategies.

A conceptual architecture for integrating software defined network and network virtualization with internet of things

<span lang="EN-US">Software defined network (SDN) and network function virtualization (NFV) are new paradigms and technologies of the network which support the best experience of providing functions and services, managing network traffic, and a new way of control. They support virtualization and separating data from control in network devices, as well as provide services in a software-based environment. Internet of things (IoT) is a heterogeneous network with a massive number of connected devices and objects. IoT should be integrated with such technologies for the purpose of providing the capabilities of dynamic reconfiguration with a high level of integration. This paper proposes a conceptual architecture for integrating software defined network (SDN) and NFV with IoT. The proposed work combines the three technologies together in one architecture. It also presents the previous works in this area and takes a look at the theoretical background of those technologies in order to give a complete view of proposed work.</span>

Reconfigurable Network-on-Chip based Convolutional Neural Network Accelerator

Convolutional Neural Networks (CNNs) have a wide range of applications due to their superior performance in image and pattern classification. However, the performance of CNNs comes at the price of high computational load and memory bandwidth usage. Hardware acceleration has become the primary way to tackle this ever-increasing complexity of CNNs. Most of the recent accelerators arrange processing units (PEs) as a many-core accelerator architecture, with the inter-PE connections tailored to the specific dataflow of the CNN layers. The performance of such accelerators is maximized if the input feature map and filter size/dimension matches that of the underlying accelerator. However, current fixed-size accelerator structures lead to sever resource underutilization because the same structure is used to compute CNN layers of varying dimensions. In this paper, we tackle this problem by presenting RC-CNN, a reconfigurable accelerator architecture for CNNs that can adapt the structure of accelerator to the size and dataflow pattern of the running CNN layer. RC-CNN relies on a reconfigurable on-chip interconnection fabric that can organize a sub-set of accelerator’s PEs as a PE set with the same size/dimension of the target CNN layer and customize the inter-PE connections for the layer’s dataflow pattern. Since the area/energy overhead does not justify using a full-fledged packet-switched network in accelerators with fine-grained PEs, we use a reconfigurable network with very simple switches in order to efficiently implement the dynamic reconfiguration capability for many-core fine-grained CNN accelerators. Experimental results show that, based on the CNN size and accelerator structure, RC-CNN yields 37% higher PE utilization over a baseline design, on average. It also improves the PE utilization of the state-of-the-art CNN accelerators we selected for comparison purpose by 18%, on average. The results show that these improvements translate to 9%–41% increase in the accelerator’s throughput. Further, RC-CNN reduces the network latency and energy consumption by 28% and 22%, respectively, compared to the state-of-the-art utilization-aware methods that employ packet-switched networks-on-chip.

A Maude Implementation of Rewritable Petri Nets: a Feasible Model for Dynamically Reconfigurable Systems

Petri Nets (PN) are a central, theoretically sound model for concurrent or distributed systems but, at least in their classical definition, not expressive enough to represent dynamic reconfiguration capabilities. On the other side, Rewriting Logic has proved to be a natural semantic framework for several formal models of concurrent/distributed systems. We propose a compact, efficient Maude formalization of dynamically reconfigurable PT nets (with inhibitor arcs), using as a running example the specification of a simple, fault-tolerant manufacturing system. We discuss the advantages of such a combined approach, as well as some concerns that it raises.

High-Performance Data Compression-Based Design for Dynamic IoT Security Systems

IoT technology is evolving at a quick pace and is becoming an important part of everyday life. Consequently, IoT systems hold large amounts of data related to the user of the system that is vulnerable to security breaches. Thus, data collected by IoT systems need to be secured efficiently without affecting the IoT systems’ performance and without compromising security as well. In this paper, a high-performance dynamic security system is introduced. The system makes use of the ZedBoard’s dynamic partial reconfiguration capability to shift between three distinct cipher algorithms: AEGIS, ASCON, and DEOXYS-II. The switching between the three algorithms is performed using two different techniques: the algorithm hopping technique or the power adaptive technique. The choice of which technique to be used is dependent on whether the system needs to be focused on performance or power saving. The ciphers used are the CAESAR competition finalists that achieved the greatest results in each of the three competition categories, where each cipher algorithm has its own set of significant characteristics. The proposed design seeks to reduce the FPGA reconfiguration time by the application of LZ4 (Lempel-Ziv4) compression and decompression techniques on the ciphers’ bitstream files. The reconfiguration time decreased by a minimum of 38% in comparison to the state-of-the-art design, while the resource utilization increased by approximately 2%.

Are fiscal policy incentives effective in stimulating firms' eco‐product innovation? The moderating role of dynamic capabilities

AbstractThis study investigates the effectiveness of fiscal policy incentives—in particular, direct subsidies and tax credits—in stimulating eco‐product innovation among Chinese manufacturing firms. We also examine the moderating effects of dynamic capabilities. The empirical results, which are based on survey data from 265 firms in China, demonstrate that both direct subsidies and tax credits are conducive to firms' eco‐product innovation. In addition, we find that when firms' dynamic integration capabilities are strong, the facilitating effects of direct subsidies and tax credits on eco‐product innovation are likewise strong. Moreover, dynamic reconfiguration capabilities positively moderate the relationship between tax credits and eco‐product innovation. By identifying moderators that influence the effect of fiscal incentives on eco‐product innovation in heterogeneous firms, this study contributes to fiscal policy debates and realizing sustainable development.

An execution environment as a service for adaptive long-running workflows

PurposeThis paper aims to present Long4Cloud (long-running workflows execution environment for cloud), a distributed and adaptive LRW execution environment delivered “as a service” solution.Design/methodology/approachLRWs last for hours, days or even months and their duration open the possibility of changes in business rules, service interruptions or even alterations of formal regulations of the business before the workflow completion. These events can lead to problems such as loss of intermediary results or exhaustion of computational resources used to manage the workflow execution. Existing solutions face those problems by merely allowing the replacement (at runtime) of services associated with activities of the LRW.FindingsLONG4Cloud extends the previous works in two main aspects, namely, the inclusion of dynamic reconfiguration capabilities and the adoption of an “as a service” delivery mode. The reconfiguration mechanism uses quiescence principles, data and state management and provides multiple adaptive strategies. Long4Cloud also adopts a scenario-based analysis to decide the adaptation to be performed. Events such as changes in business rules or service failures trigger reconfigurations supported by the environment. These features have been put together in a solution delivered “as a service” that takes advantage of cloud elasticity and allows to better allocate cloud resources to fit into the demands of LRWs.Originality/valueThe original contribution of Long4Cloud is to incorporate adaptive capabilities into the LRW execution environment as an effective way to handle the specificities of this kind of workflow. Experiments using current data of a Brazilian health insurance company were carried out to evaluate Long4Cloud and show performance gains in the execution of LRWs submitted to the proposed environment.

Latency-Sensitive Edge/Cloud Serverless Dynamic Deployment Over Telemetry-Based Packet-Optical Network

The serverless technology, introduced for data center operation, represents an attractive technology for latency-sensitive applications operated at the edge, enabling a resource-aware deployment accounting for limited edge computing resources or end-to-end network congestion to the cloud. This paper presents and validates a framework for automated deployment and dynamic reconfiguration of serverless functions at either the edge or cloud. The framework relies on extensive telemetry data retrieved from both the computing and packet-optical network infrastructure and operates on diverse Amazon Web Services technologies, including Greengrass on the edge. Experimental demonstration with a latency-sensitive serverless application is then provided, showing fast dynamic reconfiguration capabilities, e.g., enabling even zero outage time under certain conditions.

Impact of Dynamic Capabilities on Global Mind-set: The Case of ICT Start-ups in Sri Lanka

The purpose of this study is to explore how firm-level dynamic capabilities influence the level of firms’ global mindset in information and communication technology (ICT) startups in Sri Lanka. Based on the literature on dynamic capabilities and global mindset, the impact of dynamic capabilities on global mindset is tested empirically on a sample of 295 Sri Lankan ICT start-up firms using structural equation modeling (SEM) analysis technique to find whether if there is any difference of the impact from sensing dynamic capabilities, seizing capabilities and reconfiguration capabilities on the global mindset. The results show a positive significant impact of the sensing, seizing and reconfiguration capabilities on the global mindset in ICT startups in Sri Lanka. However, among three different but theoretically interrelated capabilities, seizing and reconfiguration dynamic capabilities have shown the strongest impact on the global mindset. This study contributes to the emerging literature of global mindset in the international business and to strategic management literature by understanding the global mindset through the lenses of dynamic capabilities as organizational level contingencies.

RETRACTED: Design of embedded digital image processing system based on ZYNQ

Zynq- real time edge detection system based on execution of the image reconstructed from the sequence. Although the object edge detection is an essential tool in computer vision, edge detection results in the negative image frame noise significantly. Further, due to the high computational complexity of an image filtering operation, implemented in the hardware configuration of the re-configurable hardware it is necessary. In this portion, the proposed dynamic Zynq embedded system reconfiguration capability to detect according to the input image frame to the noise level of the different density filters perform during runtime bit stream re Configuration.The results show that the accuracy of edge detection is highly evaluated. We analyze various noise density levels, and the results show that the edge detection results of the proposed filter bit stream are more accurate, while effectively providing computing capacity to support the real-time processing of the image frame. In the configuration time, CPU usage, and hardware resource utilization performance test results were compared.

Dynamic Partial Reconfiguration Profitability for Real-Time Systems

Modern field-programmable gate arrays offer dynamic partial reconfiguration (DPR) capabilities, a characteristic that opens new scheduling opportunities for real-time applications running on heterogeneous platforms. To evaluate when it is really useful to exploit a DPR, in this letter, we present the characterization of its reconfiguration cost in terms of time and a definition of the “DPR Profitability” concept targeting real-time systems. To obtain such results, the components involved in a DPR process have been identified and an innovative approach to calculate the DPR time and its worst-case bound is provided. We validate our approach on a real DPR-compliant platform, showing that our proposal is general enough to be applied to modern DPR-compliant platforms.

Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices

In the era of IoT, embedded systems are becoming the cornerstone of many IoT related applications, such as smart cars and wearable devices. However, embedded devices have numerous constraints and requirements, including stringent area and power, reduced cost and time-to-market, and increased speedup. Furthermore, these applications are becoming increasingly compute/data-intensive requiring more processing power. Also, especially for IoT related applications, security is another major issue in resource-constrained embedded devices. Although cryptographic algorithms are widely used to ensure the security of these applications, commonly used ones, such as AES, are unsuitable for highly constrained embedded devices, due to their sheer complexity. Hence, several lightweight cryptographic algorithms were proposed in the literature that might be better suited for embedded devices. From these, SPECK and SIMON, introduced by NSA, are the two most popular ones. Another important challenge is how to incorporate the cryptographic algorithms in to embedded devices, efficiently and effectively, without compromising the integrity of the compute/data-intensive applications running on these small-footprint devices. Our previous analysis demonstrated that FPGAs are currently the best avenue to support compute/data-intensive applications running on resource-constrained embedded devices, due to FPGA’s many attractive traits, including, post-fabrication reprogrammability, dynamic and partial reconfiguration capabilities, and reduced time-to-market. Also, FPGAs can be utilized to provide several advantages/features required for the embedded device’s security, such as cryptographic algorithm agility, algorithm upload, algorithm modification, and resource efficiency. In this research work, we introduce novel, unique, and efficient dynamic and partial reconfigurable hardware architectures for the most popular SPECK and SIMON algorithms on embedded devices, considering the constraints associated with these devices and the requirements of the applications running on embedded devices. We also introduce unique system-level architectures for our proposed designs. To the best of our knowledge, no similar work exists in the literature that provides dynamic and partial reconfigurable hardware for SPECK and SIMON, and also provides system-level architecture. Our dynamic and partial reconfigurable hardware designs achieve 28% space saving compared to its static reconfigurable hardware, and 59 times speedup compared to its software counterpart.

A Dynamically Reconfigurable Dual-Waveform Baseband Modulator for Flexible Wireless Communications

In future wireless communication systems, several radio access technologies will coexist and interwork to provide a great variety of services with different requirements. Thus, the design of flexible and reconfigurable hardware is a relevant topic in wireless communications. The combination of high performance, programmability and flexibility makes Field-programmable gate array a convenient platform to design such systems, especially for base stations. This paper describes a dynamically reconfigurable baseband modulator for Orthogonal Frequency Division Multiplexing and Filter-bank Multicarrier modulation waveforms implemented on a Virtex-7 board. The design features Dynamic Partial Reconfiguration (DPR) capabilities to adapt its mode of operation at run-time and is compared with a functionally equivalent static multi-mode design regarding processing throughput, resource utilization, functional density and power consumption. The DPR-based design implementation reserves about half the resources used by static multi-mode counterpart. Consequently, the baseband processing dynamic power consumption observed in the DPR-based design is between 26 mW to 90 mW lower than in the static multi-mode design, representing a dynamic power reduction between 13% to 52%. The worst-case DPR latency measured was 1.051 ms, while the DPR energy overhead is below 1.5 mJ. Considering latency requirements for modern wireless standards and power consumption constraints for commercial base stations, the DPR application is shown to be valuable in multi-standard and multi-mode systems, as well as in scenarios such as multiple-input and multiple-output or dynamic spectrum aggregation.

Modular control with carrier auto‐interleaving and capacitor‐voltage balancing for MMCs

In this study, a new control method dedicated to modular multilevel converters (MMCs) is proposed. The approach is based on local communication between the individual controls of each submodule (SM). The local values of the capacitor voltages and the carrier-phase angles are shared between immediate neighbours achieving balancing of their capacitor voltages, and an automatic interleaving of the pulse-width modulation (PWM) signals. Using an inter-cell communication strategy, the number of required data exchanges with a centralised controller is greatly reduced. This method works for any number of SMs present in the converter and provides an integrated dynamic reconfiguration capability to enable or disable SMs during operation, without any additional consideration for the control-algorithm's implementation. Such a capability is not offered by classical MMC control methods using either PWM or nearest-level control strategies. Higher stability, robustness and larger bandwidth of the proposed method are first demonstrated through real-time simulation. The auto-interleaving of the PWM carriers and the capacitor-voltage balancing, provide fast responses and adequate accuracy. Experimental results are provided using a 600 V/3 kW/18 cells single-phase MMC demonstrator confirming the simulation results, and the advantages of this SM control strategy.

A Multi-Clustering Approach to Scale Distributed Tenant Networks for Mobile Edge Computing

Fifth generation (5G) mobile networks will lead to a deep integration between networks and applications. Through novel paradigms like network functions virtualization and edge computing, the new classes of heterogeneous application services will be enabled to run close to the mobile end-user devices with zero-perceived latency and fully-cognitive dynamic reconfiguration capabilities. Such “vertical” applications exhibit diverse performance/scalability requirements, and will rely on highly distributed, extremely virtualized, multi-tenant, and software-defined infrastructures. In such a context, handling the required operations in a scalable and dynamic fashion will be of paramount importance. A specific aspect, addressed by software-defined networking (SDN), regards the provision of suitable communication channels, once resource allocation mechanisms have performed the most efficient deployment of virtual network function instances, and VNF chaining needs to be implemented to enable network services. In this respect, this paper introduces the multi-cluster overlay (MCO) network paradigm: a tunnel-less SDN scheme for scalable realization of virtual tenant networks across the 5G distributed infrastructure, able to support (bulk) migrations of software instances among geo-distributed computing resources in a seamless and effective fashion. The numerical simulation and experimental results show that the MCO achieves up to over one order of magnitude smaller number of forwarding rules than the other state-of-the-art SDN mechanisms, while also assuring high performance during reconfiguration operations.

Approach to MAI cancellation for micro-satellite clusters

With the development of micro-satellite technology, traditional monolithic satellites can be replaced by micro-satellite clusters to achieve high flexibility and dynamic reconfiguration capability. For satellite clusters based on the frequency division-code division multiple access (FD-CDMA) communication system, the inter-satellite ranging precision is usually constrained due to the influence of multi-address interference (MAI). The multi-user detection (MUD) is a solution to MAI, which can be divided into two categories: the linear detector (LD) and the non-linear detector (NLD). The general idea of the LD is aiming to make a better decision during the symbol decision process by using the information of all channels. However, it is not beneficial for the signal phase tracking precision. Instead, the principle of the NLD is to rebuild the interference signal and cancel it from the original one, which can improve the ranging performance at the expense of considerable delays. In order to enable simultaneous ranging and communication and reduce multi-node ranging performance degradation, this paper proposes an NLD scheme based on a delay locked loop (DLL), which simplifies the receiver structure and introduces no delay in the decision process. This scheme utilizes the information obtained from the interference channel to reconstruct the interference signal and then cancels it from the original delayed signal. Therefore, the DLL input signal-to-interference ratio (SIR) of the desired channel can be significantly improved. The experimental results show that with the proposed scheme, the standard deviation of the tracking steady error is decreased from 5.59 cm to 3.97 cm for SIR = 5 dB, and 13.53 cm to 5.77 cm for SIR = -5 dB, respectively.

FPGA-Centric Design Process for Avionic Simulation and Test

Real-time computing systems are increasingly used in aerospace and avionic industries. In the face of power challenge, performance requirements and demands for higher flexibility, hardware designers are directed toward reconfigurable computing using field programmable gate arrays (FPGAs) that offer high computation rates per watt and adaptability to the application constraints. However, considering reconfigurable computing in the avionic design process leads to several challenges for system developers. Indeed, such technology should be validated along the verification & validation cycle starting with simulation tools, passing through the test benches and finishing with the integration phase. For each step, the FPGA can play an essential role to achieve better performances, more adaptive systems, and cost-effective solutions. In this paper, we present a seamless FPGA-centric design process for avionic equipments. Along this process, we redefine the role of the FPGA circuits to cover the simulation, the test, and the integration steps. First, reconfigurable logics are used in the frame of heterogeneous CPU/FPGA computing in order to obtain high speed-up for real-time avionic simulation. The proposed environment supports dynamic execution model enabling reconfiguration during runtime to avoid the timing constraint violation. Second, the FPGA is used as a key solution to offer versatile test benches and to converge toward unified test and simulation tools. We have designed several commercial input output intellectual property systems with dynamic runtime reconfiguration capabilities, in order to mitigate component obsolescence and to provide increased flexibility and decreased design time. Third, at the integration phase, we use the conventional tools to make profit from reconfigurable technology in embedded avionic applications in order to deliver high computation rates and to adapt their functioning mode to provide reliability, fault tolerance, deterministic timing guarantees, and energy efficiency.

Remote dynamic partial reconfiguration: A threat to Internet-of-Things and embedded security applications

The advent of the Internet of Things has motivated the use of Field Programmable Gate Array (FPGA) devices with Dynamic Partial Reconfiguration (DPR) capabilities for dynamic non-invasive modifications to circuits implemented on the FPGA. In particular, the ability to perform DPR over the network is essential in the context of a growing number of Internet of Things (IoT)-based and embedded security applications. However, the use of remote DPR brings with it a number of security threats that could lead to potentially catastrophic consequences in practical scenarios. In this paper, we demonstrate four examples where the remote DPR capability of the FPGA may be exploited by an adversary to launch Hardware Trojan Horse (HTH) attacks on commonly used security applications. We substantiate the threat by demonstrating remotely-launched attacks on Xilinx FPGA-based hardware implementations of a cryptographic algorithm, a true random number generator, and two processor based security applications - namely, a software implementation of a cryptographic algorithm and a cash dispensing scheme. The attacks are launched by on-the-fly transfer of malicious FPGA configuration bitstreams over an Ethernet connection to perform DPR and leak sensitive information. Finally, we comment on plausible countermeasures to prevent such attacks.

Energy efficient processing of motion estimation for embedded multimedia systems

Visual sensor networks require low power compression techniques of large amount of video data in each camera node due to the energy-constrained and bandwidth-limited environments. In this paper, energy-efficient architecture for Variable Block Size Motion Estimation is proposed to fully utilize dynamic partial reconfiguration capability of programmable hardware fabric in distributed embedded vision processing nodes. Partial reconfiguration of FPGA is exploited to support run-time reconfiguration of the proposed modular hardware architecture for motion estimation. According to the required search range, hardware reconfiguration is performed adaptively to reduce the hardware resources and power consumption. A reconfigurable ME ranging from simple 1-D to a complex 2-D Sum of Absolute Differences (SAD) array to perform full search block matching is selected in order to support different search window size. The implemented scalable SAD array can provide different resolutions and frame rates for real time applications with multiple reconfigurable regions.