Dynamic Random Access Memory Cell Research Articles

Atomic Layer Growth of Rutile TiO2 Films with Ultrahigh Dielectric Constants via Crystal Orientation Engineering.

In general, the electronic and optical properties of oxide films can significantly benefit from highly textured crystallinity. However, oxide films grown by atomic layer deposition (ALD), a powerful technique for the synthesis of high-quality, nanoscale thin films, usually exhibit amorphous or randomly oriented polycrystalline phases. Here, we demonstrate the growth of highly textured rutile phase ALD TiO2 films through rational substrate design. Both a- and c-axis preferentially oriented TiO2 films are obtained by varying the lattice parameters of the initial ALD growth surface. Under optimized conditions, we find that it is possible to deposit high-quality, c-axis preferentially aligned TiO2 films with a bulk dielectric constant approaching 185, rivaling the single crystal limit. These films display a remarkably high dielectric constant of 117 despite thin thickness of 5.2 nm. Moreover, the addition of a single doping sequence of Al2O3 successfully suppresses leakage currents to levels compatible with modern dynamic random access memory cells, all the while maintaining the high bulk dielectric constant of 137. These results clearly highlight the prospect of utilizing crystal orientation engineering in ALD thin films for emerging semiconductor devices.

Capacitorless Two‐Transistor Dynamic Random‐Access Memory Cells Comprising Amorphous Indium–Tin–Gallium–Zinc Oxide Thin‐Film Transistors for the Multiply–Accumulate Operation

AbstractCapacitorless two‐transistor (2T0C) dynamic random‐access memory (DRAM) cells comprising oxide thin‐film transistors (TFTs) show potential as low‐power and high‐density DRAM cells; however, the multiply–accumulate (MAC) operation using these cells is not yet realized. In this study, 2T0C DRAM cells comprising amorphous indium–tin–gallium–zinc oxide TFTs are fabricated for MAC operations. In a 2T0C DRAM cell, one transistor acts as a write transistor and the other as a read transistor, whose gate capacitance corresponds to the data storage capacitance. The cells have a long retention time of 1000 s, which is 104 times longer than that of conventional DRAM cells, owing to the extremely low leakage current of the TFTs (1.11 × 10−18 A µm−1). These cells satisfy the original condition for synaptic devices, in which a proportional relationship exists between the input and output. The MAC operation is performed using two cells. This study demonstrates the usefulness of oxide TFTs in artificial neural networks.

A novel solution to improve static and dynamic retention characteristics by enhancing hydrogen passivation with in situ LD-TEOS/TEOS dual layer

We proposed a novel solution to improve both static and dynamic retention characteristics by additional etching of the thickness of Silicon Boron Nitride (SIBN), stopper when oxide etch, with in situ dual low deposition-tetraethyl orthosilicate (LD-TEOS)/TEOS Dual layer. As Dynamic Random Access Memory Cells shrink, it is difficult to obtain reliable retention properties, so it becomes more significant to reduce the number of interface trap (Nit) by hydrogen passivation. In this work, Nit decreased by reducing the thickness of SIBN, which has low hydrogen diffusion coefficients, improve the static and dynamic retention characteristics simultaneously through enhancing hydrogen passivation with in situ LD-TEOS Dual layer compensating for Metal contact to Other Bit line pad distance margin risk.

Transport Properties with Multiple Functions of Fe@C60-GNR Single Molecule.

Encouraged by the successful fabrication of C60-GNR (GNR=graphene nanoribbon) single-molecule transistors in experiments, four Fe-containing derived double-layered devices of Fe@C60-GNR are designed by employing different electrode linkages and their transport properties are investigated by using density functional theory (DFT) and nonequilibrium Green's function (NEGF) methods. Regardless of electrode connection, all these devices give rise to a smaller negative differential resistance (NDR) peak at V=0.2 and a higher peak at 1.2 V, suggesting their stable maneuverability as molecular devices and good candidates for developing on(off)-off(on)-on(off) current switches. The macroscopic NDR performance depends on the delocalization character and the crossing mechanism of the frontier orbitals. The peak-to-valley current ratios (Rmax) range from 454 to 2737, determined by the electrode linkage. Such a large Rmax-value is necessary for developing dynamic random-access memory (DRAM) cells. Encapsulating the Fe atom inside C60 not only improves the conductivity but also introduces the spin-polarized transport property. The spin-filtering efficiency (SFE) of almost all devices oscillates up and down in response to the bias voltage, indicating the possibility of designing on(off)-off(on)-on(off) spin switches and up-down spin switches. All these fascinating properties provide an important clue for designing similar molecular devices with multiple functions by trapping magnetic transition metal atoms inside fullerenes.

Oxide and 2D TMD semiconductors for 3D DRAM cell transistors.

As the downscaling of conventional dynamic random-access memory (DRAM) has reached its limits, 3D DRAM has been proposed as a next-generation DRAM cell architecture. However, incorporating silicon into 3D DRAM technology faces various challenges in securing cost-effective high cell transistor performance. Therefore, many researchers are exploring the application of next-generation semiconductor materials, such as transition oxide semiconductors (OSs) and metal dichalcogenides (TMDs), to address these challenges and to realize 3D DRAM. This study provides an overview of the proposed structures for 3D DRAM, compares the characteristics of OSs and TMDs, and discusses the feasibility of employing the OSs and TMDs as the channel material for 3D DRAM. Furthermore, we review recent progress in 3D DRAM using the OSs, discussing their potential to overcome challenges in silicon-based approaches.

Rapid prototyping of etch test structures for hard mask development using electron beam lithography

Semiconductor manufacturing depends on the development of new processes, advanced patterning, and novel materials to create smaller and higher performing devices to follow the industry roadmaps for applications for computing and systems (such as smartphones and servers). For dynamic random access memory (DRAM) applications, the biggest efforts are engaged in scaling and shrinking of the nodes, and these then affect the area density, performance, and cost of the DRAM cells. However, while we are reaching a slowdown in dimension-scaling, more innovation is needed to sustain the high aspect ratios required in the capacitor’s architecture—whether it is moving toward 3D architectures or developing new materials to sustain the challenge of scaling. To accelerate the learning, it is essential to screen novel hard mask (HM) materials in a rapid fashion to speed their development. While EUV (extreme ultraviolet—a wavelength of 13.5 nm) lithography requires 300 mm wafers, electron beam lithography (EBL) generates nanoscale patterns in a maskless manner on smaller substrates (from 300 mm wafers to 10 mm2 coupons) mimicking sub-50 nm EUV features. The primary goal of this work is to create a path for rapid screening of HM materials that are still under early phase development and which are prepared in small chamber tools (coupon chambers) and, therefore, not ready for 300 mm process integration. While the features investigated of 44 nm half pitch seem extremely reasonable for e-beam, the requirements and the approaches used to address the needed patterned area, resolution, speed, and uniformity exceed the standard conditions previously reported in the literature. Each aspect will be evaluated in the context of a “dots on the fly,” or DOTF, patterning technique.

Investigation on Recrystallization Channel for Vertical C-Shaped-Channel Nanosheet FETs by Laser Annealing.

Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F2 DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V.

True Nonvolatile High-Speed DRAM Cells Using Tailored Ultrathin IGZO.

Severe power consumption in the continuous scaling of Silicon-based dynamic random access memory (DRAM) technology quests for a transistor technology with a much lower off-state leakage current. Wide bandgap amorphous oxide semiconductors, especially indium-gallium-zinc-oxide (IGZO)exhibit many orders of magnitude lower off-state leakage. However, they are typically heavily n-doped and require negative gate voltage to turn off, which prevents them from true nonvolatile operation. The efforts on doping density reduction typically result in mobility degradation and high Schottky barriers at contacts, causing severe degradation of on-current and operation speed of the DRAM cells. Here, high-speed true nonvolatile DRAM cells are successfully demonstrated by deep suppression of doping density in the IGZO channel using in situ oxygen ion beam treatment and ohmic contact engineering by inserting a thin In-rich indium-tin-oxide (ITO) at contact regions. A record high on-current of 40µA µm-1 at a large positive threshold voltage of 1.78V enables the first true nonvolatile DRAM with the fastest write speed of 10ns and data retention up to 25 h under power interruption, five orders of magnitude higher than the previously projected values.

Fowler–Nordheim Stress-Induced Degradation of Buried-Channel-Array Transistors in DRAM Cell for Cryogenic Memory Applications

The degradation of the fin-type buried-channel-array transistor (BCAT) in dynamic random access memory (DRAM) cell is investigated under Fowler–Nordheim stress at various temperatures, including 77 K. While the increase in the OFF current is dominated by the Shockley–Read–Hall junction leakage, the threshold voltage shift ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V}_{T}$ </tex-math></inline-formula> ) comprises a positive component due to the interface trap generation and a negative component resulting from the electric field concentration-induced charge trapping into the gate insulator bulk, with respective activation energies of 0.22 and 0.13 eV. Furthermore, based on the consistency between the experimentally decomposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V}_{T}$ </tex-math></inline-formula> components and the simulated ones, it is found that the anode hole injection dominates the degradations of the wordline-active operation and refresh time in cryogenic DRAM.

Design optimization of heterojunction 1T DRAM cell with SiGe body/drain for high performance

In this study, a heterojunction one-transistor (1T) dynamic random-access memory (DRAM) with SiGe body/drain has been proposed and its electrical characteristics have been investigated by technology computer-aided design simulation. The results reveal that the homojunction between body and drain with a narrow band gap material enhances not only retention characteristic but also write and erase efficiencies compared to those of the structure in which SiGe is only adopted at the body region. Consequently, the sensing margin of the optimized structure is ∼15.9 and ∼2.4 times larger than that of the Si and Si0.7Ge0.3-body 1T DRAM cells, respectively, with a retention time longer than 99 ms.

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 μA/μm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future.

Effect of La doping on dielectric constant and tetragonality of ZrO2 thin films deposited by atomic layer deposition

The electrical properties of La-doped ZrO2 thin films were studied for an application to cell capacitors in dynamic random-access memory. La-doped ZrO2 thin films were deposited by changing the ratio of ZrO2:La2O3 cycles using atomic layer deposition. Grazing-incidence X-ray diffraction analysis showed that the La-doped ZrO2 thin films had a tetragonal structure. The tetragonality (c/a) of La-doped ZrO2 thin films increased from 1.41 in undoped ZrO2 to 1.43 in La-doped ZrO2 with a 7.5% La content. X-ray photoelectron spectroscopy showed that the concentration of oxygen vacancies in ZrO2 thin films increased with increasing La concentration. The dielectric constant of La-doped ZrO2 was increased by 15% from 37 in undoped ZrO2 to 43 at a La doping concentration of 7.5%, and the leakage current was also improved. Therefore, La-doped ZrO2 thin films are expected to be an excellent candidate material for dynamic random-access memory cell capacitors owing to their high dielectric constant and low leakage current.

Design of novel 3T ternary DRAM with single word-line using CNTFET

Ternary logic system is the most promising and pursued alternative to the prevailing binary logic systems due to the energy efficiency of circuits following reduced circuit complexity and chip area. In this paper, we have proposed a ternary 3-Transistor Dynamic Random-Access Memory (3 T-DRAM) cell using a single word-line for both read and write operations. For simulation of the circuit, we have used Carbon-Nano-Tube Field Effect Transistor (CNTFET). Here, we have analyzed the operation of the circuit considering different process variations and showed the results for write delay, read sensing time, and consumed current. Along with the basic DRAM design, we have proposed a ternary sense circuitry for the proper read operation of the proposed DRAM. The simulation and analysis are executed using the H-SPICE tool with Stanford University CNTFET model.

DRAM-based Physically Unclonable Functions and the Need for Proper Evaluation

Dynamic Random-Access Memory (DRAM)-based Physically Unclonable Functions (PUFs) are a part of the Physical Layer Security (PhySec) domain. Those electrical PUFs are memory based and exhibit a high availability, Shannon Entropy, low energy consumption and high amount of Challenge Response Pairs (CRPs). Because of those properties, the DRAM PUF is a promising approach for security applications in the Industrial Internet of Things (IIoT) context as well as securing the Sixth-Generation (6G) Wireless Systems and edge computing.&#x0D; DRAM, with its most common one-Transistor one-Capacitor (1T1C) architecture, and as a volatile memory is embedded in almost every modern computing unit. Regarding the PUF security applications, four main types of applications are currently distinguished in the scientific community: Retention Error, Row Hammer, Startup and Latency PUFs. Thereby these differ in their procedure in how responses are generated as well as by the physical mechanisms. Each of them with varying properties in terms of availability, reliability, uniqueness and uniformity.&#x0D; To examine this, and to obtain comparable results, this work proposes to compare the four different DRAM-PUF types i) with the same metrics of evaluation and ii) implemented on the same DRAM cells. This represents both the difference with regard to the work done in the literature and the added value of this work presented. As far as known, there is no work to date that performs the intended evaluations using the same evaluation platform under the identical conditions. However, this is required for comparable results.&#x0D; This consistent comparison is ensured by a self-developed and implemented evaluation platform, which is accordingly equipped with a significant number of DRAMs. By an appropriate high volume of measurements, a corresponding resolution will be given. Monitoring the environmental conditions prevents from wrong interpretations caused by environmental influences but also provides useful context information. Furthermore, a detailed technical and physical background will be described. The results of this approach will assist by the consideration of which DRAM-PUF is appropriate in which (environmental) conditions and thereby provide a guideline for practitioners.

DRAM Retention Behavior with Accelerated Aging in Commercial Chips

The cells in dynamic random access memory (DRAM) degrade over time as a result of aging, leading to poor performance and potential security vulnerabilities. With a globalized horizontal supply chain, aged counterfeit DRAMs could end up on the market, posing a significant threat if employed in critical infrastructure. In this work, we look at the retention behavior of commercial DRAM chips from real-time silicon measurements and investigate how the reliability of DRAM cells degrade with accelerated aging. We analyze the retention-based errors at three different aging points to observe the design-induced variations, analyze the pattern dependency, and explore the impacts of accelerated aging for multiple DRAM vendors. We also investigate the DRAM chips’ statistical distribution to attribute the vital wear-out effects present in DRAM. We see a continuous increase in retention error as DRAM chips age and therefore infer that the aged retention signatures can be used to differentiate recycled DRAM chips in the supply chain. We also discuss the roles of device signature in DRAM aging and aging-related security implication on DRAM row-hammer error.

Predominance of Carrier Diffusion in Determination of Data Retention in One-transistor Dynamic Random-access Memory

One-transistor (1T) dynamic random-access memory (DRAM) has been widely studied for higher array density and obtaining three-dimensional (3-D) array stack viability by truncating the capacitor. However, its rather short retention time has been pointed out as a weak point compared with that of conventional one-transistor one-capacitor (1T1C) DRAM cell. The three dominating factors in determining the data retention in 1T DRAM can be sorted as diffusion, drift, and recombination, by which the programmed carriers are annihilated. In this study, out of those three major factors, the most predominant one is sought in the analytical and mathematical manners. It has been found that carrier diffusion has the key to modulation of the retention time of 1T DRAM and the other two factors are insignificantly small compared with diffusion. Error functions depending on both position and time were adopted to describe the distribution of programmed holes experiencing diffusion and drift in conjunction with solving the continuity equation. It has been concluded that carrier diffusion is the most dominant factor in determining the data retention in 1T DRAM, which suggests that proper ways of decelerating the carrier diffusion out of the channel be sought in optimally designing 1T DRAM cells.

Effect of Work-function Variation on Transfer Characteristics and Memory Performances for Gate-all-around JLFET based Capacitorless DRAM

In this study, we present variations in transfer characteristics and memory performances caused by work-function variation (WFV) in the metal gate of a one-transistor dynamic random-access memory cell based on a gate-all-around junctionless field-effect transistor (GAA-JLFET). To investigate the influence of WFV, we simulated 200 samples of GAA-JLFETs. The samples had different transfer characteristics depending on the metal grain granularity. In addition, we calculated and analyzed the mean and standard deviations for the transfer characteristics. Further, the memory performances were analyzed using two extreme cases with the highest and lowest threshold voltage (V<SUB>th</SUB>) as examples. When WFV was not considered, the current ratio was 108, and retention time was more than 10 ms. Meanwhile, when WFV was considered, the current ratio was 10² and 10⁴, and the retention time was reduced to 0.051 ms and 2.2 ms, respectively. These results showed that WFV affected not only the transfer characteristics in GAA-JLFET but also the memory performances; it could adversely affect the reliability of the memory device.

OBET: On-the-Fly Byte-Level Error Tracking for Correcting and Detecting Faults in Unreliable DRAM Systems.

With technology scaling, maintaining the reliability of dynamic random-access memory (DRAM) has become more challenging. Therefore, on-die error correction codes have been introduced to accommodate reliability issues in DDR5. However, the current solution still suffers from high overhead when a large DRAM capacity is used to deliver high performance. We present a DRAM chip architecture that can track faults at byte-level DRAM cell errors to address this problem. DRAM faults are classified as temporary or permanent in our proposed architecture, with no additional pins and with minor DRAM chip modifications. Hence, we achieve reliability comparable to that of other state-of-the-art solutions while incurring negligible performance and energy overhead. Furthermore, the faulty locations are efficiently exposed to the operating system (OS). Thus, we can significantly reduce the required scrubbing cycle by scrubbing only faulty DRAM pages while reducing the system failure probability up to 5000∼7000 times relative to conventional operation.

Effect of Random Dopant Fluctuation on Data Retention Time Distribution in DRAM

We present a new simulation method for predicting the data retention time distribution including random dopant fluctuation (RDF). It is a critical problem that a long simulation time is required to predict a wide range of retention time distributions, but our model has extremely fast computation speed compared with the Monte–Carlo method and machine learning method. The proposed model is applied to the dynamic random access memory cell transistor of the 20 nm technology node. The simulation results show that RDF degrades data retention time, particularly in tail cells, and this can be effectively improved by reducing the interface trap density and the drain doping density.

Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory.

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory's data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, "0" state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.