Dynamic Power Reduction Research Articles

Low-standby-current and high-speed SAFF with improved conditional-precharge modules

A new low-power and high-speed sense-amplifier-based flip-flop with improved conditional-precharge modules (LSCP-SAFF) is proposed. By employing a modified differential latch with one shared output holder for the 2nd-stage and taking a novel clocked NMOS transistor to improve timing performance, the LSCP-SAFF can achieve a much shorter static CLK-to-Q delay and D-to-Q delay than those of the original conditional-precharge sense-amplifier-based flip-flop (CP-SAFF). Rather than the traditional CP-SAFF, a novel conditional-precharge scheme is adopted in the present study so that the standby power reduction ratio has reached 69%. Post-layout simulation results show that the LSCP-SAFF, compared with the conventional DFF of a modern industrial CMOS standard cell library, suffer from neither timing nor area penalties. Not only so, it has achieved up to 38% of the dynamic power reduction ratio and 42% of power-delay-product (PDP) reduction ratio, respectively. In addition, driven by low swing clock signals, the LSCP-SAFF is superior in both the timing performance and the standby power. Last, the reliability analysis shows that the LSCP-SAFF is less noise sensitive because of its fully differential structure.

Intelligate: An Algorithm for Learning Boolean Functions for Dynamic Power Reduction

In this work we introduce an enhanced methodology to detect dynamic invariants from a power-benchmark simulation trace database. The method is scalable for the application of clock-gating extraction on industrial designs. Our approach focuses upon dynamic simulation data as the main source for detection of opportunities for power reduction. Experimental results demonstrate our ability to learn accurate clock-gating functions from simulation traces and achieve significant power reduction (in the range of 30%-70% of the gated clock net's power) on industrial micro-processor designs.

Diagnosis of Multiple-Voltage Design With Bridge Defect

Multiple voltage is an effective dynamic power reduction design technique commonly used in low-power ICs. To the best of our knowledge, there is no reported work for diagnosing multiple-voltage enabled ICs, and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. By using synthesized ISCAS benchmarks, with realistic extracted bridges and a parametric fault model, this paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multivoltage diagnosis algorithm. In addition, it also identifies the most useful voltage settings to reduce diagnosis cost by eliminating tests at certain voltage setting using the proposed multivoltage diagnosis approach, thereby achieving high diagnosis accuracy at reduced cost.

Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips

In VLSI systems-on-chips (SoC), leakage is expected to override 50% of the total power consumption, and the memory sub-system can be responsible for up to 75% of the power. Scratch-pad memories (SPM) are a proven alternative to cache memories in power-aware SoCs. Optimal SPM mapping has already been investigated for dynamic power reduction in the main memory and for leakage reduction in the SPM itself. This paper addresses the problem of global energy optimization (i.e., active + leakage) in the whole memory sub-system of an SPM-based SoC. We focus on SPMs dedicated to instructions and constant data. We present the technology-level foundation, the mathematical problem formulation, its solution as an integer-linear-programming (ILP) problem, the implemented design flow, and the power reduction results referring to standard benchmarks and ITRS technology data.

Voltage and Level-Shifter Assignment Driven Floorplanning

Low Power Design has become a significant requirement when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for both dynamic and static power reduction while maintaining performance. Level shifters may cause area and Interconnect Length Overhead (ILO), and should be considered at both floorplanning and post-floorplanning stages. In this paper, we propose a two phases algorithm framework, called VLSAF, to solve voltage and level shifter assignment problem. At floorplanning phase, we use a convex cost network flow algorithm to assign voltage and a minimum cost flow algorithm to handle level-shifter assignment. At post-floorplanning phase, a heuristic method is adopted to redistribute white spaces and calculate the positions and shapes of level shifters. The experimental results show VLSAF is effective.

A Predictive Shutdown Technique for GPU Shader Processors

As technology continues to shrink, reducing leakage is critical to achieve energy efficiency. Previous works on low-power GPU (graphics processing unit) focus on techniques for dynamic power reduction, such as DVFS (Dynamic Voltage/Frequency Scaling) and clock gating. In this paper, we explore the potential of adopting architecture-level power gating techniques for leakage reduction on GPU. In particular, we focus on the most power-hungry components, shader processors. We observe that, due to different scene complexity, the required shader resources to satisfy the target frame rate actually vary across frames. Therefore, we propose the predictive shader shutdown technique to exploit workload variation across frames for leakage reduction on shader processors. The experimental results show that predictive shader shutdown achieves up to 46% leakage reduction on shader processors with negligible performance degradation.

Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity

In this paper, a new heuristic algorithm is proposed to optimize the power domain clustering in controlling-value-based (CV-based) power gating technology. In this algorithm, both the switching activity of sleep signals (p) and the overall numbers of sleep gates (gate count, N) are considered, and the sum of the product of p and N is optimized. The algorithm effectively exerts the total power reduction obtained from the CV-based power gating. Even when the maximum depth is kept to be the same, the proposed algorithm can still achieve power reduction approximately 10% more than that of the prior algorithms. Furthermore, detailed comparison between the proposed heuristic algorithm and other possible heuristic algorithms are also presented. HSPICE simulation results show that over 26% of total power reduction can be obtained by using the new heuristic algorithm. In addition, the effect of dynamic power reduction through the CV-based power gating method and the delay overhead caused by the switching of sleep transistors are also shown in this paper.

Thrifty BTB: A comprehensive solution for dynamic power reduction in branch target buffers

We propose Thrifty BTB, a mechanism to reduce the dynamic power dissipated by the BTB. We studied two mechanisms that reduce dynamic power dissipation. The first one is a serial-BTB configuration. The second mechanism is the filter-BTB, a combination of a low power counting Bloom filter placed in front of a conventional BTB. We also studied the effect of placing a small 32 entry direct-mapped BTB, functioning as a bypass, in parallel with the first two mechanisms. The filter-BTB reduces the number of lookups relative to a conventional BTB and the dynamic power dissipated. The serial-BTB variant only accesses the data array of the BTB upon a hit, therefore for most of the accesses the actual power dissipated is only what is dissipated by accessing the tag array. The bypass is used in parallel to either the filter- or the serial-BTB and reduces the performance cost by providing a low latency response in case of a hit. By integrating these mechanisms into a BTB design we achieve an average reduction of 51% in the dynamic power dissipation of the BTB. These benefits come at a small performance cost that is on average slightly less than 1.2%. The energy delay product was reduced by an average of 50%.

TI Low-Leakage130nm Digital Process with Nonvolatile FRAM for Ultra-Low-Power Medical Electronics

Both external and implantable devices are becoming more sophisticated and are requiring more on-chip memory to store data from biological sensors. To deal with this complexity, chip designs are moving toward smaller process geometries, which provide added functionality, reduced size, or both, often along with a reduction in dynamic power. However, leakage power begins to increase significantly at the 130nm node if steps are not taken to mitigate the increased transistor leakage. Lower operating voltages and careful transistor design can offset some of this increase. These very changes, however, make it difficult to design a dense, stable low-power SRAM. Nonvolatile memories like FRAM (F-RAM) avoid these difficulties and save power by simply turning off the memory when not in use. This is particularly valuable since many medical devices have very low duty cycle. FRAM provides the added benefit of providing SRAM-like active power, unlike competing nonvolatile technologies. To meet the challenging power requirements of medical devices, a new ultra-low-power 130nm process has been developed. The new process includes a very-high-density, SER-resistant, nonvolatile FRAM and an ultra-low-leakage transistor, coupled with a library that is optimized for low-power operation. This paper compares the power, area and performance of competing process technologies for a typical implantable medical design and highlights the advantages that FRAM provides in low static power through a transparent power-down capability and in low SRAM-like active power.

A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction

In sub-70 nm technologies, leakage power becomes a significant component of the total power. Designers address this concern by extensive use of adaptive voltage scaling techniques to reduce dynamic as well as leakage power. Low-power scan test schemes that have evolved in the past primarily address dynamic power reduction, and are less effective in reducing the total power. This paper proposes a Power-Managed Scan (PMScan) scheme which exploits the presence of adaptive voltage scaling logic to reduce test power. Some practical implementation challenges that arise when the proposed scheme is employed on industrial designs are also discussed. Experimental results on benchmark circuits and industrial designs show that employing the proposed technique leads to a significant reduction in dynamic and leakage power. The proposed method can also be used as a vehicle to trade-off test application time with test power by suitably adjusting the scan shift frequency and scan-mode power supplies.

Analysis of Options in Double-Gate MOS Technology: A Circuit Perspective

Double-gate MOS (DGMOS) technologies are emerging as possible substitutes for single-gate planar bulk devices in the near future. This paper defines and presents different DGMOS device-and circuit-design possibilities. It studies Schmitt triggers to eloquently analyze the interplay between noise immunity, circuit speed, and power dissipation as a function of device-level parameters. The asymmetric DGMOS devices and independent-gate technology can provide high noise immunity and dynamic power reduction at increased gate-delay, leakage-power, and process-sensitivity penalties. Furthermore, connected-gate DGMOS circuits work best with symmetric devices.

Gate-length biasing for runtime-leakage control

Leakage power has become one of the most critical design concerns for the system level chip designer. While lowered supplies (and consequently, lowered threshold voltage) and aggressive clock gating can achieve dynamic power reduction, these techniques increase the leakage power and, therefore, causes its share of total power to increase. Manufacturers face the additional challenge of leakage variability: Recent data indicate that the leakage of microprocessor chips from a single 180-nm wafer can vary by as much as 20/spl times/. Previously proposed techniques for leakage-power reduction include the use of multiple supply and gate threshold voltages, and the assignment of input values to inactive gates, such that leakage is minimized. The additional design space afforded by the biasing of device gate lengths to reduce chip leakage power and its variability is studied. It is well known that leakage power decreases exponentially and delay increases linearly with increasing gate length. Thus, it is possible to increase gate length only marginally to take advantage of the exponential leakage reduction, while impairing performance only linearly. From a design-flow standpoint, the use of only slight increases in gate length preserves both pin and layout compatibility; therefore, the authors' technique can be applied as a postlayout enhancement step. The authors apply gate-length biasing only to those devices that do not appear in critical paths, thus assuring zero or negligible degradation in chip performance. To highlight the value of the technique, the multithreshold voltage technique, which is widely used for leakage reduction, is first applied and then gate-length biasing is used to show further reduction in leakage. Experimental results show that gate-length biasing reduces leakage by 24%-38% for the most commonly used cells, while incurring delay penalties of under 10%. Selective gate-length biasing at the circuit level reduces circuit leakage by up to 30% with no delay penalty. Leakage variability is reduced significantly by up to 41%, which may lead to substantial improvements in the manufacturing yield and the product cost. The use of gate-length biasing for leakage optimization of cell instances is also assessed, in which: 1) not all timing arcs are timing critical and/or 2) the rise and fall transitions are not both timing critical at the same time.

Decomposing the load-store queue by function for power reduction and scalability

Because they are based on large, content-addressable memories, load-store queues (LSQs) present implementation challenges in superscalar processors. In this paper, we propose an alternate LSQ organization that separates the time-critical forwarding functionality from the process of checking that loads received their correct values. Two main techniques are exploited: First, the store-forwarding logic is accessed only by those loads and stores that are likely to be involved in forwarding, and second, the checking structure is banked by address. The result of these techniques is that the LSQ can be implemented by a collection of small, low-bandwidth structures yielding an estimated three to five times reduction in LSQ dynamic power.

Quantitative analysis and optimization techniques for on-chip cache leakage power

On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In nanometer-scale technology, the subthreshold leakage power is becoming one of the dominant total power consumption components of those caches. In this study, we present optimization techniques to reduce the subthreshold leakage power of on-chip caches assuming that there are multiple threshold voltages, V/sub T/'s, available. First, we show a cache leakage optimization technique that examines the tradeoff between access time and subthreshold leakage power by assigning distinct V/sub T/'s to each of the four main cache components-address bus drivers, data bus drivers, decoders, and static random access memory (SRAM) cell arrays with sense amplifiers. Second, we show optimization techniques to reduce the leakage power of L1 and L2 on-chip caches without affecting the average memory access time. The key results are: 1) two additional high V/sub T/'s are enough to minimize leakage in a single cache-3 V/sub T/'s if we include a nominal low V/sub T/ for microprocessor core logic; 2) if L1 size is fixed, increasing L2 size can result in much lower leakage without reducing average memory access time; 3) if L2 size is fixed, reducing L1 size may result in lower leakage without loss of the average memory access time for the SPEC2K benchmarks; and 4) smaller L1 and larger L2 caches than are typical in today's processors result in significant leakage and dynamic power reduction without affecting the average memory access time.

An Architecture Design Methodology for Minimal Total Power Consumption at Fixed <I>Vdd</I> and <I>Vth</I>

This paper presents a new methodology allowing to compare several architectures (or microarchitectures) performing the same function and to select the one presenting the smallest total power consumption under fixed supply voltage (Vdd), threshold voltage (Vth) and frequency (f ) constraints. The smallest total power consumption, which is closely related to the architecture, results clearly from a tradeoff between static and dynamic power. Static power reduction leads to select architectures with a small number of cells and not with a small number of transitions, as it was the case when only dynamic power reduction was targeted. As an example, this methodology is applied to the selection of the lowest power consuming architecture among a set of eleven 16 bit multipliers.

Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor

In this paper, a Dynamic Voltage and Frequency Management (DVFM) scheme introduced in a microprocessor for handheld devices with wideband embedded DRAM is reported. Our DVFM scheme reduces the power consumption effectively by cooperation of the autonomous clock frequency control and the adaptive supply voltage control. The clock frequency is controlled using hardware activity information to determine the minimum value required by the current processor load. This clock frequency control is realized without special power management software. The supply voltage is controlled according to the delay information provided from a delay synthesizer circuit, which consists of three programmable delay components, gate delay, RC delay and a rise/fall delay. The delay synthesizer circuit emulates the critical-path delay within 4% voltage accuracy over the full range of process deviation and voltage. This accurate tracking ability realizes the supply voltage scaling according to the fluctuation of the LSI's characteristic caused by the temperature and process deviation. The DVFM contributes not only the dynamic power reduction, but also the leakage power reduction. This microprocessor, fabricated in 0.18 μm CMOS embedded DRAM technology achieves 82% power reduction in a Personal Information Management scheduler (PIM) application and 40% power reduction in a MPEG4 movie playback application. As process technology shrinks, the DVFM scheme with leakage power compensation effect will become more important realizing in high-performance and low-power mobile consumer applications.

Leakage sources and possible solutions in nanometer CMOS technologies

Until recent years, dynamic power dissipation contributed the most to the chip's total power dissipation in CMOS digital circuits thus much attention was given to reduce this dynamic power. But as technology advances into the sub-100 nm regime, leakage power dissipation, which is a static power, increases at a much faster rate than dynamic power and it is expected to dominate the chips' total power dissipation. According to the 2004 update of the International Technology Roadmap for Semiconductors (ITRS), the required reduction of dynamic power beyond the reduction already given by technology scaling for a System-On-Chip (SOC) will grow from 0.1 in 2005 up to 8.1 reduction in 2018; at the same time the required reduction of a SOC standby power will exponentially grow from 2.4 in 2005 up to 232 in 20181.

Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

A novel nonvolatile logic style, called complementary ferroelectric-capacitor (CFC) logic, is proposed for low-power logic-in-memory VLSI, in which storage elements are distributed over the logic-circuit plane. Standby currents in distributed storage elements can be cut off by using ferroelectric-based nonvolatile storage elements, and the standby power dissipation can be greatly reduced. Since the nonvolatile storage and the switching functions are merged into ferroelectric capacitors by the capacitive coupling effect, reduction of active device counts can be achieved. The use of complementary stored data in coupled ferroelectric capacitors makes it possible to perform a switching operation with small degradation of the nonvolatile charge at a low supply voltage. The restore operation can be performed by only applying the small bias across the ferroelectric capacitor, which reduces the dynamic power dissipation. Applying the proposed circuitry in a fully parallel 32-bit content-addressable memory results in about 2/3 dynamic power reduction and 1/7700 static power reduction with chip size of 1/3, compared to a CMOS implementation using 0.6-/spl mu/m ferroelectric/CMOS.

A multi-level multi-phase charge-recycling method for low-power AMLCD column drivers

This paper describes a new low-power design concept appropriate for column drivers of high-resolution active matrix liquid crystal displays with a dot inversion method. The proposed multi-level multiphase charge-recycling method reduces power consumption incurred in driving highly capacitive column lines by storing the charge into the external capacitors and reusing it in the next cycle. With the proposed method, power consumption can be reduced asymptotically to zero with the infinite number of storage capacitors. However it is also shown that total power reduction can be counterbalanced by the power consumption in driving switches used in the recycling process. Analytical equations, simulation results, and measurement results from an experimental chip are shown to validate the proposed method. Dynamic power reduction of 55%-70% is measured with a three-level five-phase charge-recycling method compared with a conventional column driver.

Reducing switching activity on datapath buses with control-signal gating

This paper presents a technique for saving power dissipation in large datapaths by reducing unnecessary switching activity on buses. The focus of the technique is on achieving effective power savings with minimal overhead. When a bus is not going to be used in a datapath, it is held in a quiescent state by stopping the propagation of switching activity through the module(s) driving the bus. The observability don't-care of a bus is defined to detect unnecessary switching activity on the bus. This condition is used to gate control signals going to the bus-driver modules so that switching activity on the module inputs does not propagate to the bus. A methodology for automatically synthesizing gated control signals from the register transfer level description of a design is presented. The technique has very low area, delay, power, and designer effort overhead. It was applied to one of the integer execution units of a 64-bit, two-way superscalar RISC microprocessor. Experimental results from running various application programs on the microprocessor show an average of 26.6% reduction in dynamic switching power in the execution unit, with no increase in critical path delay and negligible area overhead.