Ongoing developments in the field of radiation-toleranthigh-speed transmitters (HSTs)aim at increasing the data rates above 25 Gb/s while increasingtotal ionizing dose (TID)tolerance above 1 Grad. The use of half-rate architectures imposes tight constraints on clock signal quality, in particular its duty-cycle. Radiation degradation of transistors in the clock path causesduty cycle distortion (DCD), affecting the output signal quality of the HST. In this paper, a digitally controlled duty-cycle correction circuit suitable for HST is presented. It compensates forprocess voltage temperature (PVT)variations as well as radiation-induced duty-cycle distortion of the clock.