Dual Gate Research Articles

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Design of Low Power SAR ADC with Novel Regenerative Comparator

This paper introduces two low-power design techniques for a successive approximation register (SAR) analog-to-digital converter (ADC) used in transmitting physiological signals. The first technique is called dual split switching, involving the use of a one-sided charge-scaling digital-to-analog converter (DAC) to minimize switching energy by reducing leakage in a dual transmission gate. The second technique, known as the set and reset phase, determines the amplification and comparison phases of the comparator. This approach reduces the delay time of the comparator through the use of a folded cascode pre-amplifier and a regenerative latch. The design includes a Serial-in-Parallel-Out (SIPO) N-bit register and SAR, implemented using negative edge-triggered D flip-flops (DFFs). To optimize power consumption, the supply voltage of the SAR ADC is set to 500 mV. The concept of a variable threshold is utilized throughout the design to enable operation with this lower supply voltage. The SAR ADC is designed to support a sampling rate of up to 1 Msps (mega-samples per second). The circuit is implemented using standard UMC180nm technology. According to the test results, the power consumption of the SAR ADC is only 29.06 uW, and the achieved sampling rate is 5 Ksps (kilo-samples per second). The maximum differential non-linearity (DNL) is measured to be +0.9/−0.82 least significant bits (LSBs).

Comparison study of RF/analog and linearity performance of dual material gate graphene source vertical TFET (DMG-GR-VTFET) and single material gate GR-VTFET

This paper investigates the comparative feature of Graphene Source Single Material Gate Vertical Tunnel FET (SMG-GR-VTFET) and Graphene Source Double Material Gate VTFET (DMG-GR-VTFET) on DC, analog/RF and linearity applications using Sentaurus TCAD simulator. The results show that both devices outperforms in DC characteristics, including ambipolar current, subthreshold swing (SS), ION/IOFF ratio etc The study focuses on important figures of merit (FOMs) such as transconductance (gm), output conductance (gd), cut-off frequency (ft), second-order transconductance (gm2), third-order transconductance (gm3), VIP2, and VIP3, which are all improved due to high mobility of graphene leads to improved band-to-band tunneling. The observed ION is 5.2 × 10−4 (1.1 × 10−3 A/μm), IOFF is 1.439 × 10−13 (2.28 × 10−16A/μm) and ION/IOFF ratio of 3.613 × 109 (4.824 × 1012) for SMG-GR-VTFET (DMG-GR-VTFET), respectively. It is seen that maximum gm is 2.96 × 10−3 (2.59 × 10−3 S μm−1) and cut-off frequency (ft) values of 1.1 × 1011 (1.85 × 1011 Hz) for SMG-GR-VTFET (DMG-GR-VTFET), respectively. Regarding the Linearity parameter VIP2 value is 2.71 V (0.99 V), respectively, for SMG-GR-VTFET (DMG-GR-VTFET). These results suggest that Graphene Source Vertical Tunnel FET is an excellent choice for analog and high-frequency applications.

Highly Stable Dual Gate a-InGaZnO Thin Film Transistor with Top Gate to Drain Offset for AC Gate Pulse Stress

Highly Stable Dual Gate a-InGaZnO Thin Film Transistor with Top Gate to Drain Offset for AC Gate Pulse Stress

A Novel Efficient Dual-Gate Mixed Dilated Convolution Network for Multi-Scale Pedestrian Detection

With the increasing use of onboard high-speed computing systems, vehicle manufacturers are offering significant advanced features of driver assistance systems. Pedestrian detection is one of the major requirements of such systems, which commonly use cameras, radar, and ultrasonic sensors. Image recognition based on captured image streams is one of the powerful tools used for the detection of pedestrians, which exhibits similarities and distinguishing features compared to general object detection. Although pedestrian detection has advanced significantly along with deep learning, some issues still need to be addressed. Pedestrian detection is essential for several real-world applications and is an initial step in outdoor scene analysis. Typically, in a crowded situation, conventional detectors are unable to distinguish persons from each other successfully. This study presents a novel technique, based on the Dual Gate Mixed Dilated Convolution Network, to address this problem by adaptively filtering spatial areas where the patterns are still complicated and require further processing. The proposed technique manages obscured patterns while offering improved multiscale pedestrian recognition accuracy.

A Novel Building Extraction Network via Multi-Scale Foreground Modeling and Gated Boundary Refinement

Deep learning-based methods for building extraction from remote sensing images have been widely applied in fields such as land management and urban planning. However, extracting buildings from remote sensing images commonly faces challenges due to specific shooting angles. First, there exists a foreground–background imbalance issue, and the model excessively learns features unrelated to buildings, resulting in performance degradation and propagative interference. Second, buildings have complex boundary information, while conventional network architectures fail to capture fine boundaries. In this paper, we designed a multi-task U-shaped network (BFL-Net) to solve these problems. This network enhances the expression of the foreground and boundary features in the prediction results through foreground learning and boundary refinement, respectively. Specifically, the Foreground Mining Module (FMM) utilizes the relationship between buildings and multi-scale scene spaces to explicitly model, extract, and learn foreground features, which can enhance foreground and related contextual features. The Dense Dilated Convolutional Residual Block (DDCResBlock) and the Dual Gate Boundary Refinement Module (DGBRM) individually process the diverted regular stream and boundary stream. The former can effectively expand the receptive field, and the latter utilizes spatial and channel gates to activate boundary features in low-level feature maps, helping the network refine boundaries. The predictions of the network for the building, foreground, and boundary are respectively supervised by ground truth. The experimental results on the WHU Building Aerial Imagery and Massachusetts Buildings Datasets show that the IoU scores of BFL-Net are 91.37% and 74.50%, respectively, surpassing state-of-the-art models.

HER2 and HLA-A*02 dual CAR-T cells utilize LOH in a NOT logic gate to address on-target off-tumor toxicity

BackgroundOne of the major challenges in chimeric antigen receptor (CAR)-T cell therapy for solid tumors is the potential for on-target off-tumor toxicity due to the expression of CAR tumor antigens...

Imaging quantum oscillations and millitesla pseudomagnetic fields in graphene

The exceptional control of the electronic energy bands in atomically thin quantum materials has led to the discovery of several emergent phenomena1. However, at present there is no versatile method for mapping the local band structure in advanced two-dimensional materials devices in which the active layer is commonly embedded in the insulating layers and metallic gates. Using a scanning superconducting quantum interference device, here we image the de Haas–van Alphen quantum oscillations in a model system, the Bernal-stacked trilayer graphene with dual gates, which shows several highly tunable bands2–4. By resolving thermodynamic quantum oscillations spanning more than 100 Landau levels in low magnetic fields, we reconstruct the band structure and its evolution with the displacement field with excellent precision and nanoscale spatial resolution. Moreover, by developing Landau-level interferometry, we show shear-strain-induced pseudomagnetic fields and map their spatial dependence. In contrast to artificially induced large strain, which leads to pseudomagnetic fields of hundreds of tesla5–7, we detect naturally occurring pseudomagnetic fields as low as 1 mT corresponding to graphene twisting by 1 millidegree, two orders of magnitude lower than the typical angle disorder in twisted bilayer graphene8–11. This ability to resolve the local band structure and strain at the nanoscale level enables the characterization and use of tunable band engineering in practical van der Waals devices.

Development of a microfluidic chip for protein preconcentration using dual gate structure and nanomembrane

Development of a microfluidic chip for protein preconcentration using dual gate structure and nanomembrane

Quality factor and digital inverter performance in gate underlap and overlap DMG FinFETs

This paper presents a comparative 3D simulation study of Quality factor among Gate Underlap and Overlap techniques in both Si and Ge Dual Material Gate (DMG) FinFETs using the Sentaurus TCAD tool. The results of both the techniques are carefully examined and compared with Conventional DMG FinFET to analyze the performances of these devices. The effect of gate overlap/underlap techniques on threshold voltage (Vth), ION/IOFF ratio, drain induced barrier lowering (DIBL), transconductance (gm), subthreshold swing (SS), and Quality factor (Q) are investigated. It is found that Ge DMG FinFETs have higher gm and quality factor values as compared to Si DMG FinFETs. The prospects of these techniques in low-power digital applications have been performed by implementing complementary Si DMG FinFET based inverter circuit. We have extracted the average delay and noise margin, where the overlap structure performs better such as high current gain and no overshoot/undershoot peaks in the transient characteristics.

Characterization and Reliability Analysis of Enhancement-Mode PEALD AlN/LPCVD SiNx GaN MISFET with In Situ H2/N2 Plasma Pretreatment

An effective in situ H2/N2 pretreatment technique for enhancement-mode GaN MISFET with a PEALD AlN/LPCVD SiNx Dual Gate Dielectric is presented. This technique features in situ H2 (15%)/N2 (85%) plasma pretreatment prior to AlN deposition. By using in situ H2 (15%)/N2 (85%) plasma pretreatment and a PEALD AlN protection layer, combined with an LPCVD SiNx gate dielectric, the quality of the AlN/GaN interface can be further improved due to the reduced interface trap densities between the AlN/GaN interface. The interface protection technique enables the successful integration of a high-quality PEALD AlN/LPCVD SiNx gate dielectric in an E-mode GaN MISFET with high performance, high stability, and high reliability. The fabricated enhancement-mode GaN MISFET exhibits a high gate swing and high channel effective mobility of 187.5 cm2/Vs, a threshold voltage of 2.9 V defined at 1 µA/mm, an on/off current ratio of 108, and a breakdown voltage of 1760 V defined at ID = 10 μm/mm. Our experiments showed a significant reduction in dynamic ON resistance and the suppression of current collapse when using the enhancement-mode GaN MISFET with PEALD AlN/LPCVD SiNx under high drain bias switching conditions, especially when the VDS is greater than the 60 V drain bias switch operating state.

A multi-attention and depthwise separable convolution network for medical image segmentation

Automatic medical image segmentation method is highly needed to help experts in lesion segmentation. The deep learning technology emerging has profoundly driven the development of medical image segmentation. While U-Net and attention mechanisms are widely utilized in this field, the application of attention, albeit successful in natural scene image segmentation, tends to inflate the number of model parameters and neglects the potential for feature fusion between different convolutional layers. In response to these challenges, we present the Multi-Attention and Depthwise Separable Convolution U-Net (MDSU-Net), designed to enhance feature extraction. The multi-attention aspect of our framework integrates dual attention and attention gates, adeptly capturing rich contextual details and seamlessly fusing features across diverse convolutional layers. Additionally, our encoder integrates a depthwise separable convolution layer, streamlining the model’s complexity without sacrificing its efficacy, ensuring versatility across various segmentation tasks. The results demonstrate that our method outperforms state-of-the-art across three diverse medical image datasets.

Impact of Deep Cryogenic Temperatures on High-k Stacked Dual Gate Junctionless MOSFET Performance: Analog and RF analysis

Impact of Deep Cryogenic Temperatures on High-k Stacked Dual Gate Junctionless MOSFET Performance: Analog and RF analysis

Exploring Performance and Reliability Behavior of Nanosheet Channel Thin-Film Transistors under Independent Dual Gate Bias Operation

In this work, the polycrystalline-silicon (poly-Si) thin-film transistor with an independent dual-gate (IDG) structure and ultra-thin nanosheet channel (∼4 nm) is fabricated to investigate the impacts of different dual-gate operation modes on device performance and reliability. Compared to the single top-gate (TG) operation mode, the double-gate (DG) operation mode exhibits superior threshold voltage (VTH), subthreshold swing, and saturation current in the device. In addition, the DG operation mode also shows better reliability behavior of positive gate bias stress (PGS) due to the enhanced control capability of the gate voltage on the channel potential. Under the single TG operation mode, the independent back-gate voltage (VBG) can effectively modulate the device’s VTH to meet circuit design requirements. Using a fixed positive VBG can not only reduce the VTH of the device, but also decrease the damage caused by the PGS on the device due to the buried channel effect generated by the ultra-thin nanosheet channel, which increases the coupling capacitance thickness between the buried channel and the top-gate oxide layer. On the contrary, using a negative VBG will enhance the PGS degradation of TG. Consequently, the positive VBG is suggested to lower the VTH and improve the PGS of the device.

Ultra Sensitive Breast Cancer Cell Lines Detection Using Dual Nanocavities Engraved Junctionless FET.

This article reports breast cancer cell lines (Hs578T, MDA-MB-231, MCF-7, and T47D) and healthy breast cells (MCF-10A) detection based on the modulation of its electrical properties by deploying dual nanocavity engraved junctionless FET. The device has a dual gate to enhance gate control and has two nanocavities etched under both gates for breast cancer cell lines immobilization. As the cancer cells are immobilized in the engraved nanocavities, which were earlier filled with air, the dielectric constant of the nanocavities changes. This results in the modulation of the device's electrical parameters. This electrical parameters modulation is then calibrated to detect the breast cancer cell lines. The reported device demonstrates a higher sensitivity toward the detection of breast cancer cells. The JLFET device optimization is done for improving the performance by optimizing the nanocavity thickness and the SiO2 oxide length. The variation in the dielectric property of cell lines plays a key role in the detection technique of the reported biosensor. The sensitivity of the JLFET biosensor is analyzed in terms of ∆VTH, ∆ION, ∆gm , and ∆SS . The reported biosensor shows the maximum sensitivity for T47D ( κ = 32 ) breast cancer cell line with ∆VTH = 0.800 V, ∆ION = 0.165 mA/μm, ∆gm = 0.296 mA/V-μm , and ∆SS = 5.41 mV/decade. Moreover, the effect of variation in the occupancy of the cavity by the immobilized cell lines has also been studied and analyzed. With increased cavity occupancy the variation in the device performance parameter enhances Further, the sensitivity of the proposed biosensor is compared with the existing biosensors and it is reported to be highly sensitive as compared to the existing biosensors. Hence, the device can be utilized for array based screening of cell lines of breast cancer and diagnosis with the benefit of easier fabrication and cost effectiveness of the device.

A Simulation Study of the Effect of Trap Charges and Temperature on Performance of Dual Metal Strip Double Gate TFET

A Simulation Study of the Effect of Trap Charges and Temperature on Performance of Dual Metal Strip Double Gate TFET

Reliable measurement methods for the isovolumic relaxation time: comparisons of dual gate Doppler and seven other methods

PurposeIsovolumic relaxation time (IVRT) is a useful indicator of diastolic dysfunction. However, a measurement method for IVRT has not been established. The Dual Gate Doppler method, which can record two separate pulse-wave Doppler signals simultaneously using two sample gates, may be ideal for measuring IVRT. This study aimed to evaluate the accuracy of IVRT measured using conventional methods versus that measured using the Dual Gate Doppler method.MethodsA total of 104 patients (mean age 58 ± 21 years, 48 women) were examined using ultrasound equipment with Dual Gate Doppler at our hospital. In addition to Dual Gate Doppler method, IVRTs were measured using seven different methods: pulsed Doppler (PW method), continuous wave Doppler (CW method), and other methods. The IVRT values obtained using the Dual Gate Doppler method were compared with those measured using other methods.ResultsAll IVRTs measured using conventional methods showed a strong correlation with the that measured using the Dual Gate Doppler method. However, there were slight deifferences among the IVRTs depending on the method. The PW method and the PW time difference method using only the PW showed small statistical bias and were not complicated. The IVRT measured using the CW method was significantly longer than that measured using the Dual Gate Doppler method.ConclusionsAmong the conventional methods, the PW method was the simplest and most practical method for measuring the IVRT in any conditions as arrhythmias. It is important to recognize the characteristics of IVRTs based on the measurement method.

Automated bone marrow cell classification through dual attention gates dense neural networks.

The morphology of bone marrow cells is essential in identifying malignant hematological disorders. The automatic classification model of bone marrow cell morphology based on convolutional neural networks shows considerable promise in terms of diagnostic efficiency and accuracy. However, due to the lack of acceptable accuracy in bone marrow cell classification algorithms, automatic classification of bone marrow cells is now infrequently used in clinical facilities. To address the issue of precision, in this paper, we propose a Dual Attention Gates DenseNet (DAGDNet) to construct a novel efficient, and high-precision bone marrow cell classification model for enhancing the classification model's performance even further. DAGDNet is constructed by embedding a novel dual attention gates (DAGs) mechanism in the architecture of DenseNet. DAGs are used to filter and highlight the position-related features in DenseNet to improve the precision and recall of neural network-based cell classifiers. We have constructed a dataset of bone marrow cell morphology from the First Affiliated Hospital of Chongqing Medical University, which mainly consists of leukemia samples, to train and test our proposed DAGDNet together with the bone marrow cell classification dataset. When evaluated on a multi-center dataset, experimental results show that our proposed DAGDNet outperforms image classification models such as DenseNet and ResNeXt in bone marrow cell classification performance. The mean precision of DAGDNet on the Munich Leukemia Laboratory dataset is 88.1%, achieving state-of-the-art performance while still maintaining high efficiency. Our data demonstrate that the DAGDNet can improve the efficacy of automatic bone marrow cell classification and can be exploited as an assisting diagnosis tool in clinical applications. Moreover, the DAGDNet is also an efficient model that can swiftly inspect a large number of bone marrow cells and offers the benefit of reducing the probability of an incorrect diagnosis.

Enhanced Quasi-Static Energy Recovery and Modified Clock Gating for the Wallace Tree Multiplier with Reversible Adders

High-speed, low-power digital circuits are essential in many digital applications. The objective of the paper is to design high-speed low-power multipliers with reversible gates. The realization of a multiplier with an efficient clocking system is also presented to reduce leakage power consumption. The existing reversible configurations do not possess an effective clocking system for reducing power in an idle state. In this work, a modified clock gating (MCG) and Enhanced Quasi-Static Energy Recovery Logic (EQSERL) are designed to generate a clock pulse. The EQSERL reduces the dynamic state in the circuit and it is designed with reduced complexity. This process effectively reduces leakage power consumption in the circuit. The conventional clock gating circuit is modified for connecting it with the EQSERL. This MCG circuit reduces unwanted power consumption. The conventional Wallace tree multiplier (WTM) involves full adder and half adder circuits. In this proposed work, a square root carry select adder (SQRT CSLA) with a reversible binary to excess-1 converter (BEC) and a ripple carry adder is presented. The reversible gates such as the Feynman gate, the Toffoli gate, and the dual key gate are employed. Finally, the proposed architecture is tested with different clocking circuits using Synopsys tools and the performance metrics like delay and power are observed.

Carrier confinement for mobility enhancement in dual-gate organic thin-film transistors

Mobility of charge carriers in organic thin-film transistors (OTFTs) is one of the most important parameters, which is affected by the disorders in the semiconducting films. In general, realization of higher carrier concentration facilitates improved charge transport against these disorders. Here, we demonstrate in amorphous indacenodithiophen-co-benzothiadia (IDT-BT) based dual-gate organic thin-film transistors (DG-OTFTs) that the mobility can be robustly increased from 0.8 to 1.37 cm2 V−1 s−1, when voltage biases of opposite signs (negative one accumulate holes, positive one deplete holes) are applied on the dual independent gate electrodes. In details, the positive bias can confine the spatial distribution of the accumulated carriers near the negatively biased gate, leading to a higher effective carrier concentration with higher mobility. In addition, the interface confinement effect of carriers was further verified by two-dimensional numerical simulation, and calculations based on the variable range hopping method were performed to accurately reproduce the experimentally observed charge transport behavior in DG-OTFTs.