Dual Gate Research Articles

A computational approach to optimize the linearity in dual-gate InAlGaN/AlN/GaN HEMTs

Abstract This paper investigates the effect of the proposed dual gate structures in enhancing the linearity of InAlGaN/AlN/GaN high-electron-mobility transistors (HEMTs) using TCAD analysis. Through the comprehensive analysis of the dual gate structure with the additional gate placed between the gate-source (DG-GS) and gate-drain (DG-GD) regions, the impact on the linearity performance has been compared with that of a standard single gate (SG) structure. The dual gate configuration exhibits a flatter and broader transconductance (gm) profile than the single gate configuration. The reduction in the third-order intermodulation levels is confirmed with the polynomial fitting method. The fT/fmax of the DG-GS case is simulated to be 52/102 GHz, which shows that such configuration does not deteriorate the RF performance. Comprehensive simulations are carried out to study the device physics and assess the mechanism behind the linearity improvement. The large signal model has been developed to examine the large signal RF performance as well as linearity performance metrics. An improvement of 9.6 dB in the carrier-to-intermodulation (C/I) ratio and that of 2.4 degrees in the amplitude-to-phase modulation (AM-to-PM) at 6-dB backoff from Psat have been observed as compared to the SG configuration. Such characteristics have evidenced that the optimized dual-gate configuration with the second gate placed between the source and gate can effectively improve the linearity performance of the InAlGaN/AlN/GaN HEMT configurations.

Ultra-sensitive dengue NS1 protein detection via asymmetric source-drain, heterojunction and dual-dielectric cavities in a uniform tunnel FET biosensor

In this paper, we present a unique Asymmetric Source-Drain Heterojunction Dual-Dielectric Uniform Tunnel Field Effect Transistor (A-SD-HJ-DD-UTFET) based biosensor tailored for the early detection of dengue NS1 protein during the acute phase of infection offering early diagnosis and potentially life-saving intervention. The proposed biosensor design features simplified fabrication, a narrow drain region, and a dual material control gate, enhancing specificity and sensitivity for dengue virus detection. Using a heterojunction configuration, this device optimizes electron flow for improved detection accuracy. The roles of Tunnel Gate (TG) and Auxiliary Gate (AG) are studied in terms of band energy, electric field, electrostatic potential, and other sensitivity parameters. Sentaurus TCAD tool is utilized for analyzing the characteristics of the proposed A-SD-HJ-DD-UTFET biosensor. Simulation results indicate that the designed A-SD-HJ-DD-UTFET biosensor achieves a superior Subthreshold Swing (SS) of 15.4 mV/dec and an enhanced ION/IOFF sensitivity of about 2.25 × 10¹¹ with a maximum ON and minimum OFF state currents of 2.28 × 10–4 A/μm and 1.28 × 10–16 A/μm respectively for detecting NS1 protein of dengue. Additionally, it boasts a high switch ratio in the order of 1012. The proposed biosensor outperforms conventional devices, including the state-of-the-art Junctionless (JL)-TFET biosensors. The superior electrical characteristics of the proposed A-SD-HJ-DD-UTFET biosensor make it a promising device for early detection of the dengue NS1 protein, providing a potent solution for mitigating the spread of dengue infections.

Hetero dielectric based dual material gate AlGaN channel MISHEMT for enhanced electrical characteristics

Herein, we report an AlGaN channel metal insulator semiconductor high electron mobility transistor (MISHEMT) in dual material gate (DMG) architecture with two different dielectrics as gate insulator for enhancing the DC performance of the device. The use of a high-k dielectric material as gate insulator below gate metal 1 and a low-k dielectric below gate metal 2 results in significant threshold voltage variation along the channel. This contributes to improved average carrier velocity which in turn results in better current drive. The proposed device exhibits a peak current of 162 mA/mm at zero gate bias, whereas, the DMG and single material gate (SMG) AlGaN channel HEMTs offer currents of 137 mA/mm and 125 mA/mm respectively. The peak transconductances are about 24.66 mS/mm, 23.68 mS/mm and 22.71 mS/mm respectively for the proposed device, DMG and SMG HEMTs. The proposed device reduces the OFF current by an order of 106 compared to that of DMG HEMT.

Dual-gate AlGaN channel HEMTs: advancements in E-mode performance with N-shaped graded composite barriers

Abstract This work evaluates the performance of dual gate AlGaN channel HEMTs on SiC substrate. The study analyzes two HEMT structures that differ only in barrier design, one design consists of fixed composite barriers (FCB-HEMT) i.e. there is fixed Aluminum composition x = 0.48 in the first Al x Ga1−x N barrier and x = 0.42 in the second Al x Ga1−xN barrier while the other design comprises N-shaped graded composite barriers (NGCB-HEMT) i.e. the Aluminum content varies gradually from 0.4 to 0.48 in the first AlGaN barrier and from 0.34 to 0.42 in the second AlGaN barrier. The paper concentrates on energy band diagrams, electron concentration profile, electric field distribution, drain and transfer characteristics, and the effects of high temperature on drain characteristics and mobility of the NGCB-HEMT. It has been reported that at zero gate bias, the FCB-HEMT has a drain current density of 0.137 A mm−1 while it decreases to 0.0058 A mm−1 in the case of NGCB-HEMT, thus presenting a novel approach towards enhancement-mode AlGaN HEMTs. Hence, grading can be optimized in the composite barriers to achieve enhancement mode operation of AlGaN channel HEMTs. Furthermore, the study reveals that the critical electric field of FCB-HEMT is 6.9975 M V cm−1, while that of NGCB-HEMT is 5.3124 M V cm−1, demonstrating their usefulness in electronic devices that operate at high voltages and harsh temperatures. Moreover, at higher temperatures, the phenomenon of optical phonon scattering leads to decreased mobilities, which in turn causes low drain currents relative to the drain voltage.

High-Performance Dual-Gate Transistors Based on Aligned Carbon Nanotubes.

Aligned carbon nanotubes (A-CNTs), with atomic-scale thickness and ultrahigh carrier mobility, hold promise for constructing future sub-1 nm node integrated circuits (ICs) with higher speed and lower power consumption. However, the fabricated A-CNT transistors often suffer from the disorder of high-density CNT, which degrade the off-characteristic deviating significantly from theoretical values. Introducing a dual-gate (DG) configuration can provide higher gate control efficiency compared to conventional single-gate (SG) transistors and is expected to enhance the overall performance of A-CNT transistors. However, the reported A-CNT dual-gate field-effect transistors (DG-FETs) still exhibit nonideal switching behavior, and systematic exploration and optimizations for constructing high-performance A-CNT DG structures have been lacking so far. In this work, we conducted a detailed study on the matching issues between the top-gate (TG) and bottom-gate (BG) stacks. By optimizing the gate metal materials and dielectric layer thickness, we enabled 20 nm channel A-CNT DG-FETs to achieve leading switching characteristics, including an on-state current density (Ion) of up to 1.47 mA/μm, a peak transconductance (Gm) of 2 mS/μm, a subthreshold slope (SS) as low as 83 mV/decade, and a current on/off ratio of 106. This study provides critical experimental guidance for constructing outstanding A-CNT DG-FETs at advanced technology nodes to compete with cutting-edge silicon-based chips and is also valid for two-dimensional channels.

A FinFET Based Low-Power Write Enhanced SRAM Cell With Improved Stability

This work introduces a FinFet based low-power 11T SRAM cell with write enhanced feature, which is considered to meet modern technology requirements due to its distinctive features and performance. The proposed 11T SRAM cell is designed in such a way, so that it reduces the overall power consumption, improving access time, and static noise margin (SNM), especially during the write operation. The proposed 11T SRAM cell is compared with other SRAM cells, including conventional 6T (conv6T), dual pull-up transistor 10T (DPUT10T), dual pull-down transistor 10T (DPDT10T), dual transmission gate 9T (DTG9T), and dual transmission gate 10T (DTG10T), at an equitable standard. The results obtained at the supply voltage of 0.5 V @ 27 °C shows the reduction in leakage power during hold 1 operation by 1.61×/1.33×/1.44×/1.63×/1.46×, and reduction in power consumption during read operation by 1.02×/1.55×/ 1.01×/1.81×/1.97× in comparison with conv6T/DPUT10T/ DPDT10T/DTG9T/DTG10T, respectively. Write access time is also improved by a factor of 1.67×/1.71×/2.59×/1.45×/1.97×, respectively. Additionally, read static noise margin (RSNM) and write static noise margin (WSNM) are improved by 2.03×/1.01×/1.65×/1.54×/1.43×, and 1.42×/1.33×/1.41×/1.02×/1.62×, respectively. This demonstrates why the proposed low-power 11T SRAM cell is desirable, especially when compared to the other cells under consideration.

Design and analysis of central gate organic thin film transistor

Abstract This paper presents a novel central gate organic thin-film transistor (OTFT) with electrodes in top-bottom configuration and its comparative performance analysis with conventional single and dual gate OTFTs. The central gate OTFT is comprised of a single gate electrode configured to be the center thin film. A pair of identical dielectric layers viz. top dielectric layer and a bottom dielectric layer on both sides of gate electrode to facilitate the further deposition top and bottom organic semiconductor layer over them respectively. The organic semiconductor layers (OSC) are configured as top OSC layer and a bottom OSC to accommodate two independent conduction channels. The source and drain electrodes are also deposited in pairs in top and bottom configurations. Due to the subtle modifications in the architecture the resultant output drain current of the central gate (CG) OTFT has increased manifold. It has been found in the study that the CG OTFT produces 94%, 76.36%, 80.58% higher drain current than bottom gate bottom contact (BGBC), top gate bottom contact (TGBC) and bottom gate top contact (BGTC) OTFT respectively of similar size, operating under identical voltage regime. Similarly in the case of dual gate (DG) OTFT an improvement of 5.10% has been recorded without any additional gate electrode at the same operating voltages.

Assessment of Trap Charges for Analog/RF FOMs and Linearity Behaviour on InAs Based Dual Metal Hetero Gate Oxide TFET for Enhanced Reliability

Assessment of Trap Charges for Analog/RF FOMs and Linearity Behaviour on InAs Based Dual Metal Hetero Gate Oxide TFET for Enhanced Reliability

Artificial synapse based on low-voltage Ni-doped CuI thin-film transistors for neuromorphic application

Inspired by the human brain's capacity as a powerful biological computer capable of simultaneously processing a vast array of cognitive tasks, many emerging artificial synapse devices have been developed in recent years. Electric-double-layer (EDL) transistors based on interfacial ion-modulation have attracted widespread attention for simulating synaptic plasticity and neural functions. Here, low-voltage EDL p-type thin-film transistors (TFTs) are fabricated on glass substrates, with Ni-doped cuprous iodide (Ni0.06Cu0.94I) as the channel and chitosan as the dielectric. The electrical performance of the Ni0.06Cu0.94I TFTs is investigated: current on/off ratio of 6.4 × 104, subthreshold swing of 33 mV/dec, threshold voltage of 1.38 V, operating voltage of 2 V, and saturation field-effect mobility of 15.75 cm2 V−1 s−1. A dual in-plane gate OR logic operation is demonstrated. Importantly, by applying single voltage pulses, dual voltage pulses, and multiple voltage pulses to the gate, the Ni0.06Cu0.94I transistors exhibited typical synaptic characteristics, including short-term potentiation, short-term depression, long-term potentiation, long-term depression, paired-pulse facilitation, and spiking-rate-dependent plasticity. Furthermore, the synaptic transistor can also simulate the learning–forgetting–relearning process of the human brain. These remarkable behaviors of voltage-stimulated synaptic transistors have potential for neuromorphic applications in future artificial systems.

Impact of underlap layer on DC and RF/analog performance of asymmetric junctionless dual material double gate MOSFET for low-power analog amplifier design

Impact of underlap layer is analytically investigated on asymmetric junctionless dual material double gate MOSFET (AJDMDG) to reduce subthreshold slope and threshold voltage, which are two essential requirements with shrinking device dimensions to avoid short channel effects. The model utilizes two-dimensional Poisson’s equation with parabolic approximation for determining electrical parameters where dimensional ranges are kept within fabrication limit. Excellent accuracy is found for the obtained analytical outcome, when compared with results obtained from TCAD ATLAS simulator. Comparative study is extended for conventional junctionless DMDG (JDMDG) and underlap asymmetric junctionless single material DGFET (UAJDG) device, having identical dimensional parameters and biasing ranges; where the present structure exhibits superior performance in terms of threshold voltage, subthreshold slope and DIBL of 34.57%, 62.85% and 69.85% respectively compared to JDMDG and 12.50%, 26.08% and 40.25% respectively w.r.t UAJDG structure. Supremacy of the proposed architecture is further established with RF/analog Figures of Merit (FOMs), which are essential for designing low power analog amplifier.

Impact of deep cryogenic temperatures on gate stack dual material DG MOSFET performance: Analog and RF analysis

By understanding the potential benefits of Gate Stack Dual Material double gate MOSFET (DG MOSFET), this research aims to contribute to the investigation of its electrical characteristics with improved performance and dependability. A detailed investigation is conducted into the temperature dependent electrical properties at different temperatures. A detailed analysis is conducted on the enhanced gate controllability in lower technology nodes and the protection against short channel effects. Together with the DC performances, this research also analyzes the suggested device's analog performance. The device's performance matrix was presented for temperatures ranging from 70 K to 800 K. The results showsthe improvement the drain current, transconductance, and transconductance generation factor(TGF) with decrease in temperature.

Persistent polarization effects and memory properties in ionic-liquid gated InAs nanowire transistors

Iontronics exploits mobile ions within electrolytes to control the electronic properties of materials and devices' electrical and optical response. In this frame, ionic liquids are widely exploited for the gating of semiconducting nanostructure devices, offering superior performance compared to conventional dielectric gating. In this work, we engineer ionic liquid gated InAs nanowire-based field effect transistors and adopt the set-and-freeze dual gate device operation to probe the nanowires in several ionic gate regimes. We exploit standard back-gating at 150 K, when the ionic liquid is frozen and any crosstalk between the ionic gate and the back gate is ruled out. We demonstrate that the liquid gate polarization has a persistent effect on the nanowire properties. This effect can be conveniently exploited to fine-tune the properties of the nanowires and enable new device functionalities. Specifically, we correlate the modification of the ionic environment around the nanowire to the transistor threshold voltage and hysteresis, on/off ratio and current level retention times. Based on this, we demonstrate memory operations of the nanowire field effect transistors. Our work shines a new light on the interaction between electrolytes and semiconducting nanostructures, providing useful insights for future applications of nanodevice iontronics.

Device and circuit-level performance evaluation of DG-GNR-DMG vertical tunnel FET

This work presents the comparative study of Graphene Nanoribbon (GNR) based channel Double Gate (DG) Dual Gate Material (DMG) Vertical tunnel Field Effect Transistor (VTFET) performance with all Silicon material Tunnel Field Effect Transistor. The two-dimensional (2D) material GNR has been proposed in the channel material to enhance the device performance due to its low bandgap, high mobility, and high saturation velocity. The proposed device's DC, RF, and circuit-level performance analysis has been carried out for the first time. GNR-based channel VTFET shows a better average subthreshold swing (SSAVG) of 16 mV/decade compared to Silicon Vertical Tunnel FET (36 mV/decade) at a drain voltage VDS = 0.5 V. The study of temperature effects on the DC parameters is also included along with the analog/RF FOMs for the proposed two structures. In addition, the performances are compared with other reported works; it is observed that DG-GNR-DMG-VTFET offers better results than Silicon (Si)-based VTFET and other said TFET work. Finally, circuit-level analysis has been done by designing inverter and ring oscillator circuits for the proposed structures, and performance is compared in these two devices. The market-available Silvaco ATLAS TCAD simulator has been used for device-level simulation. Further, circuit-level analysis has been carried out in the Cadence Virtuoso tool using a look-up table-based Verilog-A model.

A modified gate oxide tunnel Field-Effect transistor (TFET) biosensor to identify receptor Tyrosine-Protein kinase 2 (C-erbB-2) in Serum/Saliva

This research demonstrates an analysis of a modified gate oxide tunnel field-effect transistor (TFET) with pocket (Poc-MGOTFET) biosensor for the incredibly sensitive and real-time identification of the breast cancer (BC) biomarker receptor tyrosine-protein kinase (C-erbB-2) in serum and saliva. This research investigates the impact of interface charge modulation in Poc-MGOTFET biosensor with embedded cavities for rapid, accurate, and reliable identification of antigens in bodily fluids, like serum and saliva. The TCAD Sentaurus is used to numerically simulate the proposed biosensor in 2D. The dual cavity etched underneath the dual gate electrode of the proposed biosensor facilitates biomolecule immobilization. This enhances the ability of biomolecules to regulate the source/channel tunneling rate and the proposed biosensor’s electrical performance metrics. A numerical model is developed for the interface charge equivalent of the C-erbB-2. The sensitivity of the device to different C-erbB-2 concentrations in serum/saliva has been studied. The results of our research demonstrate that Poc-MGOTFET, featuring an extended gate structure, modified gate oxide, and pocket along the source side, reduces the leakage current (ILeakage) and OFF current (IOFF), enhances the probability of tunneling, boosts gate control for a greater ON current (ION) and ION/IOFF ratio, and increases sensitivity. Moreover, increased sensitivity by an order of magnitude 106 results from the effect of interface charges corresponding to varying concentrations of C-erbB-2 biomarkers on the sensitivity of the biosensor (as measured by the ION/IOFF ratio).

A fast-switching low-loss field-stop IGBT with dual control gate of SIPOS material

A fast-switching low-loss field-stop insulated gate bipolar transistor with a dual control gate (DIGBT) of a semi-insulating polycrytalline silicon (SIPOS) material is proposed in this paper. Because the SIPOS has uniform high resistance, it has an approximate linear electric potential distribution. When DIGBT conducts, the higher electric potential on SIPOS causes the P-type drift region (P-drift) to generate an inversion layer of electrons, adjusting the number of carriers and making the generation of non-equilibrium carriers no longer dependent on the doping concentration in P-drift (Nd) but on the electric potential distribution on SIPOS. Therefore, it can solve the contradiction among the breakdown voltage, forward voltage drop [VCE(sat)], turn-off time (toff), and turn-off loss (Eoff) caused by the Nd. Through Technology Computer Aided Design (TCAD) simulation, the VCE(sat) of DIGBT is 30.6% lower than that of SJFS IGBT. Meanwhile, DIGBT reduces the toff by 62.8% while reducing the Eoff by 83.0% compared to SJFS IGBT. In addition, the static latch-up I–V and the forward biased safe operating area of the DIGBT have been significantly improved. This paper adjusts the number of carriers through the characteristics of SIPOS material, enabling the above-mentioned physical phenomena to be applied in insulated gate bipolar transistor power devices and achieving device performance breakthroughs.

Thermal Effects on Monolithic 3D Ferroelectric Transistors for Deep Neural Networks Performance

Monolithic three‐dimensional (M3D) integration advances integrated circuits by enhancing density and energy efficiency. Ferroelectric thin‐film transistors (Fe‐TFTs) attract attention for neuromorphic computing and back‐end‐of‐the‐line (BEOL) compatibility. However, M3D faces challenges like increased runtime temperatures due to limited heat dissipation, impacting system reliability. This work demonstrates the effect of temperature impact on single‐gate (SG) Fe‐TFT reliability. SG Fe‐TFTs have limitations such as read‐disturbance and small memory windows, constraining their use. To mitigate these, dual‐gate (DG) Fe‐TFTs are modeled using technology computer‐aided design, comparing their performance. Compute‐in‐memory (CIM) architectures with SG and DG Fe‐TFTs are investigated for deep neural networks (DNN) accelerators, revealing heat's detrimental effect on reliability and inference accuracy. DG Fe‐TFTs exhibit about 4.6x higher throughput than SG Fe‐TFTs. Additionally, thermal effects within the simulated M3D architecture are analyzed, noting reduced DNN accuracy to 81.11% and 67.85% for SG and DG Fe‐TFTs, respectively. Furthermore, various cooling methods and their impact on CIM system temperature are demonstrated, offering insights for efficient thermal management strategies.

Gate-tunable subband degeneracy in semiconductor nanowires

Degeneracy and symmetry have a profound relation in quantum systems. Here, we report gate-tunable subband degeneracy in PbTe nanowires with a nearly symmetric cross-sectional shape. The degeneracy is revealed in electron transport by the absence of a quantized plateau. Utilizing a dual gate design, we can apply an electric field to lift the degeneracy, reflected as emergence of the plateau. This degeneracy and its tunable lifting were challenging to observe in previous nanowire experiments, possibly due to disorder. Numerical simulations can qualitatively capture our observation, shedding light on device parameters for future applications.

Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs

In this work, the trap sensitivity of single material gate (SMG) and dual material gate (DMG) nano ribbon FETs (NRFETs) are reported using TCAD Sentaurus Device simulator. The trap sensitivity is extracted for Gaussian trap distribution of both acceptor and donor type traps. We have reported the trap sensitivity for the variation in trap concentration, energy peak position, work function of metal gate, and temperature for both the NRFETs. It is realized that trap sensitivity is greater and lesser than 100% for acceptor type trap in SMG and DMG NRFETs, respectively, whereas, such sensitivity is 147% and 123% for donor type trap concentration, respectively. Temperature also shows a significant variation in trap sensitivity for both the NRFETs. The increase in work function leads to the reduction in trap sensitivity for both NRFETs in existence of acceptor and donor trap charges. The maximum sensitivity in trap are 400% and 275% for SMG and DMG NRFETs, respectively, in presence of donor trap concentration. Moreover, the trap sensitivity is very insignificant at high gate bias for donor type trap concentration with wide variation in parameters.

A Novel high-voltage DMG Fe-doped AlGaN/AlN/GaN HEMTs with sheet charge density model

In this work, two-dimensional electron gas of the dual material gate Fe doped AlGaN/AlN/GaN High Electron Mobility Transistors (HEMTs) device, sheet charge density model is demonstrated. The model is constructed by considering the electron charge in the barrier layer and the quasi triangular quantum well. This sheet charge density is calculated by Fermi-Dirac statistics by the formation of various sub energy bands and it is valid for all bias voltages. Higher carrier densities are produced and the introduction of the Fe-doped AlN layer reduces the electrons penetration to pass through the AlGaN barrier layer. The model's transcoductance variation is basically constant over an extensive variety of gate source voltages, thereby rendering it perfect regarding high-performance amplifications. The developed analytical model is demonstrated and the simulation results are validated with TCAD simulation. A good agreement is achieved with both analytical and simulation results for all of the voltages employed and device geometries.

50‐4: Invited Paper: Low‐Temperature Metal‐Oxide Thin‐Film Transistor Technology and the Realization of Electronic Systems on Flexible Substrates

A low‐temperature technology for fabricating thin‐film transistors (TFTs) is essential for the realization of electronic systems on flexible substrates. Presently reviewed are improved techniques for forming the source/drain regions and reducing the population of channel defects in a metal‐oxide TFT. These have been applied to the construction of different TFT structures, including ones with bottom gate, top gate, and dual gates. The utility of the improved 300‐°C technology has been demonstrated by the realization of a variety of electronic systems, such as a gate‐driver on array for active‐matrix displays, an analog front‐end for acquiring biopotential signals, and an artificial neural network for neuromorphic computing.