Dual-mode Power Amplifier Research Articles

Dual‐mode linearity enhanced power amplifier with wideband AM‐PM compensation for 5–6‐GHz FeLAA applications

This letter presents a 5–6-GHz dual-mode power amplifier (PA) realized for further enhanced licensed assisted access application of downlink transmission. The output matching network with multiple harmonic traps and the wideband AM-PM compensation technique are used in the design. To achieve high linear output power with less variation in the wide frequency range, different bias voltages of the first stage PA are set for dual-mode operation. In the range 5–6 GHz, the PA delivers > 30 dBm saturated output power and reaches 24.4–24.8 dBm linear power at −35 dBc adjacent channel leakage ratio.

A 6–18-GHz Switchless Reconfigurable Dual-Band Dual-Mode PA MMIC Using Coupled-Line-Based Diplexer

In this paper, a switchless dual-band, dual-mode power amplifier (PA) has been developed for multioctave operation. For the switchless dual-band operation, we proposed a new coupled-line-based diplexer structure. The proposed diplexer operates as a balun at high-band frequencies and the coupled line at low-band frequencies. To better understand the proposed diplexer structure, a detailed analysis is performed based on a coupled-line theory. The interstage and output-stage matching networks of the PA are designed by using the proposed diplexer. To maximize the power-added efficiency (PAE) of the designed PA, turn off the unused band PAs and decide the optimum off-state bias condition of transistors. The designed dual-band, dual-mode PA is fabricated with commercial 0.25- $\mu \text{m}$ GaN HEMT process. The fabricated PA shows over 15-dB small-signal gain at 5–11 GHz in the low-band mode and 9–18 GHz in the high-band mode. The measured average output power and PAE are 35 dBm, 23% in the low-band mode and 37 dBm, 26% in the high-band mode.

A <inline-formula> <tex-math notation="LaTeX">${Ka}$ </tex-math> </inline-formula>-Band Dual-Mode Power Amplifier in 65-nm CMOS Technology

In this letter, a Ka-band dual-mode power amplifier with a new topology is fabricated in 65-nm standard CMOS. The PA with the switched capacitor to modulate the output impedance to match the optimal load impedance of the operation mode provides efficiency enhancement in low-output power region and costs smaller chip size. The PA demonstrates 19.9 dBm (17 dBm) $P_{\mathrm {sat}}$ , 25.8% (22.8%) PAEmax, 17 dBm (14 dBm) OP1dB, and 14.5% (17.4%) PAE1dB at 34 GHz in the high-power (low-power) mode. The total chip size of the dual-mode PA is only 0.365 mm2, including pads.

A Fully Integrated Dual-Mode CMOS Power Amplifier With an Autotransformer-Based Parallel Combining Transformer

This letter presents a fully integrated dual-mode power amplifier (PA) with an autotransformer-based parallel combining transformer (ABPCT), fabricated with a standard 40-nm CMOS process. In comparison with a parallel combining transformer, the proposed ABPCT can offer high-efficiency performance in both high-power (HP) and low-power (LP) modes, and does so with a compact die area. With an 802.11g signal (64-QAM 54 Mbps) of 20-MHz channel bandwidth, the fully integrated dual-mode PA achieves 19.7 and 15.7 dBm average output powers with PAEs of 17.1% and 13%, in HP and LP modes, respectively, while satisfying a −25 dB error vector magnitude and spectral mask requirements. Operating the PA in the LP mode can save more than 40% of the current consumption at a 10-dBm average output power when compared with that in the HP mode.

A Fully Integrated RF CMOS Front-End IC for Connectivity Applications

A fully integrated RF CMOS front-end (FE) IC (FEIC), which is fabricated with a 0.13- $\mu\text{m}$ bulk RF CMOS process for wireless local area network/Bluetooth (WLAN/BT) applications, is presented. The proposed FEIC includes a dual-mode power amplifier (PA), integrated switches, and a shared low-noise amplifier (LNA) without external matching networks. The proposed compact reconfigurable matching network satisfies the optimum matchings for a multimode PA and a shared LNA. Measurements showed a 16.2-dBm $P_{\mathrm{OUT}}$ , with a 6.7% power-added efficiency (PAE), at −34-dB error vector magnitude, with an 802.11ac signal source, with a high-power-mode WLAN PA. With a low-power-mode BT PA, it showed a 13.7-dBm $P_{\mathrm{OUT}}$ , with a 10.9% PAE, with a 2.1+EDR signal. The shared LNA has a 14.8-dB gain and a 3.6-dB noise figure. All the measurements were carried out, including integrated mode-change switches for time-division duplex operation without any digital predistortion.

A PAPR-Aware Dual-Mode Subgigahertz CMOS Power Amplifier for Short-Range Wireless Communication

A peak-to-average power ratio (PAPR)-aware dual-mode power amplifier (PA) for short-range wireless communication in the subgigahertz band is proposed in this brief. By carefully choosing the bias, the dual-mode PA achieves the measured output P1 dB (OP1 dB) of 13.6 dBm with a PAE of 25.5%. Furthermore, a dynamic load modulation network is utilized to optimize the PA's efficiency at back-off power. A power-control loop is proposed to detect the input signal PAPR in real time and flexibly reconfigure the PA's operation modes. With these proposed techniques, the PAE has been improved by ×2.61 at 7-dB back-off power. The measurement shows that the subgigahertz-band PA archives an adjacent channel leakage ratio (ACLR1) of −37.3 dBc and an average/peak error vector magnitude of −30.4 dB/−20.5 dB at 8.9-dBm output power for ∼5-dB-PAPR 16-quadrature-magnitude-modulation LTE signals with 5-MHz bandwidth with the power control loop enabled. The PAPR-aware dual-mode PA, powered by a 2-V supply, occupies a 2.52-mm2 die area in a 180-nm CMOS.

Highly Efficient Concurrent Power Amplifier With Controllable Modes

This paper presents a controllable mode design method for a concurrent dual-mode power amplifier (PA). The principle of the controllable mode combination is proposed by investigating the characteristics of different highly efficient PA modes, which is analyzed from frequency response of the low-pass matching circuit. Then a dual-mode PA with Class- ${\bf F}^{-{\bf 1}}$ and Class-J mode is taken for example to verify this mode combination concept. A GaN device PA with 10-W output is designed at two frequency ranges of 1.9 $\sim$ 2.0 GHz and 2.3 $\sim$ 2.6 GHz. Measurement results show an output power of 40.2 $\sim$ 42.9 dBm and drain efficiency of 75.6 $\sim$ 80.3% and 76.6 $\sim$ 68.8% in two frequency bands. It also provides a broadband operation with drain efficiency of 60 $\sim$ 80.3% over 1.7 $\sim$ 2.8 GHz. To evaluate its modulated signal performance with concurrent multiband and broadband applications, dual-band signals (20 MHz $+$ 20 MHz) with 140- and 300-MHz frequency spacing and 100-MHz long-term evolution advanced (LTE-A) signals at two modes are both employed. With digital pre-distortion algorithm, adjacent channel leakage ratio lower than $-$ 47.5, $-$ 48.6 and $-$ 46.1 dBc are achieved, indicating its excellent performance in mobile communication systems.

A 60-GHz CMOS Dual-Mode Power Amplifier With Efficiency Enhancement at Low Output Power

A 60-GHz dual-mode power amplifier (PA) with efficiency enhancement at low output power in 65-nm bulk CMOS is presented. The PA consists of two cascaded common-source driver stages and one transformer-based output stage. The dual-mode output stage is reconfigured into a stacked-transistor amplifier with a 2.5-V power supply in high-power (HP) mode for high-power-handling capability and a cascode amplifier with a 1.2-V power supply in low-power (LP) mode for efficiency enhancement at low output power. The measured results show that the presented PA achieves a small-signal gain of 23.5/21.3 dB, a saturated output power value of 17.6/11.4 dBm, a 1-dB output power value of 12.5/4.7 dBm, and a peak power-added-efficiency (PAE) value of 20.4%/13.3% in the HP/LP mode at 60 GHz, respectively. The PAE at 10-dBm output power is improved by 2.8x (10.6% versus 3.8%) by utilizing the LP mode compared with the HP-mode-only PA. The total chip area is 0.68 mm × 0.35 mm, including pads.

A 0.1–5.0 GHz Reconfigurable Transmitter With Dual-Mode Power Amplifier and Digitally-Assisted Self-Calibration for Private Network Communications

A 0.1-5.0 GHz 65 nm CMOS reconfigurable transmitter for private network wireless communications is presented. The transmitter integrates a 0.1-1.5 GHz high-efficiency dual-mode power amplifier to support low-cost narrowband applications and a 0.45-5.0 GHz efficiency-optimized pre-power amplifier to support high-performance wideband applications. A wideband PLL frequency synthesizer, DACs with reconfigurable sampling rate and the reconfigurable digital baseband processing with standard JESD207 interface are all included to implement the highly-integrated transmitter. Specifically, with the proposed digitally-assisted self-calibration technique for LO leakage and image rejection, the transmitter achieves 52 dBc LO leakage and >53 dBc image rejection ratio (IRR), showing 20 dB and 30 dB improvement compared with the un-calibrated cases, respectively. The system verifications have demonstrated an EVM of 1.7% for 905 MHz EDGE with 19.5 dBm output power, and an EVM of 3.2% for LTE Band42 with 5.5 dBm output power. This proposed transmitter has achieved the comparable or even better performance in linearity, noise floor and power consumption compared with the state-of-the-art reconfigurable transmitters.

A Reconfigurable Dual-Mode CMOS Power Amplifier With Integrated T/R Switch for 0.1–1.5-GHz Multistandard Applications

A reconfigurable dual-mode power amplifier (PA) with an integrated transmit/receive (T/R) switch in 65-nm CMOS is presented. The PA can be reconfigured into linear mode or switching mode. In the linear mode, it achieves >19 dBm OP1 dB with >20% PAE over 0.1-1.5 GHz; in the switching mode, the maximum saturation output power of 23.2 dBm with the peak PAE of 60% is obtained. By utilizing the asymmetrical topology and stacked techniques, the T/R switch demonstrates ~0.5-dB TX insertion loss, >27-dB TX-RX isolation, and 24.8 dBm IP1 dB across 0.1-1.5 GHz. This brief proposes, for the first time, a CMOS dual-mode PA with an integrated T/R switch for multistandard applications.

A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS

A 60-GHz dual-mode power amplifier (PA) is implemented in 40-nm bulk CMOS technology. To boost the amplifier performance at millimeter-wave (mmWave) frequencies, a new transistor layout is proposed to minimize the device and interconnect parasitics while the neutralized amplifier stage is co-optimized with input transformer to improve the power gain and stability. The transformer-based power-combining PA consists of two unit amplifiers, operating in Class AB for better back-off efficiency. To further reduce the power consumption and hence extend battery lifetime, one unit PA is tuned off in low-power mode. A switch is used to short the output of this non-operating unit PA to reduce the combiner loss and improve the efficiency. The PA achieves a measured saturated output power (PSAT) of 17.0 dBm (12.1 dBm) and 1-dB compressed power (P1dB) of 13.8 dBm (9.1 dBm) in the high-power (low-power) mode. The power-added efficiencies (PAEs) at PSAT and P1dB are 30.3% and 21.6% respectively for the high-power mode. Compared to Class A, the PA operating in Class AB shows 5.3% improvement in measured PAE at P1dB with no compromise in linearity. The PA with the power combiner only occupies an active area of 0.074 mm 2. The reliability measurements are also conducted and the PA has an estimated lifetime of 80613 hours.

A Dual-Mode CMOS RF Power Amplifier With Integrated Tunable Matching Network

A dual-mode CMOS power amplifier (PA) with an integrated tunable matching network is presented. A switched capacitor is fully analyzed to implement a tunable matching network in terms of power-handling capability, tuning ratio, quality factor, and linearity. Based on the presented consideration, a 3.3-V 2.4-GHz fully integrated CMOS dual-mode PA is implemented in a 0.18-μm CMOS process. The PA has two power modes, high-power and low-power (LP), and each mode is optimally matched by the tunable matching network. The LP mode enables more than 50% dc current reduction from 0- to 10-dBm power range. The improved efficiency in this study is approximately twice that of other multimode CMOS PAs reported thus far.

A Dual-Mode Power Amplifier With On-Chip Switch Bias Control Circuits for LTE Handsets

In this brief, we present a dual-mode (high and low) power amplifier (PA) for fourth-generation long-term evolution (LTE) handset applications using a device switching technique to improve the efficiency at low output power. In particular, the effects of the gate voltage variation of the input and output switches on the amplifier performances are described. In addition, a bias control circuit for a dual-mode PA, which can provide the correct voltage to the input and output switches and can be effectively controlled by the mode control voltage, is also proposed. The bias control circuit, the mode switch, and the PA are implemented with the integrated pseudomorphic high-electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) technology on the same chip (i.e., bipolar field effect transistor process). A dual-mode PA with a gain of 27.2 dB, PAE of 34.5%, a ACLRE-UTRA value of -31.2 dBc, and error vector magnitude (EVM) of 2.97% has been achieved in high-power mode; whereas a 22 dB of gain, PAE of 19%, a ACLRE-UTRA value of -31.6 dBc and EVM of 2.84% were measured in the low-power mode with LTE uplink signals.

Efficiency enhancement of RF power amplifier using reconfigurable power dividers

A reconfigurable power divider is proposed using coupled lines and switches. It routes the input signal to one of two outputs with low insertion loss and good impedance matching. The proposed power divider is applied to a dual-mode power amplifier (PA). Measurement at 900 MHz shows that the efficiency of the PA can be greatly improved at low input powers thanks to the developed reconfigurable power dividers.

A 3-V monolithic SiGe HBT power amplifier for dual-mode (CDMA/AMPS) cellular handset applications

A dual-mode (CDMA/AMPS) power amplifier has been successfully implemented by using a monolithic SiGe/Si heterojunction bipolar transistor (HBT) foundry process for cellular handset (824-849 MHz) applications. The designed two-stage power amplifier satisfies both CDMA and AMPS requirements in output power, linearity, and efficiency. At V/sub cc/=3 V,the power amplifier shows an excellent linearity (first ACPR<-44.1 dBc and second ACPR<-57.1 dBc) up to 28 dBm of output power for CDMA applications. Under the same bias condition, the power amplifier also meets AMPS handset requirements in output power (up to 31 dBm) and linearity (with second and third harmonic to fundamental ratios lower than -37 dBc and -55 dBc, respectively). At the maximum output power level, the worst power-added efficiencies (PAEs) are measured to be 36% for CDMA and 49% for AMPS operations. The power amplifier also tolerates severe output mismatch (VSWR>12:1) up to V/sub cc/=4 V, with spurs measured to be <-22 dBc in CDMA outputs at two specific tuning angles, but with no spur in AMPS outputs at any tuning angle.