Dual Insulator Research Articles

Analytical modeling of Ni–Co based multilayer bimorph actuators involving dual insulation layers

This paper proposes a new design of multilayered bimorph electrothermal actuators based on a Ni and Co alloy (Ni–Co) substrate and analytical models to estimate their performance. The proposed bimorph actuator consists of a flexible Ni–Co substrate having high coefficient of thermal expansion (CTE) along with two insulation (low-CTE materials) and Pt heater layers. A multilayered thermo-mechanical model to estimate the tip deflection was derived based on Timoshenko’s classical model for metal bilayers. An analytical model based on the Euler–Bernoulli beam theory was also derived to calculate the blocking force of the multilayered actuators. An appropriate layer composition of the low-CTE layers was derived based on the analytical models and lattice parameters of the adjacent layers: the performance of the bimorph actuator was significantly improved when the low-CTE layers are composed of a dual layer instead of a single layer of SiO2. The analytical solutions of the simplified 3D models were then compared with finite element analysis (FEA) and experimental results. In the comparison of the tip deflection, the analytical solution of the three-layer actuator omitting the Pt heater was similar to the FEA result and the experimental result compensating for the initial dead zone. In the comparison of the blocking force, the analytical solution was also similar to the FEA results, though there was a deviation from the experimental results. Abnormal behavior of the actuator was observed in the experimental result of the blocking force, and the cause was investigated in this study.

Analytical Modeling of Ni–Co Based Multilayer Bimorph Actuators Involving Dual Insulation Layers

Analytical Modeling of Ni–Co Based Multilayer Bimorph Actuators Involving Dual Insulation Layers

Strain-relaxed GeSn-on-insulator (GeSnOI) microdisks

GeSn alloys offer a promising route towards a CMOS compatible light source and the realization of electronic-photonic integrated circuits. One tactic to improve the lasing performance of GeSn lasers is to use a high Sn content, which improves the directness. Another popular approach is to use a low to moderate Sn content with either compressive strain relaxation or tensile strain engineering, but these strain engineering techniques generally require optical cavities to be suspended in air, which leads to poor thermal management. In this work, we develop a novel dual insulator GeSn-on-insulator (GeSnOI) material platform that is used to produce strain-relaxed GeSn microdisks stuck on a substrate. By undercutting only one insulating layer (i.e., Al2O3), we fabricate microdisks sitting on SiO2, which attain three key properties for a high-performance GeSn laser: removal of harmful compressive strain, decent thermal management, and excellent optical confinement. We believe that an increase in the Sn content of GeSn layers on our platform can allow us to achieve improved lasing performance.

이중절연 정전흡착 패드를 활용한 로봇 구동

이중절연 정전흡착 패드를 활용한 로봇 구동

Strained Ge Light Emitter with Ge on Dual Insulators for Improved Thermal Conduction and Optical Insulation

We present a new way to create a thermally stable, highly strained germanium (Ge) optical resonator using a novel Ge-on-dual-insulators substrate. Instead of using a conventional way to undercut the oxide layer of a Ge-on-single-insulator substrate for inducing tensile strain in germanium, we use thin aluminum oxide as a sacrificial layer. By eliminating the air gap underneath the active germanium layer, we achieve an optically insulating, thermally conductive, and highly strained Ge resonator structure that is critical for a practical germanium laser. Using Raman spectroscopy and photoluminescence experiments, we prove that the novel geometry of our Ge resonator structure provides a significant improvement in thermal stability while maintaining good optical confinement.

Impact of HfO<SUB>2</SUB> in Graded Channel Dual Insulator Double Gate MOSFET

Impact of HfO<SUB>2</SUB> in Graded Channel Dual Insulator Double Gate MOSFET

Some Device Design Considerations to Enhance the Performance of DG-MOSFETs

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current (<TEX>$I_{off}$</TEX>), on current (<TEX>$I_{on}$</TEX>), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

Electric field computation of composite line insulators up to 1200 kV AC

Satisfactory operation of composite insulators is intimately related to the surface electric field (stress) distribution. This paper presents results of calculation of the electric field distribution for composite insulators up to 1200 kV, using a 3D software package based on the Boundary Element Method. The impact of corona and grading rings, single and bundled conductors, insulator orientation (dead-end and suspension), single and double units, and surface condition (dry and wet) on the electric field distribution has been analyzed. For UHV systems (higher than 750 kV ac) the use of dual insulators with individual corona rings at the line and ground end and a common grading ring at the line end is beneficial. The existence of optimal dimensions of corona and grading arrangement has been illustrated on a 1000 kV insulator string. It was found that the dead end insulators experience higher electric stress when compared to their suspension counterparts and this difference gets more prominent as the system voltage increases.

Poly(3-hexylthiophene) Thin-Film Transistors with Dual insulator Layers

Poly(3-hexylthiophene) thin-film transistors with anodized high-dielectric constant (κ) tantalum pentoxide (Ta2O5) and spin-coated poly(4-vinylphenol) (PVP) film dual insulator layers were demonstrated. The polymeric PVP layer covering the Ta2O5 can considerably improve the transistor performance. The mobility was increased up to 3.07×10-2 cm2/(V·s), which is much higher than that obtained by only using a PVP or Ta2O5 single dielectric layer. The threshold voltage of the dual-insulator device was as low as 1.7 V, because the Ta2O5 insulator possesses a high-dielectric constant.

Fabrication of silicon-on-SiO2/diamondlike-carbon dual insulator using ion cutting and mitigation of self-heating effects

A diamondlike-carbon (DLC) layer was used to substitute for the buried SiO2 layer in silicon on insulator (SOI) to mitigate the self-heating effects in our previous study. However, we discovered drawbacks associated with the inferior Si/DLC interface, inadequate thermal stability as well as carbon-silicon interdiffusion at the Si/DLC interface that could hamper future application of this silicon-on-diamond structure to microelectronic devices. In this work, we introduced a silicon dioxide barrier layer between the Si film and DLC buried layer to form a silicon-on-SiO2∕DLC dual-insulator structure to tackle these problems. Cross-sectional high-resolution transmission electron microscopy reveals that the Si/insulator interface is atomically flat and the top Si layer has nearly perfect crystalline quality. The SiO2∕DLC dual-insulator layer retains excellent insulating properties at typical complementary metal oxide silicon processing temperatures. Numerical simulation reveals that the negative differential resistance and channel temperature are significantly reduced compared with those of the same metal oxide semiconductor field effect transistors fabricated in conventional SiO2-based SOI, suggesting that the silicon-on-dual-insulator structure can alleviate the self-heating penalty effectively.

Charge storage characteristics of MIS structures employing dual-insulator composites of HfO2–SiO2 and SrTiO3–SiO2

Two MIS versions have been fabricated employing rf-sputtered dual insulator structures comprised of 1000 Å HfO2-20 Å SiO2 and 1000 Å SrTiO3-20 Å SiO2. The high-dielectric-constant insulators in combination with a 20-Å layer of silicon dioxide permit the transfer of charge by tunneling into traps at the dual-insulator interface to occur at considerably lower voltages than comparable structures employing silicon nitride or aluminum oxide. It was found that trap density and, hence, the degree of flat-band voltage shift could be altered by sputtering 50-Å layers of selected materials at the insulator-SiO2 interface. The devices employing hafnium dioxide show promise in an application as a nonvolatile electrically alterable memory element. Although the strontium titanate devices exhibit a low threshold voltage for onset of charge transfer, the charge retention characteristics are poor.