Dual-gate Thin-film Transistors Research Articles

Oxide semiconductor thin-film transistors with nano-splitting and field-surrounding channels fabricated by subwavelength photolithography

Oxide semiconductors feature high tunability of carrier concentrations under the control of electric field. In thin film transistors (TFTs), applying dual gate has been reported to be efficient in enhancing the coupling between the gate field and the channel accumulation. In this work, we demonstrate nano-splitting and field-surrounding semiconducting channels (based on InGaZnO) in TFTs, which is fabricated by facile subwavelength photolithography. In such TFTs, semiconducting channels have 200 nm gaps parallel to the drain field, are wrapped by oxide insulators and thus the gate field. The devices show enhanced performance as compared with dual-gate and single gate TFTs, exhibiting higher drain current and steeper subthreshold swing. The maximum transconductance gm is 27.9% higher than dual gate TFT and 73.1% higher than single gate TFT. According to device simulation, the improvement of the wrapping insulators device correlates with the three-dimensional accumulation of carriers and increased gate electric field near the semiconductor-dielectric interface. These surrounded-channel effects become noticeable in the device with the gap distance less than 1 μm, with gate electric field squeezing in the submicron gaps. The proposed approach offers an alternative way to take advantage of the oxide semiconductors and their application in TFTs with related circuits.

Early stage detection of Staphylococcus epidermidis biofilm formation using MgZnO dual-gate TFT biosensor

Early stage detection of biofilm formation is an important aspect of microbial research because once formed, biofilms show serious tolerance to antibiotics in contrast to the free-floating bacteria, which significantly increases the difficulty for clinical treatment of bacterial infections. The early stage detection technology is desired to improve the efficiency of medical treatments. In this work, we present a biosensor consisting of a magnesium zinc oxide (MZO) dual gate thin-film transistor (DGTFT) as the actuator and an MZO nanostructure (MZOnano) array coated conducting pad as the extended sensing gate for the early stage detection of Staphylococcus epidermidis (S. epidermidis) biofilm formation. S. epidermidis bacteria were cultured in vitro on the nanostructure modified sensing pad. Charge transfer occurs between microbial cells and the MZOnano during the initial bacterial adhesion stage. Such electrical signals, which represent the onset of biofilm formation, were dynamically detected by the DGTFT where the top gate electrode was connected to the extended MZOnano sensing pad and the bottom gate was used for biasing the device into the optimum characteristic region for high sensitivity and stable operation. The testing results show that a current change of ~80% is achieved after ~200 min of bacterial culturing. A crystal violet staining-based assay shows that tiny bacterial microcolonies just start to form at 200 min, and that it would take approximately 24 h to form matured biofilms. This technology enables medical professionals to act promptly on bacterial infection before biofilms get fully established.

Junctionless Dual In-Plane-Gate Thin-Film Transistors with AND Logic Function on Paper Substrates.

Dual-gate thin-film transistors (DGTFTs) have attracted increasing attention in the past few years because of threshold voltage modulation and device logic functionality. Here, solution-processed chitosan-based proton conductors are used as the gate dielectric. The threshold voltage shift depends on the ratio of the capacitances of the two gate dielectrics. The second interesting application of DGTFTs is logic functionality. This device demonstrates AND logic function controlled by applying either 0 or −1 V to each of the gate electrodes. When both gates were simultaneously applied to be 0 V, the current flows (ON). Otherwise, the current is blocked (OFF). In order to provide a comprehensive overview of these paper devices, the planarization of paper surface and switching stability of such DGTFTs are all discussed.

Static and Dynamic Response Comparison of Printed, Single- and Dual-Gate 3-D Complementary Organic TFT Inverters

A dual-gate configuration has been introduced to organic thin-film transistors (TFTs) for full-depletion behavior to enhance the transconductance, subthreshold slope, and drain current on–off ratio. In this letter, we show how those dual-gate effects influence the static and dynamic responses of three-dimensional (3-D) complementary organic logic gates in comparison to their single-gate counterpart. For the comparative study, 3-D inverters and ring oscillators were fabricated by printing directly on plastic foil in both single- and dual-gate configurations. In the static inverter operation, the fully depleted characteristics of the dual-gate TFTs lead to an increase in voltage gain and a dramatic decrease in standby power consumption. In the dynamic ring oscillator operation, the two configurations have comparable gate delays because the use of an additional gate increases not only the drain current but also the load input gate capacitance. Our findings demonstrate the performance of an inverter that can represent the overall operation of complementary logic gates consisting of pull-up and pull-down networks, thereby providing significant insight into the printed organic TFT circuit design using dual gating effects.

Bistaggered Contact Geometry for Symmetric Dual-Gate Organic TFTs

This transaction proposes a symmetric bistaggered dual-gate organic thin-film transistor (TFT) to minimize the difference between the top and bottom channel current characteristics and demonstrates it through experiment and 2-D simulation. In dual-gate organic TFTs, asymmetric top and bottom channel currents are mainly a result of their asymmetric contact geometry. To address this geometric limitation, the contact electrodes were sandwiched between the two organic semiconductor layers to be placed in a staggered position to both top and bottom gates. Two-way current crowding at the bistaggered contact electrodes leads to high-charge injection efficiency in both channels.

Temperature-dependent Electrical Characterization of Single and Dual-gate Flexible Carbon Nanotube Thin Film Transistors

Dual-gate carbon nanotube thin film transistors (CNTTFTs) with hafnium dioxide (HfO2) and silicon dioxide (SiO2) as gate dielectrics and single-gate CNTTFTs of two types both of bottom-gate structure but one with HfO2 as gate dielectric and another with SiO2 as gate dielectric were fabricated on a flexible polyimide substrate using a scalable process. Electrical characteristics of the fabricated devices at elevated temperatures varying from 25 to 120°C were investigated and compared. Both single and dual-gate flexible devices have exhibited p-type characteristics. As the temperature was raised the on-current, off current, subthreshold swing, transconductance and drain conductance of both single and dual-gate devices increased whereas on–off current-ratio and threshold voltages decreased. The devices exhibited deterioration in transconductance and on-current with the increase of channel lengths. The present work illustrates that dual-gate flexible CNTTFTs outperform the single-gate flexible CNTTFTs in all electrical characteristic parameters and have shown the highest gate control over the channel at different temperatures varying from 25 to 120°C. The performance variations of both single and dual-gate flexible devices were less than 3.1% till the temperature of 50°C and were operational as CNTTFTs at temperatures varying from 25 to 120°C. The on–off current ratio, subthreshold swing, and threshold voltages deteriorate highly at temperatures higher than 120°C and also it was investigated that electrical characteristics were not repeatable at temperatures higher than 120°C. The CNTTFTs on the flexible substrate can be used for flexible electronics applications till 120°C.

Drain bias and position dependent performance degradation of dual-gate poly-Si TFTs with undoped region offsets

In this paper, electrical characteristics of dual-gate polycrystalline silicon (poly-Si) thin film transistors (TFTs) with different undoped region (UR) offsets are investigated. Performance degradation of the poly-Si TFT is dependent on the offset value, offset direction, and offset location. In addition, the degradation is also dependent on the applied drain bias. Significant performance deterioration is observed when the offset is larger than ±0.4 μm. Even an offset in an individual UR can cause the degradation. At a low drain bias of −0.1 V, the degradation is independent on the direction and the location of the offset. When the drain bias increases to −10 V, the performance degradation of the TFT with the positive UR offset significantly reduces. The physical mechanisms underlying the performance variation are studied by analyzing the energy band diagrams, carrier concentration distributions, and electric field distributions.

Effects of Ultraviolet Light on the Dual-Sweep <inline-formula> <tex-math notation="LaTeX">$I$ </tex-math> </inline-formula>–<inline-formula> <tex-math notation="LaTeX">$V$ </tex-math> </inline-formula> Curve of a-InGaZnO4 Thin-Film Transistor

The instability of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under ultraviolet (UV) light was thoroughly investigated in this paper. Unlike in a darkened state, an off-state leakage current can be found in the dual-sweep I–V transfer curve of a-IGZO TFTs under UV light illumination. Furthermore, despite the same UV light condition, the forward sweep and reverse sweep show different I–V curves, representing two different physical mechanisms. First, the subthreshold swing degradation and threshold voltage shift to the negative direction in the forward sweep are due to the total channel barrier lowering and can be confirmed by changing the light exposure region. Second, in the reverse sweep, the suggested back-channel leakage current can be controlled by dual-gate TFTs. UV light exposure of the metal–insulator–semiconductor–metal structure verifies that the off-state leakage current passes through the back channel in a reverse sweep. Finally, the physical mechanism links between forward and reverse sweeps have comprehensive interpretation in this paper.

A High Performance Operational Amplifier Using Coplanar Dual Gate a-IGZO TFTs

We fabricate an operational amplifier (op-amp) composed with the coplanar amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs). The circuit consisted of 19-TFTs and designed on a glass substrate in both dual gate (DG) and single gate (SG) structure for performance evaluation. Having the yield of a total voltage gain ( $A_{v}$ ) of 23.5 dB, a cutoff frequency ( $f_{c}$ ) of 500 kHz, a unit gain frequency ( $f_{\mathrm{ ug}}$ ) of 2.37 MHz, gain-bandwidth product (GBWP) of 7500 kHz, a slew rate (up/down) of (2.1/1.2) V/ $\mu \text{s}$ , and a phase margin (PM) of 102° at a supply voltage of ±10 V, the fabricated DG TFT op-amp demonstrates good performance among all a-IGZO-based literature.

Fully Printed Flexible Dual-Gate Carbon Nanotube Thin-Film Transistors with Tunable Ambipolar Characteristics for Complementary Logic Circuits

Semiconducting single-wall carbon nanotubes (sSWCNTs) have been widely used as the channel material for high-performance printed flexible thin-film transistors (TFTs). Due to the absorption of moisture and oxygen in air, the printed sSWCNT TFTs generally exhibit p-type characteristics only. In this paper, we report fully printed dual-gate sSWCNT TFTs that exhibit almost symmetric ambipolar characteristics. With the applied control gate voltage varying from -60 to +60 V, a threshold voltage tuning range of 27 V is achieved, allowing the device to be effectively tuned into either predominantly p-type or predominantly n-type. The tunable ambipolar characteristics are found to be very stable over a long period of time (4 months). By integrating two printed dual-gate TFTs biased with different control gate voltages, a complementary metal oxide semiconductor inverter with close to rail-to-rail output voltage swing is demonstrated. The use of a dual-gate structure for achieving n-type printed carbon nanotube TFTs is much more controllable and repeatable compared to other methods such as chemical doping. Our work shows the feasibility of implementing more sophisticated complementary logic circuits using printed flexible carbon nanotube transistors.

A Wearable Self-Driven Impulse Sensor Based on a Mechanical-Field-Coupled Thin-Film Transistor

This letter reports on an electronic device that works as a self-driven impulse sensor with high sensitivity and ultra-low power consumption. It consists of a mechanical-field-coupled thin-film transistor (TFT) formed by integrating a piezoelectric transducer with a 3-D FIN-shaped dual-gate TFT. An analytical model is presented to intricate the variation of output current in the response of the human impulse force, and an experimental study is conducted to evaluate its sensitivity and capability of acquiring impulse waveforms as well as heart rate. The proposed impulse sensor is anticipated to be pragmatic in wearable medical devices for prevention against cardiovascular abnormalities, both continuously and non-invasively.

Vertical ITO/SiOX/a-Si:H Photodiode-Gated Low-Temperature Polycrystalline Silicon Thin-Film Transistor Intended for In-Display Fingerprint Imaging Applications

To embed an active pixel optical sensor in a display pixel for fingerprint imaging, an area-efficient and vertical ITO/SiOX/a-Si:H photodiode-gated low-temperature polycrystalline silicon dual-gate thin-film transistor with controllable photosensitivity is proposed and experimentally demonstrated. The device can be operated as a driving switch to the display pixel, and the driving current is insensitive to normal ambient light; the device can also be operated as an optical sensor, which provides 8 bits of effective data and reasonable detectable intensity range. The compact structure and dual-mode operation make it a promising solution to in-display, large-area fingerprint identification for smartphones.

Reduced Mechanical Strain in Bendable a-IGZO TFTs Under Dual-Gate Driving

We report the reduced strain in bendable amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) with dual-gate (DG) driving. The performance of the fabricated TFTs on a 15- $\mu \text{m}$ polyimide substrate are sensitive to bending radius and the changes in threshold voltage ( $\Delta \mathrm {V}_{\mathrm {TH}}$ ) fits well by analytical modeling. DG driving TFTs are found very stable under tensile strain ( $\varepsilon$ ) compared with single-gate (SG) TFTs. Technology computer-aided design strain distribution confirms a 25% less strain on a-IGZO layer for DG TFT structure compared with SG TFT and the maximum tensile strain is observed at the center of the TFT channel. The SG and DG TFTs under 1 mm radius exhibit $\Delta \mathrm {V}_{\mathrm {TH}}$ (V) shift of −1.5 and −0.3 V, respectively, from the flat state, which is due to the reduced strain in the DG TFT.

A Wearable Piezoelectric Energy Harvester Rectified by a Dual-Gate Thin-Film Transistor

This paper addresses a wearable piezoelectric energy harvester that combines a PVDF piezoelectric charge generator with an a-Si:H dual-gate thin-film transistor as a rectifier. An analytical model and equivalent circuit elaborate their working principle and device physics. A preliminary experimental study proves the device concept and demonstrates that such a harvester is capable of generating microwatt-range power with a simple 90° finger bending action. Coupled with low-cost and large-area fabrication processes, a pixelated energy-harvesting array can be potentially achievable, making it a promising alternative to energy sources for wearable electronics.

3-D Dual-Gate Photosensitive Thin-Film Transistor Architectures Based on Amorphous Silicon

In contrast to the conventional planar p-i-n photodiode and a metal-semiconductor–metal photodetector, the 3-D dual-gate photosensitive thin-film transistor (TFT) architectures presented here attain excellent photoresponse characteristics. Operating the device in the subthreshold regime further boosts the photoconductive gain as a result of light-induced decrease in the threshold voltage. This paper presents design considerations along with a performance comparison between 3-D photosensitive TFTs that have $\pi $ - and FIN-shaped channels and conventional TFT with a planar channel. Our paper shows that the $\pi $ -shaped structure tends to have a higher sensitivity while the FIN-shaped counterpart is more responsive with wider dynamic range. For both structures, a measured photoconductive gain of $10^{\textsf {4}} \sim 10^{\textsf {6}}$ % is obtained with spectral responsivity ranging from near UV to near IR, and the photoresponse time in the range of tens of milliseconds. The 3-D dual-gate photosensitive TFT architecture appears to be very promising for large-area, low-level UV, visible, and IR detection applications.

Stability of double gate amorphous In–Ga–Zn–O thin-film transistors with various top gate designs

Electrical characteristics of the dual-gate amorphous indium gallium zinc oxide thin-film transistors have been studied. Compared with the traditional bottom gate thin film transistor, the dual-gate structure has a larger on-current and a smaller threshold voltage shift because of the formation of an additional carrier channel and the depletion of the semiconductor layer. The top gate-to-channel barrier height is critical to threshold voltage and the stability of the thin film transistor. The complete overlap between the top gate and the channel region is important for the top channel function, which warrants the large on-current and low threshold slope shift. Therefore, the top gate design is critical to the performance and stability of the dual-gate thin film transistor.

Piezoelectric Pressure Sensing Device Using Top-Gate Effect of Dual-Gate a-IGZO TFT

We propose a pressure sensor composed of single-gate and dual-gate amorphous-indium-gallium-zinc-oxide thin-film transistors (TFTs) that are integrated with a P(VDF-TrFE)/PZT composite piezo-capacitor. The TFTs are connected in an inverter configuration, where the piezo-capacitor is connected to the floating top-gate of the dual-gate TFT (driving TFT). When the pressure is applied by finger pressing, the potential of the top-gate changes, and thus, the threshold voltage of the driving TFT shifts, leading to the generation of an output signal that is typically in the range of 200-300 mV.

Fast Threshold Voltage Compensation AMOLED Pixel Circuit Using Secondary Gate Effect of Dual Gate a-IGZO TFTs

We report a fast threshold voltage ( $\text{V}_\mathrm {TH})$ compensation pixel circuit for active-matrix organic light-emitting diode displays. The circuit utilizes the secondary gate effect in amorphous-indium-gallium-zinc-oxide thin-film transistors (TFTs) with the dual-gate (DG) (bottom and top gate) structure and consists of three single-gate TFTs, one DG driving TFT, and two capacitors. It compensates the initial $\text{V}_{\mathrm {TH}}$ variation after fabrication and takes into account the carrier mobility differences between the top and bottom channels of a DG TFT by using a correction TFT that enables $\text{V}_\mathrm {TH}$ sampling via the channel with the higher mobility, the bottom channel. This achieves very short $\text{V}_\mathrm {TH}$ sampling time, below $10~\mu \text{s}$ . Experimental results are consistent with those from Silvaco SmartSpice simulations.

Highly Photosensitive Dual-Gate a-Si:H TFT and Array for Low-Dose Flat-Panel X-Ray Imaging

Amorphous silicon thin-film transistors (TFTs) have been widely used to build flat-panel X-ray detectors for medical imaging. To meet the growing demand for low dose and high sensitivity, attention has been paid to active pixel sensor (APS) with high signal-to-noise-ratio (SNR). However, most APS architectures generally require multiple TFTs in one pixel, resulting in low fill factor, low spatial resolution, and discounted SNR. We proposed a smart pixel architecture based on a dual-gate photosensitive TFT that combines sensor, switch, and storage into one TFT intended for high fill factor, high spatial resolution, and high SNR. This letter aims to investigate the sensitivity and noise performance of the smart pixel along with the evaluation of the first $4\times 4$ smart pixel sensor array.

One Gate Diode-Connected Dual-Gate a-IGZO TFT Driven Pixel Circuit for Active Matrix Organic Light-Emitting Diode Displays

A dual-gate (DG) amorphous indium–gallium–zinc-oxide thin-film transistor (TFT)-driven pixel circuit for active-matrix organic light-emitting diode displays is presented. One gate of the DGs serves as a primary gate (PG) and the other as an auxiliary gate (AG). The threshold voltage ( $V_{\mathrm {{TH}}}$ ) of the DG TFT under the PG operation is modulated by the AG bias voltage. The $V_{\mathrm {{TH}}}$ variation ( $\Delta V_{\mathrm {{TH}}}$ ) is compensated with the AG and the drain diode-connected structure. The validity of the presented pixel circuit is experimentally verified. The measured current error rates are less than 3.2% at a $\Delta V_{\mathrm {{TH}}}$ of $\text {TFT} = \pm 0.5$ V and a $\Delta V_{\mathrm {{TH}}}$ of OLED = 0.5 V with the emission current ranging from 7 nA to $1.13~\mu \text{A}$ .