DSP Applications Research Articles

Approximate Multiplication and Division Calculation for DSP Applications

Digital signal processing (DSP) is a promising alternative to accomplish a wide variety of signal processing operations. Multiplications and divisions have been urgently proposed to perform different DSP operations in real-time applications. However, the design and implementation of multiplication and division calculations have some limitations such as strict timing, bounded power consumption, and higher accuracy. The exact execution of these complex operations consumes great hardware resources and power consumption. Approximate computation for the main and complex arithmetic functions is a demand solution to decrease power, area, and delay. In this paper, low-power and high-accuracy approximate multiplication and division processes have been implemented using a 90 nm CMOS process, 1.0 V supply voltage standard cell library. The approximate multiplication and division algorithm depends on enhanced logarithmic converters. The logarithm-based arithmetic exhibits a good performance with decreasing the used hardware resources and runs at a higher speed. The proposed scheme achieves less hardware with minimal power consumption. The proposed approximate structure demonstrates up to a 62% saving in power with a rise in the accuracy level as compared with the prior approximate works. At the same time, the proposed multiplier and divider can carry out the multiplication and division processes in 1.8 ns, respectively.

A novel reduced local search algorithm for optimization of digital filter coefficients

Digital Filtering is an important operation in DSP. Most of the DSP applications demand low power implementations. In CMOS digital circuits, switching from logic 0 to logic 1 and vice-versa decides the dynamic power consumption. This paper proposes and develops a novel algorithm based on mixed integer linear programming to minimize the number of ones (filter cost) in filter coefficients, which in turn minimizes the switching factor of CMOS circuits and the number of additional adders needed for hardware implementation. The search space for finding the optimal value of the coefficient is reduced thereby increasing the speed of execution of the algorithm. The average reduction of 18.02 % in the number of transitions is obtained with the proposed algorithm. The suggested technique results in an 18.72 % decrease in the typical price of digital filters. Also the proposed algorithm works faster than the previously proposed algorithm used for finding the optimized coefficients.

High-performance power spectral/bispectral estimator for biomedical signal processing applications using novel memory-based FFT processor

This research paper proposes a novel robust high-performance power spectrum estimator, and bispactral power density analyzer that has outstanding capabilities in estimating noisy biomedical signal's power spectrum, and bispectrum. Biomedical signals usually are exposed to several sources of noises such as electrical noise from environmental noise from external sources, electrical equipment, and biological noise from the body. Therefore, accuracy and reliability are the most important feature of these systems in processing non-stationary biomedical signals. The proposed computationally-efficient architecture is based on a radix-8 memory-based 1024-point Blackman-Tuckey method power spectral density (PSD) estimator. The proposed nonparametric estimator uses a novel shared-resource CORDIC-Ⅱ unit to avoid multiplications in FFT computation, as well as filtering operations implemented in folded architectures. In order to merge two FFTs, the module uses bidirectional fractional delay filters to estimate half delay samples. By using modified safe-scaling, valid final output would be achieved, without any averaging operation. The proposed and competing designs are implemented on Artix-7 FPGA which is an ideal option for DSP applications. As final results demonstrate, the hardware has a remarkable capability in operating in short word-lengths which allows high-performance in low-power applications to compute the power spectrum and bicoherence of a vital signal.

Approximate Square and Square Root Calculation without Multiplication or Division for DSP Applications

Approximate Square and Square Root Calculation without Multiplication or Division for DSP Applications

Analisis Aplikasi Dana Siap Pakai (DSP) dengan Metode Pieces pada Badan Nasional Penanggulangan Bencana

The submission of requests for Ready Use Fund Assistance (DSP) by the Regional Disaster Management Agency (BPBD) to the National Disaster Management Agency (BNPB) continues to increase along with the number of disaster events. The web-based DSP Application System used by BNPB to manage DSP request documents is no longer in accordance with the current needs of the organization. This study uses the PIECES analysis method which can be considered in developing an information system, in PIECES there are 6 (six) aspects used in analyzing an application or information system, namely Performance, Information, Economic, Control, Efficiency, Service (PIECES), where in each aspect a method and provisions are needed in conducting assessments. The results of the analysis using the PIECES method show that the DSP application has shortcomings in every aspect, the results of the PIECES analysis can be used as a basis for improving the DSP application to meet the needs of users and organizations

Low-Power Approximate Unsigned and Signed Multipliers with Configurable Error Recovery

In the field of Digital Signal Processing and similar applications, Approximate circuits are being explored as a means to enhance performance and energy efficiency by sacrificing a degree of accuracy. Within these circuits, Multipliers play a crucial role and are being investigated for their potential impact on overall system optimization. In this paper, a novel approximate multiplier with a low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbours for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery. The multipliers using these two error reduction strategies are referred to as Approximate Multiplier 1 (AM1) and Approximate Multiplier 2 (AM2), respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Unsigned multiplication multiplier, with the signed multiplication. The signed multiplication tends to have lower power consumption is observed. By utilizing an appropriate error recovery, the proposed approximate multipliers achieve similar processing accuracy as traditional exact multipliers, but with significant improvements in power.

Energy efficient approximate multipliers compatible with error-tolerant application

Multipliers are one of the most commonly used parts in a system, responsible for performing computations, while significantly contributing to power consumption. In this article, by removing the least significant bits, a new architecture is presented to implement 3 multipliers (Mul-1, Mul-2 and Mul-3), in order to reduce complexity and power consumption. Compared to the previous works, Mul-1 has the most accuracy in addition to its low energy consumption, therefore, it has been able to deliver a good trade-off between accuracy and energy consumption. All proposed designs and existing multipliers have been simulated and compared in 7 nm FinFET technology using Hspice tool. Moreover, the accuracy and quality of the proposed approximate multipliers are also evaluated using MATLAB. The results show that Mul-1 and Mul-3 are very efficient in image processing applications. According to the results, Mul-1 outperforms its counterpart by 10%, 50% and 50% in PDP, NMED and MRED, respectively. Furthermore, Mul-3 has satisfactory MSSIM in DSP applications and is better than its counterpart by 23% and 16% in PDP and MRED. Meanwhile, Mul-2 improves PDP by nearly 53% compared to Mul-1 and has the lowest power consumption.

“DSP原理及应用”课程教学改革探索

“DSP原理及应用”课程教学改革探索

High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications

High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications

Design and Implementation of Hybrid Multiplier for DSP Applications

In recent decades, there has been a consistent reduction in feature sizes in integrated circuit (IC) technology, leading to the need for increased placement of functional circuits on each chip. When it comes to the design of digital circuits, there is a significant focus on hybrid logic. Hybrid logic is highly regarded due to its ability to consume less power while achieving higher efficiency. Hybrid logic circuits have similarities to complementary metal-oxide-semiconductor (CMOS) transistors, yet possess a reduced transistor count while offering enhanced performance and reliability capabilities. This study examines the modeling and implementation hybrid multiplier with of help of hybrid adder. The functionality of adder is determined with the help of hybrid logic producing XOR/XNOR functionalities in single circuit. The proposed hybrid Multiplier, which incorporates a hybrid Adder, has been successfully designed and implemented using CMOS 45nm technology and Mentor Graphics software the hybrid transistor logic multiplier demonstrates a decrease in total delay of 60% compared to CMOS.

Analysis and application of key technologies in digital signal processing

With the uncreasing reform of times and the continuous advancement of my science and technology, in recent years, my overall national strength is strengthening gradually. I have entered an information age, one digital age, the use of digital signal processing is becoming more and more frequent and important. Therefore, this paper mainly analyzes the application of DSP, the digital signal processing technology show to make the exposition. Digitalization is a major trend in today's society and the main theme of the development of the times, while digital signal processor is a component born with the times. The so-called digital signal processing is to use a universal digital signal chip to extract useful information from the signal by digital calculation. In recent years, in the wake of the constantly improving of science and technology and the continuous reform and innovation of technology in China, DSP is more and more close to people's production and life, and plays an important role in practical applications. Therefore, it is necessary to discuss and analyze its development.

A High-Accuracy Low-Power Approximate Multipliers with New Error Compensation Technique for DSP Applications

A High-Accuracy Low-Power Approximate Multipliers with New Error Compensation Technique for DSP Applications

Design of canonical signed digit multiplier using spurious power suppression technique adder

Reducing power consumption is a major challenge in developing integrated processors for smart portable devices. This is particularly important for extending battery life and ensuring extended usage of the device. However, some DSP processing applications involve complex algorithms that consume more power, which poses a significant challenge in designing DSP applications for VLSI circuits. To address this issue, low-power consumption methodologies are required. Although various strategies have been developed to reduce power consumption, they have not demonstrated a significant decrease in dynamic power consumption, which is the primary factor determining the total amount of power dissipation.The focus of this research is to develop a low-power multiplier using the spurious power suppression technique (SPST), a method that divides the arithmetic unit into the most significant part (MSP) and least significant part (LSP) and turns off the MSP when it is not required for computation. This approach reduces dynamic power and overall power consumption of the VLSI combinational circuit. The proposed system also utilizes canonical signed digit (CSD) representation to further reduce power usage.The system was designed using Cadence design suite, and the results showed a significant reduction of 35.8% in power consumption for a 32-bit SPST-enabled CSD multiplier. The proposed system’s total power consumption is 0.561 mW. Additionally, the proposed system was used in a power and area-efficient 256-point FFT architecture, resulting in an 86.6% reduction in power consumption. This system is suitable for real-time applications such as systems that use orthogonal frequency division multiplexing.

Design of FIR Filter Using Low-Power and High-Speed Carry Select Adder for Low-Power DSP Applications

Adders are one of the basic arithmetic circuits of any processor, microcomputer, multiplication circuits, etc. Presently, the most substantial areas in the research of VLSI design are area, power, and efficient high-speed circuits. In this paper two new architectures Carry Select Adder (CSLA) using D-latch and CSLA using multiplexers are proposed to reduce the power, delay, and its efficiency is compared with conventional carry select adder (CSLA) and existing literature. Architectural level power reduction is the most important area where it plays a vital role in improving the speed and power of the overall circuit. The existing and proposed CSLAs are synthesized with the Synopsys EDA tool using 32 nm technology node is used for the design and implementation. The values obtained across technology in nm underline the dominance of the proposed adder architectures in terms of delay and energy and area efficiency. For the proposed architectures, the evaluation results show that 60%–75% improvement in delay and 22%–56%in power when compared to other architectures. Proposed architectures shows increment in area but overall are delay product reduces compares to existing designs The proposed CSLA-DLATCH-FIR obtained significant reduction for 16-bits for power (46.4 (µW)), delay (0.66), ADP (359.8 × 10–15), and PDP (30.63 × 10–15). While the proposed CSLA-MUX-FIR has attained substantial performance for power (52.44 (µW)), delay (0.82 ns), ADP (457.392 × 10–15), and PDP (42.9 × 10–15). With the use of this proposed CSLA, a FIR filter was able to significantly reduce its power and delay.

Guest Editorial: Special Issue on Systems Optimizations for DSP and AI Applications

Guest Editorial: Special Issue on Systems Optimizations for DSP and AI Applications

Efficient Algorithms and Architectures for DSP Applications

In the new era of digital revolution, the digital sensors and embedded designs become cheaper and more present [...]

Energy Efficient Approximate 8-bit Vedic Multiplier

Abstract: The digital signal processing and its classification applications on the energy constrained devices should be supported based on efficiency. Because such applications must perform highly complex computations especially complex multiplication processes while exhibiting tolerance for a large amount of noise and for computational errors too. So, comparing all the arithmetic computations, improving the energy efficiency of multiplication is critical. In this project, an energy efficient approximate 8-bit Vedic multiplier is proposed which gives a tradeoff between computational accuracy and energy consumption. The proposed architecture has reduced area compared to other multiplier architectures which process same number of bits. The reduced architecture area reduces the power consumption. Also, the Vedic technology adopted for the multiplication reducesthe delay further. But the approximate architecture output possesses a small amount of computational accuracy which is negligible for DSP applications.

VLSI implementation of high speed multiplier architecture using VHBCSE algorithm for DSP applications

VLSI implementation of high speed multiplier architecture using VHBCSE algorithm for DSP applications

VLSI Implementation of Low Power FIR Filter using Variable Precision Two-Dimensional Pipeline Gating Multiplier

The low-power FIR filter is required for many DSP applications. The crucial and powerhungry block in the filter is a multiplier. To implement the low power FIR filter a twodimensional variable precision fine-grain pipeline gating technique is introduced in the multiplier. The optimized multiplier is used to implement the transposed form-based FIR filter for the order N = 8 in ASIC design tools from Cadence in CMOS 45nm Technology. The designed FIR filter is compared with the existing multiplier-based FIR filters. The power-saving is achieved by the proposed filter is 22% without any degradation in the speed. The area penalty is 3% only due to the variable precision two-dimensional pipeline gating technique. Keywords: FIR filter, Fine grain pipeline, dynamic power, clock gating, low power multiplier, VLSI, and variable precision.

Low Complexity Multiplierless Welch Estimator Based on Memory-Based FFT

This paper proposes a novel hardware efficient low power Welch power spectral density (PSD) estimator. The presented multiplier-less hardware uses a combined coefficient selection and shift-and-add implementation (CCSSI) unit in order to prevent multiplications in FFT computation. Two filtering operations, which are implemented in folded architecture, are utilized. The micro-rotation resources of the CCSSI unit can be shared with estimator’s modules simultaneously. The proposed architecture is a nonparametric estimator that operates based on a modified, memory-based, 128-point scalable radix-22 FFT processor. It uses bidirectional fractional delay filter to estimate half delay sample in merging two FFTs. Using modified safe-scaling, the final output would be valid, without any averaging operation. Another important feature of the proposed method is its capability of operating in short word lengths (WL). Artix-7, as an ideal option for DSP applications, is the utilized FPGA in this research. As results demonstrate, the hardware has a high capability in operating in short WLs which results in high performance in low-power applications.