Drain Overlap Region Research Articles

Investigation of the Device Electrical Parameters for Homo and Hetero Junction Based TFETs

This paper presents the analytical approximation of device physics of heterojunction based double gate (DG) Tunnel field effect transistors (TFETs) in terms of potential distribution, electron density and electron barrier tunneling. In order to improve the device performance with respect to ON current (ION), DG TFET with gate-drain overlap is developed. An asymmetric gate oxide is introduced in the gate - drain overlap region and is compared to DG TFET. The device physics and its performance characteristics are studied by using various materials, such as Si, SiGe, InAs and GaSb. The simulated results are validated against the model values. DG TFETs with gate-drain overlap offers higher tunneling probability compared to DG TFETs. Also GaSb/Si based DG TFETs with gate-drain overlap shows good performance improvement by offering higher tunneling probability which in turn offers a higher ION of 1.15 mA/μm.

Compact Modeling of Temperature-Dependent Gate-Induced Drain Leakage Including Low-Field Effects

We model the temperature-dependent gate-induced drain leakage (GIDL) in FinFETs. Berkeley short-channel IGFET model-common multi gate (BSIM-CMG) model for FinFET uses the only band-to-band tunneling (BTBT) to model the GIDL mechanism, which is not sufficient to capture the GIDL at low electric field. The proposed model captures trap-assisted tunneling (TAT) at low electric field and BTBT at a high electric field, in the gate–drain overlap region. It contains a single piece expression for trap-assisted tunneling GIDL current, especially present in the sub-20-nm FinFET technology node. The model is validated with the measurement data and it accurately captures the physical behavior of GIDL current. The developed model can be implemented in industry standard compact models.

Endurance degradation and lifetime model of p-channel floating gate flash memory device with 2T structure

The endurance degradation mechanisms of p-channel floating gate flash memory device with two-transistor (2T) structure are investigated in detail in this work. With the help of charge pumping (CP) measurements and Sentaurus TCAD simulations, the damages in the drain overlap region along the tunnel oxide interface caused by band-to-band (BTB) tunneling programming and the damages in the channel region resulted from Fowler-Nordheim (FN) tunneling erasure are verified respectively. Furthermore, the lifetime model of endurance characteristic is extracted, which can extrapolate the endurance degradation tendency and predict the lifetime of the device.

Dependence of DRAM Device Performance on Passivation Annealing Position in Trench and Stack Structures for Manufacturing Optimization

The dependence of dynamic random access memory (DRAM) device performance on trench and stack cell structures was first observed by changing the process position of passivation annealing. For the trench DRAM, the data retention fail bit counts (FBCs) decreased by 18% and the cell transistor threshold voltage (CTVth) shift by 53 mV. The FBCs are primarily influenced by the junction leakage current. In contrast, for the stack DRAM, the data retention FBCs increased by 225% and the CTVth shift increased by 20 mV. The FBCs are primarily influenced by the gate-induced drain leakage (GIDL) current because of the large gate and the drain overlap region in the recess channel array transistor (RCAT). The interface states increased after the deposition of the plasma nitride layer, as observed in the charge pumping measurement in the trench DRAM. Transmission electron microscopy indicated that the gate oxide thickness in the bottom region of the RCAT is thinner to generate gate oxide leakage. Furthermore, a decrease in the activation energy from 0.64 to 0.55 eV implies the occurrence of GIDL current, which corresponds to the FBC analysis result. This paper demonstrated that the passivation annealing position requires careful adjustment for device and manufacturing optimization.

Characterization of defect density created by stress in the gate to drain overlap region using GIDL current model in n-channel MOSFET

In this paper we study the impact of stress on gate induced drain leakage (GIDL) current variations in MOS transistors, which manifested by tunneling in the gate to drain overlap region. The oxide thickness of n-channel transistor used is 8.5 nm. We show that this phenomenon is accentuated in high stress accumulation V g=?3 V, V d=3 V, but more less for stress V g=V d=3 V. In both cases, any constraint corresponds to an increase in accumulated charges in the transistor and hence the current GIDL.

Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

We generated traps inside gate oxide in gate–drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler–Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal–oxide–semiconductor field-effect transistors (MOSFETs).

Effect of Channel Length and Width on NBTI in Ultra Deep Sub-Micron PMOSFETs

The effects of channel length and width on the degradation of negative bias temperature instability (NBTI) are studied. With the channel length decreasing, the NBTI degradation increases. As the channel edges have more damage and latent damage for the process reasons, the device can be divided into three parts: the gate and source overlap region, the middle channel region, and the gate and drain overlap region. When the NBTI stress is applied, the non-uniform distribution of the generated defects in the three parts will be generated due to the inhomogeneous degradation. With the decreasing channel length, the channel edge regions will take up a larger ratio to the middle channel region and the degradation of NBTI is enhanced. The channel width also plays an important role in the degradation of NBTI. There is an inflection point during the decreasing channel width. There are two particular factors: the lower vertical electric field effect for the thicker gate oxide thickness of the shallow trench isolation (STI) edge and the STI mechanical stress effecting on the NBTI degradation. The former reduces and the latter intensifies the degradation. Under the mutual compromise of the both factors, when the effect of the STI mechanical stress starts to prevail over the lower vertical electric field effect with the channel width decreasing, the inflection point comes into being.

The formation of polycrystalline-Si thin-film transistors by using large-angle-tilt-implantation of dopant through gate sidewall spacer

Formation of poly-Si thin-film transistor (TFT) by large-angle-tilt-implantation of dopant through gate sidewall spacer (LATITS) has been proposed. By this LATITS scheme, the lightly doped drain (LDD) region under the oxide spacer is formed by tilt implantation of dopant through spacer and then the n + source/drain region is formed via using the same mask layer while the CMOS integration. The resultant on-state currents are comparable for both the conventional LDD scheme and the LATITS scheme. In addition, the LATITS scheme can even cause a smaller leakage current than the LDD scheme at high negative gate voltage, due to less gate–drain overlap region. By the LATITS scheme with proper tilt implantation energy, dose and angle, poly-Si TFT devices with an on/off current ratio above eight orders may be achieved with fewer process steps, as compared to the conventional LDD scheme.

A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential

We have developed a model for circuit-simulation which describes the MOSFET region from pinch-off to drain contact based on the surface potential. The model relates the surface-potential increase beyond the pinch-off point to the channel/drain junction profile by applying the Gauss law with the assumption that the lateral field is greater than the vertical one. Explicit equations for the lateral field and the pinch-off length are obtained, which take the potential increase in the drain overlap region into account. The model, as implemented into a circuit simulator, correctly reproduces measured channel conductance and overlap capacitance for 100 nm pocket-implant technologies as a function of bias condition and gate length.

Si–H Bond Breaking Induced Retention Degradation During Packaging Process of 256 Mbit DRAMs With Negative Wordline Bias

Data retention degradation of a 256-Mbit DRAM during the packaging process is investigated in this paper. Electrical measurement and device simulation show that a trap-assisted leakage degrades the retention time even in packaging process at about 250/spl deg/C. Retention time of the degraded chip is strongly dependent on the negative wordline voltage and operation temperature, but less sensitive to the substrate bias. Trap-assisted gate induced drain leakage is proposed as the mechanism of retention loss in the degraded chip. The degraded chips usually can be repaired by another thermal baking process. We propose Si-H bond breaking and the subsequent trap generation at the gate and drain overlap region as the root cause of retention degradation according to the fact that the Si-H bond density of backend passivation oxide and nitride layers correlate well with the retention performance of DRAM chips with negative wordline bias. Moreover, the packaged chip shows variable retention behavior during a thermal baking of 250/spl deg/C. Theoretical calculation indicates that the trap generation or movement to the high electrical field region beneath the gate can increase the trap-assisted gate induced drain leakage by about an order of magnitude.

Suppression of Gate Depletion in p+-Polysilicon-Gated Sub-40 nm pMOSFETs by Laser Thermal Processing

Laser thermal processing (LTP) was investigated as a gate pre-annealing technique and its advantages over rapid thermal annealing (RTA) with regard to both gate activation and suppression of boron penetration were confirmed by evaluating the electrical characteristics of sub-40 nm p-metal oxide semiconductor field effect transistors (pMOSFETs). Laser annealing transformed amorphous Si in which high doses of boron were implanted into poly-Si with highly activated boron profiles down to the gate/gate oxide interface. By suppressing gate depletion with suppressing boron penetration, LTP results in an on-current at Ioff=70 [nA/µm] that is 4% greater than that in a device fabricated using conventional RTA. The off-state Ig current that flows mainly from the p+ poly-Si gate to the drain overlap region is smaller in devices fabricated using LTP because the reduced roughness of the poly-Si gate/gate oxide interface in these devices reduces the local electric field enhancement.

Impact of gate-induced drain leakage on retention time distribution of 256 Mbit DRAM with negative wordline bias

A negative wordline bias scheme is utilized to reduce the subthreshold leakage of deep submicron DRAM cell transistors. With excessive negative wordline bias, gate-induced drain leakage (GIDL) could dominate cell leakage and degrade product retention time performance. The dependence of retention time on negative wordline bias for a 256-Mbit DRAM with 0.14/spl mu/m ground rule is investigated. The retention fail bit count in the tail distribution increases as wordline bias goes more negative and as temperature increases. A cell array with a density of 1.14M is also characterized for the device leakage behavior. The negative wordline bias and temperature dependent GIDL is believed to be due to band to defect tunneling. Hence, elimination of traps near the oxide/silicon interface in the gate to drain overlap region during the DRAM fabrication process is important for the negative wordline scheme.

Structural dependence of breakdown characteristics and electrical degradation in ultrathin RPECVD oxide/nitride gate dielectrics under constant voltage stress

The structural dependence of breakdown characteristics and electrical degradation in ultrathin oxide/nitride (O/N) dielectrics, prepared by remote plasma enhanced chemical vapor deposition, is investigated under constant voltage stress. In the early stage of oxide wearout, soft breakdown is a local phenomenon dominated by the tunneling current. After a given period of stress, a strong channel-length dependence of dielectric breakdown and the corresponding stress-induced leakage current from the evolution of increased tunneling current have been found. Stacked O/N dielectrics with interface nitridation demonstrate improved device performance on subthreshold swing and threshold voltage shifts after stress, indicating the suppression of stress-induced traps at the oxide/Si and oxide/drain interfaces compared to thermal oxides. Experimental evidence shows more severe breakdown and device degradation in the threshold voltage, drain current and transconductance for shorter channel PMOSFETs with O/N dielectrics. These degradations result from the enhancement of hole trapping in the gate–drain overlap region as evidenced by a positive off-state leakage current, which leads to hard breakdown, and the complete failure of device functionality.

Soft breakdown at all positions along the N-MOSFET

We observe soft breakdowns at all positions along the gates of N-MOSFETs when testing is performed at low voltage or with low current compliance. Devices whose breakdown spots are at or near the gate–drain overlap region have the highest off-currents, although not high enough to be fatal to device operation.

Offset-Gate Structures for Increased Breakdown Voltages in Silicon-On-Insulator Transistors

ABSTRACTAn offset-gate structure was used to fabricate p-channel MOS transistors in laser-recrystallized silicon-on-insulator (SOI) films. The breakdown voltage increased from about -18 V with a conventional gate structure to about -38 V with the offset gate and was then limited by bulk breakdown in the film, rather than by the high fields near the gate drain overlap region. Simulations indicate that breakdown voltages of about -60 V can be achieved in the structure used, provided that the back-surface fixed-charge density is limited to 1×10″ cm−2.