Drain Current Degradation Research Articles

Local oxide capacitance as a crucial parameter for characterization of hot-carrier degradation in long-channel n-MOSFETs

A theoretical model for the MOSFET local oxide capacitance as a crucial parameter for the characterization of hot-carrier degradation has been developed. For this purpose, the conformal mapping technique is used. On the basis of the proposed approach a refined extraction scheme for the defect distribution from charge-pumping measurements has been employed. Assuming the extracted spatial trap distributions at different stress times as input, the transfer characteristics and linear drain current degradation are numerically calculated and compared with the experimental results. A very good agreement is achieved. These results demonstrate that the coordinate dependence of the oxide capacitance is extremely important for an accurate extraction of the defect profile particularly for large stress times. Additionally, the obtained results confirm the findings of our physics-based model of hot-carrier degradation.

Numerical analysis of localised charges impact on static and dynamic performance of nanoscale cylindrical surrounding gate MOSFET based CMOS inverter

In the present work, effect of stress/hot carrier/process damage/radiation damage induced localised/fixed charges on static and dynamic performance of CMOS inverter using nanoscale cylindrical surrounding gate (SRG) MOSFET has been studied. Significant threshold voltage shift, drain current and transconductance degradation due to induced localised charges at the Si–SiO2 interface of the SRG p-MOSFET (used as load) give rise to inverter performance degradation in terms of change in its voltage transfer characteristics, noise margin and propagation delay. Four different localised charge density profiles have been used to in order to estimate the performance degradation due to localised charges.

Reliability Improvement of 28-nm High-$k$/Metal Gate-Last MOSFET Using Appropriate Oxygen Annealing

In this letter, performance and reliability of high-k/metal gate MOSFETs can be effectively improved using post metallization annealing. Both oxygen and nitrogen were shown to diffuse into a high-k/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interfacial layer to suppress the formation of oxygen vacancy, thus reducing the gate leakage current without increasing effective oxide thickness. In particular, with appropriate oxygen annealing, gate-induced drain leakage, drain-current degradation, and gate leakage current variation of high- k/metal gate-last MOSFETs can be efficiently suppressed.

Threshold voltage shift and drain current degradation by negative bias temperature instability in Si (110) p-channel metal-oxide-semiconductor field-effect transistor

Negative bias temperature instability in Si (100) and (110) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) is systematically studied. Threshold voltage shift in (110) pMOSFETs is found to be larger than that in (100) pMOSFETs because of larger amount of the generated interface traps. On the other hand, mechanisms behind the generation of the interface traps are independent of the surface orientations. We newly found that drain current degradation in (110) pMOSFETs is severer than that in (100) pMOSFETs even when the same amount of charges is generated at the interface. This can be explained by larger mobility degradation in (110) pMOSFETs.

Investigation of Hot-Carrier Stress Effect on High-Frequency Performance of Laterally Diffused Metal–Oxide–Semiconductor Transistors

The hot-carrier stress effects on the high-frequency performance characteristics of laterally diffused metal–oxide–semiconductor (LDMOS) transistors were investigated. A constant bias channel hot-carrier stress was applied at room temperature. After applying 3 h of hot-carrier stress, the on-resistance and saturation drain current degradations are 18 and 9%, respectively. However, the degradations of the cutoff frequency and maximum oscillation frequency were less than 2% when the devices were biased before the onset of quasi-saturation. In addition, we found that the degradations of high-frequency parameters are not related to the change in transconductance but to the changes in gate capacitances. Finally, S-parameter variations under hot-carrier stress were also examined in this study. The observations of S-parameter variations are important for RF power amplifier design.

GaN HEMT Reliability: From Time Dependent Gate Degradation to On-state Failure Mechanisms

ABSTRACTIn this paper, we compare degradation modes and failure mechanisms of different AlGaN/GaN HEMT technologies. We present data concerning reverse-bias degradation of GaN-based HEMTs, which results in a dramatic increase of gate leakage current, and present a timedependent model for gate degradation. Some of the tested technologies demonstrated to be immune from this failure mechanism up to drain-gate voltages in excess of 100 V. When this was the case, the main failure mode consisted of drain current degradation during on-state tests, resulting from charge trapping in the gate-drain access region attributed to hot-electron effects. Finally, the use of diagnostic techniques such as electroluminescence microscopy and Deep Level Transient Spectroscopy for the identification of failure modes and mechanisms of GaNbased HEMTs is reviewed. Concerning reverse-bias degradation of GaN-based HEMTs, we demonstrate that, (i) when submitted to reverse-gate stress, HEMTs can show both recoverable and permanent degradation. (ii) recoverable degradation consists of a decrease in gate current and threshold voltage, which are ascribed to the simultaneous trapping of negative charge in the AlGaN layer, and of positive charge close to the AlGaN/GaN interface. (iii) permanent degradation is manifested by the generation of parasitic leakage paths. Time-dependent analysis suggests that permanent degradation can be ascribed to a defect generation and percolation process. Results supports the existence of a time to breakdown for HEMT degradation, which significantly depends on the stress voltage level. On the contrary, AlGaN/GaN technologies which were found to be resistant to gate degradation (off-state critical voltage larger than 100 V for a 0.25 um gate device) were subjected to on-state tests at different gate and drain voltage levels. All tests showed a non-recoverable degradation of electrical parameters (drain saturation current, threshold voltage and on-state resistance) and electroluminescence signal EL, with a strong dependence on the EL value of the bias point, and a negligible dependence of temperature. Once verified that EL intensity represents a reliable estimate of channel hot electron effects, we attributed the degradation to hot electron trapping in the gate-drain access region. Using EL intensity as a measure of the stress acceleration factor, we derived an acceleration law for GaN HEMT hot electron degradation similar to the one already demonstrated for GaAs devices.

(Invited) Electric-Field and Thermally-Activated Failure Mechanisms of AlGaN/GaN High Electron Mobility Transistors

Main failure modes of AlGaN/GaN HEMTs can be divided into three main categories: 1) Catastrophic increase of gate leakage, accompanied by an increase in trap density which closely resembles time dependent dielectric breakdown effects of MOS structures; 2) hot-electrons and trap-induced effects, which induce increase in parasitic drain resistance and threshold voltage shifts; 3) thermally-activated degradation of drain current, which has been observed especially during long-term accelerated tests, with a very wide range of activation energies, from 1.05 eV to 2.47 eV. In the following, some recent results concerning these three failure modes are presented, together with some hypothesis on the degradation mechanisms involved.

Degradation in InAlN/AlN/GaN heterostructure field-effect transistors as monitored by low-frequency noise measurements: Hot phonon effects

Low-frequency noise technique was applied to analyze performance of nearly lattice-matched InAlN/AlN/GaN heterostructure field-effect transistors and their degradation caused by electrical stress. Nearly identical devices from the same wafer have undergone a 7 h DC electrical stress at a fixed DC drain bias of VDS = 20 V and different gate biases. We noted up to 32 dB/Hz higher low-frequency noise for stressed devices over the entire frequency range of 1 Hz-100 kHz. The measurements showed the minimum degradation at a gate-controlled two-dimensional electron gas density of 9.4 × 1012 cm−2. This result is in good agreement with the reported stress effect on drain-current degradation and current-gain-cutoff-frequency measurements and consistent with the ultrafast decay of hot-phonons due to the phonon–plasmon coupling.

Laser Anneal-Induced Effects on the NBTI Degradation of Advanced-Process 45nm High-K PMOS

This paper presents the effects imposed on the reliability of advanced-process CMOS devices, specifically the NBTI degradation, subsequent to the integration of laser annealing (LA) in the process flow of a 45nm HfO2/TiN gate stack PMOS device. The laser annealing temperatures were varied from 900°C to 1350°C. The effects imposed on the NBTI degradation of the device were comprehensively analyzed in which the shifts of the threshold voltage and drain current degradation were observed. The analysis was extended to the effects of the conventional RTA as opposed to the advanced laser annealing process. It was observed that the incorporation of laser annealing in the process flow of the device enhances the NBTI degradation rate of the device, in contrast to the integration of the conventional RTA. Laser annealing subsequent to spike-anneal is observed to improve the reliability performance of the transistor at high negative biases.

The Layout Geometry Dependence of the Power Cells on Performances and Reliability

The performances and reliability of the NMOS power cells for power amplifiers (PA) were proposed. The performances of power cells with different layout geometries have been compared. The drain current degradation of the NMOS transistors due to hot-carrier effect and high RF power stresses induced by the load impedance mismatches was also present in this work. The load mismatch factors at fundamental, second-order, and third-order frequencies were analyzed to quantify the power mismatch. The cells were fabricated by a 0.18 μm CMOS process. All of the characteristics of the devices were measured at 5.2 GHz.

Novel fluctuation-based approach to optimization of frequency performance and degradation of nitride heterostructure field effect transistors

The fluctuation-based technique has been used to shed light onto the physical processes responsible for the performance of nitride heterostructure field effect transistors. A non-monotonic dependence of hot-phonon lifetime on the density of two-dimensional electron gas (2DEG) is found and interpreted in terms of plasmon-longitudinal-optical-phonon resonance. Experimental data show that the hot-phonon lifetime acquires the shortest value in the vicinity of the resonance. At a fixed 2DEG density of the 2DEG, the resonance can be tuned in with supplied electric power. The signatures of the resonance have also been resolved in frequency performance of the transistors and their degradation. In particular, the transistor operation is the fastest and the reliability is the highest when the hot-phonon lifetime is the shortest. (online colour at: www.pss-a.com) Drain current degradation (stars [8]) correlates with hot-phonon lifetime (curve).

Role of stress voltage on structural degradation of GaN high-electron-mobility transistors

In GaN high-electron-mobility transistors, electrical degradation due to high-voltage stress is characterized by a critical voltage at which irreversible degradation starts to take place. Separately, cross-sectional TEM analysis has revealed significant crystallographic damage for severely degraded devices. Furthermore, a close correlation between the degree of drain current degradation and material degradation has been reported. However, the role of the critical voltage in physical degradation has not been explored. In this work, we investigate the connection between electrical degradation that occurs around and beyond the critical voltage and the formation of crystallographic defects through detailed electrical and TEM analysis, respectively. We find that a groove in the GaN cap starts to be generated around the critical voltage. At higher voltages, a pit develops that penetrates into the AlGaN barrier. The size of the pit increases with stress voltage. We also observe a good correlation between electrical and material degradation.

Effect of Interface Traps and Oxide Charge on Drain Current Degradation in Tunneling Field-Effect Transistors

In this letter, we report for the first time the degradation mechanism of drain current in tunneling field-effect transistors (TFETs). Using positive-bias and hot-carrier (HC) stress experiments and TCAD simulation, we show that the drain current degradation is mainly induced by the interface traps and/or oxide charge located above the tunneling region, causing reduction of tunneling field and tunneling current. The interface traps mainly induce the degradation in transconductance, while the oxide charge essentially causes a threshold-voltage shift in TFETs. The results show that the interface-trap generation is dominant under a positive-bias stress, while the oxide-charge creation is important under an HC stress in n-TFETs.

High breakdown AlGaN/GaN MOSHEMT with thermal oxidized Ni/Ti as gate insulator

Direct oxidation of composite Ni/Ti metal film structure for AlGaN/GaN MOSHEMT has been successfully demonstrated. In comparison with normal HEMT with Schottky-gate, transistors fabricated with this novel process exhibit three orders of magnitude reduction in gate leakage current, superior breakdown voltage ( V br = 471 V vs. 88 V for normal HEMT) and electrical stability (∼0.3% electric field stress induced drain current degradation versus ∼6% for normal HEMT after 25 V drain bias). The drastic improvement in device performance stability, renders the new process highly promising for GaN based, microwave power amplifier applications in communication and radar systems.

The effect of neutron irradiation on the AlGaN/GaN high electron mobility transistors

AbstractThe SiN‐passivated AlGaN/GaN high electron mobility transistors were investigated by 1MeV neutron irradiation at fluences up to 1015 cm‐2, yielding a significant degradation for the transconductance near the knee voltage and the reverse gate leakage current at fluences ranging from 1014 to 1015 cm‐2 which could be attributed to the irradiation induced mobility shift and the defects in SiN passivation layers respectively since no any recovery was found after 20 hour annealing at room temperature. Meanwhile the negligible degradation of the saturation drain current, the maximal transconductance and the threshold voltage gave the fact that the effectiveness of SiN layers in passivated surface states in the source‐gate spacer and gate‐drain spacer was undiminished by neutron irradiation. Moreover the ohmic contact was robustness to neutron since the sheet resistance of ohmic contact region hardly shifted, but the schottky characteristics degraded obviously. (© 2010 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Stress test measurements of lattice‐matched InAlN/AlN/GaN HFET structures

AbstractInAlN/GaN heterostructures offer some benefits over existing AlGaN/GaN heterostructures for HFET device applications. In addition to having a larger bandgap than typical AlGaN compounds used in HFET devices (with Al &lt; 30%), which leads to better confinement and subsequent larger power carrying capacity, InAlN can be grown lattice‐matched to GaN, resulting in strain‐free heterostructures. As such, lattice‐matched InAlN provides a unique system wherein the reliability of the devices may exceed that of the strained AlGaN/GaN devices as a result of being able to decouple the hot electron/hot phonon effects on the reliability from the strain related issues. In this work, we subjected lattice‐matched InAlN‐based HFETs to electrical stress and observed the corresponding degradation in maximum drain current. We found that the degradation rates are lower only for a narrow range of moderate gate biases, corresponding to low field average 2‐dimensional electron gas (2DEG) densities of 9–10 × 1012 cm−2. We propose that the degradation is attributable to the buildup of hot phonons since the degradation rates as a function of electron density generally follow the hot phonon lifetime versus electron density. This provides evidence that hot phonons have a significant role in device degradation and there exists an optimal 2DEG density to minimize hot phonon related degradation. We did not observe any correlation between the degradation rate and the gate leakage.

Fabrication Process of Carbon Nanotube Field Effect Transistors Using Atomic Layer Deposition Passivation for Biosensors

Fabrication process of the carbon nanotube (CNT) field effect transistors (FETs) for biosensors was studied. Atomic layer deposition (ALD) of HfO2 was applied to the deposition of the passivation/gate insulator film. The CNT-FETs did not show the drain current degradation after ALD passivation even though the passivation by Si3N4 deposited by plasma-enhanced chemical vapor deposition (PECVD) resulted in a significant drain current decrease. This indicates the advantage of the present ALD technique in terms of the damage suppression. The biosensing operation was confirmed using thus fabricated CNT-FETs.

Passivation of AlN∕GaN high electron mobility transistor using ozone treatment

Ozone treatment of AlN on AlN∕GaN heterostructures produces effective surface passivation and chemical resistance to the AZ positive photoresist developer used for subsequent device fabrication. The ozone-passivated AlN∕GaN high electron mobility transistors (HEMTs) exhibited low gate leakage currents, high gate modulation voltage, and minimal drain current degradation during gate pulse measurements. With an additional oxygen plasma treatment on the gate area prior to the gate metal deposition, enhancement-mode AlN∕GaN high electron mobility transistors were realized. The gate characteristics of the HEMTs treated with the ozone and oxygen plasma behaved in a manner similar to a metal oxide semiconductor diodelike gate current-voltage characteristic instead of a Schottky diode. Drain breakdown voltages of 23 and 43V for d- and e-mode HEMTs were obtained, respectively. For d-mode HEMTs, there was no reduction in the drain current during the gate pulse measurements at frequencies of 1, 10, and 100kHz. For the e-mode HEMT, the drain current was reduced 5% at 100kHz.

Plasma-Induced Defect-Site Generation in Si Substrate and Its Impact on Performance Degradation in Scaled MOSFETs

Plasma-induced ion-bombardment damage was studied in terms of defect sites created underneath the exposed Si surface. From the shift of capacitance-voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> ) curves, the defect sites were found to capture carriers (being negatively charged in the case of an Ar plasma exposure). This results in a change of the effective impurity-doping density and the profile. We also report that the defect density depends on the energy of ions from plasma. A simplified and quantitative model is proposed for the drain-current degradation induced by the series-resistance increase by the damage. The relationship derived between the defect density and the drain-current degradation is verified by device simulations. The proposed model is useful to predict the device performance change from plasma process parameters.

Convergence of Hot-Carrier-Induced Saturation Region Drain Current and On-Resistance Degradation in Drain Extended MOS Transistors

Hot-carrier-induced device degradation in n-type high-voltage drain-extended MOS (DEMOS) devices stressed under high drain voltage and high gate voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vg</i> ) is investigated. Charge pumping data and technology computer-aided-design simulation results reveal that hot-carrier-induced interface state formation in the gate overlapped shallow trench isolation region is responsible for device degradation. Furthermore, an unexpected high saturation region drain current ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Id</i> (sat)) degradation (close to on-resistance degradation) is observed. The occurrence of quasi-saturation under high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vg</i> bias is the cause of significant <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Id</i> (sat) degradation. The results presented in this paper suggest that severe <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Id</i> (sat) degradation may become a reliability concern for devices exhibiting the quasi-saturation phenomenon.