Double Gate Junctionless Transistor Research Articles

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson's equation using "variable separation technique". The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.

Compact model for short-channel symmetric double-gate junctionless transistors

In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage roll-off, series resistance, drain saturation voltage, channel shortening and saturation velocity. The threshold voltage shift and subthreshold slope variation is determined through the minimum value of the potential in the channel. Only eight model parameters are used. The model is physically-based, considers the total charge in the Si layer and the operating conditions in both depletion and accumulation. Model is validated by 2D simulations in ATLAS for channel lengths from 25nm to 500nm and for doping concentrations of 5×1018 and 1×1019cm−3, as well as for Si layer thickness of 10 and 15nm, in order to guarantee normally-off operation of the transistors. The model provides an accurate continuous description of the transistor behavior in all operating regions.

A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor

In this paper, we have developed a pseudo two-dimensional (2-D) analytical model for the surface potential of a dual-material double-gate junctionless field-effect transistor. We have incorporated the effects of depletion into the source and drain regions to model the surface potential for all three operating modes: (a) full depletion, (b) partial depletion, and (c) near flatband. The effects of the device parameters such as oxide thickness, silicon thickness, and impurity concentration on the surface potential is demonstrated through the model. The model is further extended to derive an expression for the threshold voltage which predicts the expected change with respect to variation in the device parameters. The accuracy of the proposed model is verified against 2-D numerical simulations.

Analog performance investigation of misaligned double gate junctionless transistor

In this paper, the analog performance of a misaligned double gate junctionless transistor (DGJLT) is demonstrated for the first time. The gate misalignment can occur on either source side (MA_S) or at drain side (MA_D). Since misalignment is a type of degradation that occurs during device fabrication, the idea behind this demonstration is to analyze the impact of gate misalignment on DGJLT. The analog performance parameters analyzed are, transconductance $$(\hbox {g}_{\mathrm{m}})$$(gm), output conductance $$(\hbox {g}_{\mathrm{ds}})$$(gds), early voltage $$(\hbox {V}_{\mathrm{EA}})$$(VEA) and intrinsic gain $$(\hbox {A}_{\mathrm{VO}})$$(AVO). They are compared with a double gate inversion mode transistor (DGIMT) under same gate misalignment condition. A DGJLT is found to have better tolerance to gate misalignment compared to DGIMT. MA_S configuration of a DGJLT shows better analog performance compared to MA_D configuration where as for DGIMT it shows better performance for MA_D compared to MA_S configuration.

Double-gate junctionless transistor model including short-channel effects

This work presents a physically based model for double-gate junctionless transistors (JLTs), continuous in all operation regimes. To describe short-channel transistors, short-channel effects (SCEs), such as increase of the channel potential due to drain bias, carrier velocity saturation and mobility degradation due to vertical and longitudinal electric fields, are included in a previous model developed for long-channel double-gate JLTs. To validate the model, an analysis is made by using three-dimensional numerical simulations performed in a Sentaurus Device Simulator from Synopsys. Different doping concentrations, channel widths and channel lengths are considered in this work. Besides that, the series resistance influence is numerically included and validated for a wide range of source and drain extensions. In order to check if the SCEs are appropriately described, besides drain current, transconductance and output conductance characteristics, the following parameters are analyzed to demonstrate the good agreement between model and simulation and the SCEs occurrence in this technology: threshold voltage (VTH), subthreshold slope (S) and drain induced barrier lowering.

Computational Study of Effects of Surface Roughness and Impurity Scattering in Si Double-Gate Junctionless Transistors

Electron transport in Si double-gate junctionless transistors (JLTs) is simulated on the basis of the multisubband Monte Carlo method, considering acoustic phonons, intervalley phonons, ionized impurities (IIs), and surface roughness (SR) scattering. It is demonstrated that JLTs can actually minimize the mobility degradation caused by SR scattering and improve the current drivability. On the other hand, II scattering is confirmed to degrade the current drivability compared with conventional MOSFETs with an intrinsic channel. However, the performance degradation in JLTs due to II scattering is shown to be insignificant, owing to the screening effect of free carriers and the forward scattering properties of high-speed carriers. Furthermore, by extracting a backscattering coefficient, the screening effect and the forward scattering properties are shown to more mitigate II scattering as the gate voltage increases.

Enhanced sensitivity of double gate junctionless transistor architecture for biosensing applications

In the present work, we demonstrate the potential of double gate junctionless (JL) architecture for enhanced sensitivity for detecting biomolecules in cavity modulated field effect transistors (FETs). The higher values of body factor, achieved in asymmetric gate operation under impact ionization is utilized for enhanced sensing margin which is nearly five times higher than compared to symmetrical mode operation. The intrinsic detection sensitivity is evaluated in terms of threshold voltage change, and the ratio of drain current in the presence and absence of biomolecules in JL nanotransistors. It is shown that asymmetric mode JL transistor achieves a higher degree of detection sensitivity even for a partially filled cavity. The work demonstrates the potential of JL channel architecture for cavity based dielectric modulated FET biosensors.

Modeling and simulation of Double Gate Junctionless Transistor considering fringing field effects

In the present work, the performance of DG-JL transistor has been analysed using analytical modeling scheme as well as 3D device simulation technique. Thus an advance two dimensional analytical sub-threshold drain current model for Double Gate Junctionless (DG-JL) Transistor is presented in this work by considering the impact of fringing field from the gate to source/drain region using conformal mapping technique. The results obtained from proposed model have been verified with the ATLAS 3D device simulation software results. The relevant Short Channel Effect parameters like threshold voltage roll off, Drain Induced Barrier Lowering (DIBL) and Subthreshold Slope (S) are also evaluated using modeling scheme. In addition to this, the suitability of DG-JL Transistor for low voltage digital and analog applications has been investigated through exhaustive device simulation using ATLAS 3D device simulation software only. In essence, this work provides the dependencies of the device performance on the physical device parameters of DG-JL transistor for its assessment for better digital and analog operation.

Channel Grading Technique for Improved Tolerance to Gate Misaligned Double Gate Junctionless Transistor

Channel Grading Technique for Improved Tolerance to Gate Misaligned Double Gate Junctionless Transistor

The effect of high-k gate dielectrics on device and circuit performances of a junctionless transistor

The impacts of high-k gate dielectric permittivity on the device and circuit performances of a double-gate junctionless transistor (DGJLT) are studied with the help of extensive device simulations. The results are compared with a conventional inversion mode double-gate metal oxide semiconductor field effect transistor (DG MOSFET) of same dimension. Drain induced barrier lowering, intrinsic gain $$(G_{m}R_{O})$$(GmRO), and unity gain cut-off frequency $$(f_{T})$$(fT) are degraded with an increase in gate dielectric permittivity $$(k)$$(k). The transconductance $$(G_{m})$$(Gm) and gate capacitance $$(C_{GG})$$(CGG) are slightly affected with increase in $$k$$k. The gain of CMOS single stage amplifier and delay of inverter are found to be decreasing and increasing, respectively, with increase in $$k$$k. In order to mitigate these short channel effects due to the high-k gate dielectrics, a hetero-gate-dielectric structure with symmetric double-gate junctionless transistor (HG-DGJLT) is studied. HG-DGJLT offers superior $$G_{m}, \, C_{GG}$$Gm,CGG and $$f_{T}$$fT compared to $$\hbox {SiO}_{2}$$SiO2-only and $$\hbox {HfO}_{2}$$HfO2-only DGJLT. However, intrinsic gain of HG-DGJLT is inferior to $$\hbox {SiO}_{2}$$SiO2-only and $$\hbox {HfO}_{2}$$HfO2-only DGJLT.

Compact analytical model of double gate junction-less field effect transistor comprising quantum-mechanical effect

We investigate the quantum-mechanical effects on the electrical properties of the double-gate junction-less field effect transistors. The quantum-mechanical effect, or carrier energy-quantization effects on the threshold voltage, of DG-JLFET are analytically modeled and incorporated in the Duarte et al. model and then verified by TCAD simulation.

Explicit Analytical Current-Voltage Model for Double-Gate Junctionless Transistors

An explicit analytical model for long-channel double-gate junctionless transistors is presented in each operation mode: 1) full depletion; 2) partial depletion; and 3) accumulation. The proposed model calculates potentials, electric fields, mobile charges, and drain current without any implicit function or special functions. The results obtained with the proposed model agree well with the results obtained with a 2-D technology computer-aided design simulation in all modes of operation and for various device structures. Furthermore, a physical insight is provided into reducing variability using the threshold voltage model.

Modeling of characteristic parameters for nano-scale junctionless double gate MOSFET considering quantum mechanical effect

This paper analytically models the characteristics parameters of nano-scale junctionless double gate MOSFETs under quantum confinement, as junctionless transistors gain advantages over their junction based counterparts recently. The models explicitly show how the device parameters like silicon channel thickness, oxide thickness, channel length etc. affect the characteristic parameters like surface potential, threshold voltage etc. when quantum mechanical effects dominate. We also study the effect of temperature on electron populations on sub-band energy levels. Variable quasi Fermi energy level is considered in this paper to increase the accuracy of the proposed models. Threshold voltage roll-off and drain induced barrier lowering are also analyzed to increase the efficacy of the models. These analytical models, valid from accumulation to depletion regimes, are validated and verified with the data obtained from Schrodinger---Poisson solver model of Technology Computer Aided Design. Simplicity of the proposed models give easy way to understand, analyze, and design Double Gate Junctionless transistors comprehensively.

Physically Based Evaluation of Electron Mobility in Ultrathin-Body Double-Gate Junctionless Transistors

In this letter, we presented theoretical results on the low-field electron mobility of ultrathin-body double-gate junctionless transistors. A 1D Poisson-Schrodinger problem perpendicular to the gate is self-consistently solved to get the electron wavefunctions, and the Kubo-Greenwood formula with consideration of phonon, surface roughness, and ionized impurity scattering is employed to evaluate the corresponding mobility components. The dependence of mobility on silicon layer thick- ness and doping concentration is also investigated.

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.

Effect of geometric parameters on the performance of p-type junctionless lateral gate transistors.

This paper examines the impact of two important geometrical parameters, namely the thickness and source/drain extensions on the performance of low doped p-type double lateral gate junctionless transistors (DGJLTs). The three dimensional Technology Computer-Aided Design simulation is implemented to calculate the characteristics of the devices with different thickness and source/drain extension and based on that, the parameters such as threshold voltage, transconductance and resistance in saturation region are analyzed. In addition, simulation results provide a physical explanation for the variation of device characteristics given by the variation of geometric parameters, mainly based on investigation of the electric field components and the carries density variation. It is shown that, the variation of the carrier density is the main factor which affects the characteristics of the device when the device's thickness is varied. However, the electric field is mainly responsible for variation of the characteristics when the source/drain extension is changed.

Compact core model for Symmetric Double-Gate Junctionless Transistors

A new charge-based compact analytical model for Symmetric Double-Gate Junctionless Transistors is presented. The model is physically-based and considers both the depletion and accumulation operating conditions including the series resistance effects. Most model parameters are related to physical magnitudes and the extraction procedure for each of them is well established. The model provides an accurate continuous description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of being symmetrical with respect to drain voltage equal to zero. It is validated with simulations for doping concentrations of 5×1018 and 1×1019cm−3, as well as for layer thickness of 10 and 15nm, allowing normally-off operation.

A compact model of subthreshold characteristics for short channel double-gate junctionless field effect transistors

A compact subthreshold characteristics model for short channel fully-depleted double-gate (DG) junctionless field effect transistors (JL FETs) which is based on an approximated solution of 2 dimensional Poisson’s equation has been proposed. The derivation details are introduced and the model’s accuracy has been verified by comparison with both previous models and the TCAD simulations’ results which proves that the subthreshold characteristics such as channel potential distribution, subthrethold drain-to-source current, subthreshold slope, drain-induced-barrier-lowering and threshold voltage can be accurately predicted by our proposed compact model.

Device and circuit performance analysis of double gate junctionless transistors at L g = 18 nm

The design and characteristics of double-gate (DG) junctionless (JL) devices are compared with the DG inversion-mode (IM) field effect transistors (FETs) at 45 nm technology node with effective channel length of 18 nm. The comparison are performed at iso-V th for both n- and p-type of devices. The JL device shows lower drain-induced barrier lowering, steep subthreshold slope and lower OFF state current. For the first time, the authors demonstrate a pass gate (PG) logic, inverter circuit and static random access memory (SRAM) stability analysis using JL devices, rather than a complementary metal-oxide semiconductor (CMOS) configuration. They observed that transient response of JL PG configuration is similar to that of conventional CMOS PGs. JL inverter also shows similar transient characteristics with 25% reduction in delay and 12% improvement in 6 T SRAM cell stability compared with IMFETs, which shows large potential in digital circuit applications. The simulations were performed using coupled device-circuit methodology in ATLAS technology aided computer design (TCAD) mixed-mode simulator.

A Dual-Material Gate Junctionless Transistor With High-$k$ Spacer for Enhanced Analog Performance

In this paper, we present a simulation study of analog circuit performance parameters for a symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with high- k spacer dielectric (DMG-SP) on both sides of the gate oxides of the device. The characteristics are demonstrated and compared with DMG DGJLT and single-material (conventional) gate (SMG) DGJLT. The DMG DGJLT presents superior transconductance (Gm), early voltage (VEA), and intrinsic gain (GmRO) compared with SMG DGJLT. The values are further improved for DMG-SP DGJLT, because high- k spacer enhances the fringing electric fields through the spacer.