The barrel shifter is an indispensable floating-point (FP) adder circuit. It performs the alignment on the mantissa of the smallest FP number and also normalizes the added mantissa in a conventional FP adder. Alignment and normalization are two different FP steps at distinct two-barrel shifters. It increases the implementation cost of the FP adder by increasing the chip area and power consumption. The proposed FP adder targets to reduce the area. Where a single barrel shifter replaces two shifters in a conventional FP adder, a single barrel shifter aligns the mantissa. After the mantissa addition, it normalizes the added mantissa. Alignment and normalization share a barrel shifter in the second and fourth FP steps. Consecutive two-clock cycles allow the two sets of FP numbers for two FP additions. In the subsequent two consecutive clock cycles, the shared barrel shifter blocks the input stage that does not fetch the new FP inputs. Compared with a conventional FP adder and FPGA FP cores, a proposed FP adder has two barrel shifters; the single shifter in the proposed adder has a gate count of 867, and the two shifter adder's gate count is 1131. Throughput is restricted in the proposed FP adder sharing a single barrel shifter (SSB) in two pipeline stages. SSB stalls the input stage during the sharing period for two clock cycles. Accordingly, the output is not taken during the period of pipeline stall. The shared barrel shifter conserves the area of 21.60% in Xilinx ZynQ FPGAs and 13.5% in Intel Cyclone FPGAs. Latency remains unchanged in proposed and conventional FP adders. The proposed adder implemented in Xilinx and Intel FPGAs of 3% to 10% of fmax improvement over the conventional double barrel shifter (DBS) FP adder. The proposed adder is feasible for applications where cyclic addition is not required, and it is suitable for interleaved addition like post-quantum cryptography and homomorphic encryption.