Double Adjacent Error Correction Research Articles

Implementation of SEC-DED-DAEC Codes using Mentor Graphics

Correction of a single error Double Error Detection (SEC-DED) and Double Adjacent Error Correction (DAEC) are prominent error correction algorithms used in computer memory systems to detect and fix errors that arise during data transfer. In this research, we want to put these ideas into practice and assess how well they work through simulations and experiments. We will research the trade-offs between these strategies' efficiency and reliability and contrast them with other error correction techniques. Our research will involve designing and putting error detection and correction procedures into circuits and algorithms for DAEC and SEC-DED. We will also investigate other methods, including parallel processing and error checking mechanisms, to enhance the performance of these strategies. Our findings may also have applications in other domains where error correction is important, such as communication systems and medical equipment. They will help us understand and enhance error correction techniques used in computer memory systems.

Correction Masking: A Technique to Implement Efficient SET Tolerant Error Correction Decoders

Single Event Transients (SETs) can be a major concern for combinational circuits. Its importance grows as technology scales because a small charge can create a large disturbance on a circuit node. One example of circuits that can suffer from SETs is the decoders of the Error Correction Codes (ECCs) that are used to protect memories from errors. This paper presents Correction Masking (CM), a technique to implement SET tolerant syndrome decoders. The proposed technique is presented and evaluated both in terms of protection effectiveness and circuit overhead. The results show that it can provide an effective protection while reducing the circuit area and power significantly compared to a Triple Modular Redundancy (TMR) protection. An interesting result is that Correction Masking also reduces the delay as it adds less logic in the critical path than TMR. Finally, the proposed technique can be used for any syndrome decoder. This means that it is applicable to many of the ECCs used to protect memories such as Single Error Correction (SEC), Single Error Correction Double Error Detection (SEC-DED), Single Error Correction Double Adjacent Error Correction (SEC-DAEC), and 3-bit burst codes.

SEC-BADAEC: An Efficient ECC With No Vacancy for Strong Memory Protection

Shrinking process technology and rising memory densities have made memories increasingly vulnerable to errors. Accordingly, DRAM vendors have introduced On-die Error Correction Code (O-ECC) to protect data against the growing number of errors. Current O-ECC provides weak Single Error Correction (SEC), but future memories will require stronger protection as error rates rise. This paper proposes a novel ECC, called Single Error Correction–Byte-Aligned Double Adjacent Error Correction (SEC-BADAEC) and its construction algorithm to improve memory reliability. SEC-BADAEC requires the same redundancy as SEC O-ECC, but it can also correct some frequent 2-bit error patterns. Our evaluation shows SEC-BADAEC can improve memory reliability by 23.5% and system-level reliability by 29.8% with negligible overheads.

Codes for Limited Magnitude Error Correction in Multilevel Cell Memories

Multilevel cell (MLC) memories have been advocated for increasing density at low cost in next generation memories. However, the feature of several bits in a cell reduces the distance between levels; this reduced margin makes such memories more vulnerable to defective phenomena and parameter variations, leading to an error in stored data. These errors typically are of limited magnitude, because the induced change causes the stored value to exceed only a few of the level boundaries. To protect these memories from such errors and ensure that the stored data is not corrupted, Error Correction Codes (ECCs) are commonly used. However, most existing codes have been designed to protect memories in which each cell stores a bit and thus, they are not efficient to protect MLC memories. In this paper, an efficient scheme that can correct up to magnitude-3 errors is presented and evaluated. The scheme is based by combining ECCs that are commonly used to protect traditional memories. In particular, Interleaved Parity (IP) bits and Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes are utilized; both these codes are combined in the proposed IP-DAEC scheme to efficiently provide a strong coding function for correction, thus exceeding the capabilities of most existing coding schemes for limited magnitude errors. The SEC-DAEC code is used to detect the cell in error and correct some bits, while the IP bits identify the remaining erroneous bits in the memory cell. The use of these simple codes results in an efficient implementation of the decoder compared to existing techniques as shown by the evaluation results presented in this paper. The proposed scheme is also competitive in terms of number of parity check bits and memory redundancy. Therefore, the proposed IP-DAEC scheme is a very efficient alternative to protect and correct MLC memories from limited magnitude errors.

Low Delay 3-Bit Burst Error Correction Codes

The increasing importance of Multiple Cell Upsets (MCUs) in modern memories has spurred research on error correction codes that can correct adjacent bit errors. For example, Double Adjacent Error Correction (DAEC), 3-bit burst and 4-bit burst codes have been proposed in the last years. However, as the error correction capabilities are increased so is the complexity of the encoder and decoder circuits. This directly impacts the encoding and decoding delay and thus limits the use of the codes in high speed memories. To reduce the complexity, some techniques have been proposed recently. Those include more advanced optimization programs to find codes with a lower number of ones in the parity check matrix or the interleaving of data and parity check bits to simplify the decoding. In this paper, those techniques are combined to design more efficient 3-bit burst error correction codes. The encoders and decoders for the proposed codes have been implemented and compared with the state of the art 3-bit burst error correction codes. The results show that the new codes reduce the encoder and decoder delay significantly. Therefore, the proposed codes provide memory designers with a more efficient option to implement protection against 3-bit burst errors for high speed memories.

Optimizing the Implementation of SEC–DAEC Codes in FPGAs

Single error correction and double-adjacent error correction (SEC–DAEC) codes are a type of error correction codes (ECCs) capable of correcting single and double-adjacent errors. They are useful in applications where multiple adjacent errors may occur, such as space or avionics. ECC encoders and decoders have a regular structure that makes it easier to accommodate them into field-programmable gate arrays (FPGAs). This brief proposes methods to optimize the decoder of SEC–DAEC codes when implemented in an FPGA, reducing the resource utilization when compared with the conventional implementations.

On the Minimum Redundancy of SEC-DAEC-TAEC Binary Linear Block Codes

The redundancy $n-k$ of an $(n,k) $ binary linear block code capable of single error correction, double adjacent error correction and triple adjacent error correction (SEC-DAEC-TAEC) is lower bounded by $\log_2(3n-2)$ . Recently, researchers have tried to find minimum redundancy codes which achieve equality in this lower bound using computer search and failed. In this letter, we prove that such codes do not exist for any $n$ and $k$ . This results in the tighter lower bound of $n-k \geq \log_2(3n-1)$ on the redundancy of SEC-DAEC-TAEC codes.

Designing scrubbing strategy for memories suffering MCUs through the selection of optimal interleaving distance

As technology scales, multiple cell upsets (MCUs) have shown prominent effect, thus affecting the reliability of memory to a great extent. Ideally, the interleaving distance (ID) should be chosen as the maximum expected MCU size. In order to mitigate MCU errors, interleaving schemes together with single error correction (SEC) codes can be used to provide the greatest protection. In this paper, we propose the use of scrubbing sequences to improve memory reliability. The key idea is to exploit the locality of the errors caused by a MCU to make scrubbing more efficient. The single error correction, double error detection, and double adjacent error correction (SEC-DEDDAEC) codes have also been used. A procedure is presented to determine a scrubbing sequence that maximises reliability. An algorithm of scrubbing strategy, which keeps the area overhead and complexity as low as possible without compromising memory reliability, is proposed for the optimal interleaving distance, which should be maximised under some conditions. The approach is further applied to a case study and results show a significant increase in the mean time to failure (MTTF) compared with traditional scrubbing.

A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes

Radiation-induced soft errors are a major reliability concern for memories. To ensure that memory contents are not corrupted, single error correction double error detection (SEC-DED) codes are commonly used, however, in advanced technology nodes, soft errors frequently affect more than one memory bit. Since SEC-DED codes cannot correct multiple errors, they are often combined with interleaving. Interleaving, however, impacts memory design and performance and cannot always be used in small memories. This limitation has spurred interest in codes that can correct adjacent bit errors. In particular, several SEC-DED double adjacent error correction (SEC-DED-DAEC) codes have recently been proposed. Implementing DAEC has a cost as it impacts the decoder complexity and delay. Another issue is that most of the new SEC-DED-DAEC codes miscorrect some double nonadjacent bit errors. In this brief, a new class of SEC-DED-DAEC codes is derived from orthogonal latin squares codes. The new codes significantly reduce the decoding complexity and delay. In addition, the codes do not miscorrect any double nonadjacent bit errors. The main disadvantage of the new codes is that they require a larger number of parity check bits. Therefore, they can be useful when decoding delay or complexity is critical or when miscorrection of double nonadjacent bit errors is not acceptable. The proposed codes have been implemented in Hardware Description Language and compared with some of the existing SEC-DED-DAEC codes. The results confirm the reduction in decoder delay.

Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs

As technology scaling increases embedded static random access memory bit-cell density, the number of soft errors due to radiation-induced multiple-bit upsets (MBUs) also increases. Traditionally, these errors have been addressed using a simple error correction code (ECC) combined with word interleaving. With continued scaling, however, errors beyond this setup begin to emerge. Although more powerful ECCs exist, they come at an increased overhead in terms of area and latency. Additionally, interleaving adds complexity to the system and may not always be feasible for the given architecture. In this brief, a set of double adjacent error correction (DAEC) codes is modified to provide triple adjacent error correction for a cost of zero additional check-bits over the code's DAEC equivalent, yielding a 2.25× reduction in bit-level soft error rate for a 22-nm MBU error channel model. MATLAB simulation and HDL synthesis results are included for standard 16- and 32-data-bit memory word sizes and compared against existing codes.

Protection of On-chip Memory Systems against Multiple Cell Upsets Using Double-adjacent Error Correction Codes

Protection of On-chip Memory Systems against Multiple Cell Upsets Using Double-adjacent Error Correction Codes

A Method to Design SEC-DED-DAEC Codes With Optimized Decoding

Single error correction-double error detection- double adjacent error correction (SEC-DED-DAEC) codes have been proposed to protect SRAM devices from multiple cell upsets (MCUs). The correction of double adjacent errors ensures that the most common types of MCUs are corrected. At the same time, SEC-DED-DAEC codes require the same number of parity check bits as traditional SEC-DED codes. The main overhead associated with SEC-DED-DAEC codes is the increase in decoding complexity that can impact access time and circuit power and area. In this paper, a method to design SEC-DED-DAEC codes with optimized decoding is presented and evaluated. The proposed scheme starts by setting some constraints on the parity check matrix of the codes. Those constraints are then used to simplify the decoding. The proposed scheme has been implemented and evaluated for different word-lengths. The results show that, for data words of 32 bits, the scheme can be implemented with the same number of parity check bits as SEC-DED codes. For 16 and 64 bits words, an additional parity check bit is required, making the scheme less attractive. With the proposed method, the decoders can be optimized for area or speed. Both implementations are evaluated and compared with existing SEC-DED-DAEC decoders. The results show that the proposed decoders reduce significantly the circuit area, power, and delay. Index Terms—SEC-DAEC codes, Multiple Cell Upsets (MCUs), error correction codes, SRAM memories.

A New SEC-DED Error Correction Code Subclass for Adjacent MBU Tolerance in Embedded Memory

The reliability concern associated with radiation-induced soft errors in embedded memories increases as semiconductor technology scales deep into the sub-40-nm regime. As the memory bit-cell area is reduced, single event upsets (SEUs) that would have once corrupted only a single bit-cell are now capable of upsetting multiple adjacent memory bit-cells per particle strike. While these error types are beyond the error handling capabilities of the commonly used single error correction double error detection (SEC-DED) error correction codes (ECCs) in embedded memories, the overhead associated with moving to more sophisticated double error correction (DEC) codes is considered to be too costly. To address this, designers have begun leveraging selective bit placement to design SEC-DED codes capable of double adjacent error correction (DAEC) or triple adjacent error detection (TAED). These codes can be implemented for the same check-bit overhead as the conventional SEC-DED codes; however, no codes have been developed that use both DAEC and TAED together. In this paper, a new ECC scheme is introduced that provides not only the basic SEC-DED coverage but also both DAEC and scalable adjacent error detection ( xAED) with a reduction in miscorrection probability as well. Codes capable of up to 11-bit AED have been developed for both 16- and 32-bit standard memory word sizes, and a (39, 32) SEC-DED-DAEC-TAED code implementation that uses the same number of check-bits as a conventional 32-data-bit SEC-DED code is presented.

Single error correction, double error detection and double adjacent error correction with no mis-correction code

Single error correction, double error detection and double adjacent error correction with no mis-correction code

Correct Bluetooth EDR FEC performance with SEC-DAEC decoding

By selecting from Bluetooth's enhanced data rate (EDR) packet types according to channel conditions, optimal data-rates are approached, especially if forward error control (FEC) is extended to EDR. Correct calculation of these packet types is presented, which also accounts for double adjacent error correction (DAEC) in addition to conventional single error correction (SEC).