Dominant Trapping Sets Research Articles

Doped low-density parity-check codes

In this paper, we propose a doping approach to lower the error floor of Low-Density Parity-Check (LDPC) codes. The doping component is a short block code in which the information bits are selected from the coded bits of the dominant trapping sets of the LDPC code. Accordingly, an algorithm for selecting the information bits of the short code is proposed, and a specific two-stage decoding algorithm is presented. Simulation results demonstrate that the proposed doped LDPC code achieves up to 2.0 ​dB gain compared with the original LDPC code at a frame error rate of 10−6. Furthermore, the proposed design can lower the error floor of original LDPC codes.

Effective identification of dominant fully absorbing sets for Raptor‐like LDPC codes

AbstractThe error‐rate floor of low‐density parity‐check (LDPC) codes is attributed to the trapping sets of their Tanner graphs. Among them, fully absorbing sets dominantly affect the error‐rate performance, especially for short blocklengths. Efficient methods to identify the dominant trapping sets of LDPC codes were thoroughly researched as exhaustively searching them is NP‐hard. However, the existing methods are ineffective for Raptor‐like LDPC codes, which have many types of trapping sets. An effective method to identify dominant fully absorbing sets of Raptor‐like LDPC codes is proposed. The search space of the proposed algorithm is optimized into the Tanner subgraphs of the codes to afford time‐efficiency and search‐effectiveness. For 5G New Radio (NR) base graph (BG) 2 LDPC codes for short blocklengths, the proposed algorithm finds more dominant fully absorbing sets within one seventh of the computation time of the existing search algorithm, and its search‐effectiveness is verified using importance sampling. The proposed method is also applied to 5G NR BG1 LDPC code and Advanced Television Systems Committee 3.0 type A LDPC code for large blocklengths.

Construction of Time Invariant Spatially Coupled LDPC Codes Free of Small Trapping Sets

In this paper, we propose a design technique for the construction of variable-regular time-invariant spatially-coupled low-density parity-check (SC-LDPC) codes with small constraint length and low error floor. The proposed technique reduces the error floor by imposing simple constraints on the short cycles in the code's Tanner graph, which in turn, result in the elimination of the most dominant trapping sets of the code. In some cases, we also derive lower bounds on the syndrome former memory for satisfying such constraints. The designed codes are superior to the state-of-the-art in terms of error floor performance and/or decoding complexity and latency.

Error Floor Estimation of LDPC Coded Modulation Systems Using Importance Sampling

One of the key weaknesses of low-density parity-check (LDPC) codes is the error floor that they typically exhibit at high signal-to-noise ratios (SNRs). Such an error floor is usually attributed to problematic structures known as trapping sets (TSs). The overwhelming majority of existing error floor estimation schemes consider the case of binary phase shift keying (BPSK) signalling. Unfortunately, these schemes are not readily extensible to estimate the error floor of high order LDPC coded modulation systems considered herein. To provide such a scheme, in this work, we use mean-shift importance sampling (MS-IS) to develop a novel error floor estimation methodology for high-order pulse amplitude modulation (PAM) and quadrature amplitude modulation (QAM) LDPC coded systems. First, a computationally efficient graphical-based approach is used to identify the TSs of a given LDPC code. Subsequently, a novel analytical approach is devised to identify the TSs that are likely to have a higher contribution in the error floor. These TSs are referred to as potentially dominant TSs (PDTSs). Finally, a new methodology for categorizing the PDTSs into equivalence classes is developed. A representative PDTS of each equivalence class is chosen and an MS-IS framework is devised to obtain the error rate corresponding to each equivalence class. To arrive at the desired MS-IS scheme, we develop an algorithm that invokes the geometry of the constellation to determine the MS value. In contrast with the conventional MS-IS method used in BPSK signalling, in the proposed MS-IS scheme, the MS value is a variable that is determined based on the TS and the transmitted codeword. The computational complexity of the three main steps of our methodology, viz. extracting the PDTSs, determining the MS values, and applying the MS-IS scheme, depends merely on the size of the constellation and the structure of the code, but not on the SNR. Numerical simulations confirm the efficacy and accuracy of the proposed technique at different SNRs.

Construction of Irregular Protograph-Based QC-LDPC Codes With Low Error Floor

In this article, we design finite-length irregular protograph-based quasi-cyclic (QC) low-density parity-check (LDPC) codes with good waterfall performance and low error floor. To achieve a low error floor, we eliminate a targeted set of dominant elementary trapping sets (ETS) ${\mathcal{ L}}$ in the Tanner graph of the code. For a given rate and girth, the codes are designed to be free of the largest set of problematic ETSs for a given block length, or to have the shortest block length while a given set of ETSs is avoided. The design is based on a search algorithm that identifies whether any instance of any structure within ${\mathcal{ L}}$ exists in the Tanner graph of the constructed code or not. The search algorithm performs this task with minimal complexity, making it feasible to construct practical codes by running the search algorithm a large number of times. Simulation results are provided to demonstrate the superior performance of designed codes compared to similar state-of-the-art irregular QC-LDPC codes.

Spatially Coupled LDPC Codes With Small Constraint Length and Low Error Floor

In this letter, we design time-invariant spatially coupled low-density parity-check (SC-LDPC) codes with small constraint length and low error floor. For this, we modify the codes in the literature that have (close to) minimal constraint length for a given degree distribution and girth, to improve their error floor. This is performed by eliminating (or minimizing the multiplicity of) some of the dominant trapping sets (TSs) of the codes and/or increasing the minimum distance. To reduce the multiplicity of the TSs effectively and efficiently, we devise a technique based on the parent/child relationship between TSs that aims at successively minimizing the multiplicity of TSs depending on their harmfulness.

On the Construction of Regular QC-LDPC Codes With Low Error Floor

Quasi-cyclic low-density (QC-LDPC) codes benefit from efficient encoding hardware and display excellent error correcting performance. Therefore, they have been accepted into the 5G standards in addition to being potential candidates for next generation mobile systems. However, dominant trapping sets in the Tanner graphs cause some failures for the iterative decoding algorithm. In this letter, we propose a simulated annealing based method to find regular QC-LDPC codes without dominant trapping sets and have good error floor performance. Simulation results show that our proposed method generates QC-LDPC codes that have the best trapping sets distribution among recent works and better frame rate performance than others.

Breaking the Trapping Sets in LDPC Codes: Check Node Removal and Collaborative Decoding

Trapping sets strongly degrade performance of low-density parity check (LDPC) codes in the low-error-rate region. This creates significant difficulties for the deployment of LDPC codes to low-error-rate applications such as storage and wireless systems with no or limited retransmission options. We propose a novel technique for breaking trapping sets based on collaborative decoding that utilizes two different decoding modes. While the main decoding mode executes message passing based on the original parity check matrix of the corresponding LDPC code, the sub-decoding mode operates on a modified parity check matrix formed by removing a portion of check nodes in the factor graph representation of the given code. The modified parity check matrix is designed to promote a passing of correct information into erroneous variable nodes in the trapping set. Theoretical properties of the proposed trapping-set-breaking technique have been established based on the notion of the improved separation for the trapped variable nodes. Simulation results show that the proposed collaborative LDPC decoding scheme switching between the two decoding modes back and forth effectively breaks dominant trapping sets of various known types of regular and irregular LDPC codes.

LDPC Decoding Scheduling for Faster Convergence and Lower Error Floor

This paper presents a maximum mutual information increase (M <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> )-based algorithm that can be used to arrange low-density parity-check (LDPC) decoding schedules for faster convergence, where the increase is used to guide the arrangement of the fixed decoding schedule. The predicted mutual information for the messages to be updated is used in the calculation of the increase. By looking ahead for several decoding stages, a high-order prediction can be realized, which can then be used to devise a schedule with an even faster convergence. For a single received frame, different decoding results can be obtained using different schedules, and, hence, schedule diversity, that lowers the error floor resultant from the dominant trapping sets, is proposed. By adopting the M <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -based schedule together with the schedule diversity, both the convergence speed in the waterfall region and the error-rate in the floor region can be improved.

Fast and Accurate Error Floor Estimation of Quantized Iterative Decoders for Variable-Regular LDPC Codes

In this letter, we propose a fast and accurate technique to estimate the error floor of variable-regular low-density parity-check (LDPC) codes under quantized iterative decoding algorithms. The technique, which is based on enumerating the dominant elementary trapping sets of the code, provides significant improvement over existing methods in terms of speed and accuracy.

Lowering Error Floors of Systematic LDPC Codes Using Data Shortening

In this paper, data shortening methods for lowering error floors of systematic LDPC codes are proposed. Rather than attempting to analyze trapping (or stopping) sets of a given LDPC code rigorously, we search information bits associated with dominant trapping (or stopping) sets of systematic LDPC codes through simulation under various channels. Then, proper information bits forming dominant trapping (or stopping) sets are selected and known values are assigned to them before encoding to weaken the effect of dominant trapping (or stopping) sets. To decode codewords, fixed known values are assigned to the selected information bits, which gives rise to the disconnection of some edges in dominant trapping (or stopping) sets. Through simulation, it is shown that the proposed schemes result in remarkably better performance, especially at the error floor region, than the base LDPC codes under various channels with negligible loss of code rate.

Efficient Algorithm for Finding Dominant Trapping Sets of LDPC Codes

This paper presents an efficient algorithm for finding the dominant trapping sets of a low-density parity-check (LDPC) code. The algorithm can be used to estimate the error floor of LDPC codes or as a tool to design LDPC codes with low error floors. For regular codes, the algorithm is initiated with a set of short cycles as the input. For irregular codes, in addition to short cycles, variable nodes with low degree and cycles with low approximate cycle extrinsic message degree (ACE) are also used as the initial inputs. The initial inputs are then expanded recursively to dominant trapping sets of increasing size. At the core of the algorithm lies the analysis of the graphical structure of dominant trapping sets and the relationship of such structures to short cycles, low-degree variable nodes, and cycles with low ACE. The algorithm is universal in the sense that it can be used for an arbitrary graph and that it can be tailored to find a variety of graphical objects, such as absorbing sets and Zyablov-Pinsker trapping sets, known to dominate the performance of LDPC codes in the error floor region over different channels and for different iterative decoding algorithms. Simulation results on several LDPC codes demonstrate the accuracy and efficiency of the proposed algorithm. In particular, the algorithm is significantly faster than the existing search algorithms for dominant trapping sets.

A PEG Construction of Finite-Length LDPC Codes with Low Error Floor

The progressive-edge-growth (PEG) algorithm of Hu et al. is modified to improve the error floor performance of the constructed low-density parity-check (LDPC) codes. To improve the error floor, the original PEG algorithm is equipped with an efficient algorithm to find the dominant elementary trapping sets (ETS's) that are added to the Tanner graph of the under-construction code by the addition of each variable node and its adjacent edges. The aim is to select the edges, among the candidates available at each step of the original PEG algorithm, that prevent the creation of dominant ETS's. The proposed method is applicable to both regular and irregular variable node degree distributions. Simulation results are presented to demonstrate the superior ETS distribution and error floor performance of the constructed codes compared to similar codes constructed by the original and other modifications of the PEG algorithm.

Lowering the Error Floor of LDPC Codes Using Cyclic Liftings

Cyclic liftings are proposed to lower the error floor of low-density parity-check (LDPC) codes. The liftings are designed to eliminate dominant trapping sets of the base code by removing the short cycles which are part of the trapping sets. We derive a necessary and sufficient condition for the cyclic permutations assigned to the edges of a cycle ξ of length <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">l</i> (ξ) in the base graph such that the inverse image of ξ in the lifted graph consists of only cycles of length strictly larger than <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">l</i> (ξ). The proposed method is universal in the sense that it can be applied to any LDPC code over any channel and for any iterative decoding algorithm. It also preserves important properties of the base code such as degree distributions, and in some cases, the code rate. The constructed codes are quasi-cyclic and thus attractive from a practical point of view. The proposed method is applied to both structured and random codes over the binary symmetric channel (BSC). The error floor improves consistently by increasing the lifting degree, and the results show significant improvements in the error floor compared to the base code, a random code of the same degree distribution and block length, and a random lifting of the same degree. Similar improvements are also observed when the codes designed for the BSC are applied to the additive white Gaussian noise (AWGN) channel.

Fast Performance Evaluation Method of LDPC Codes

This paper shows a fast estimation method of very low error rate of low-density parity-check (LDPC) codes. No analytical tool is available to evaluate performance of LDPC codes, and the traditional Monte Carlo simulation methods can not estimate the low error rate of LDPC codes due to the limitation of time. To conquer this problem, we propose another simulation method which is based on the optimal simulation probability density function (PDF). The proposed simulation PDF can also avoid the dependency between the simulation time and the number of dominant trapping sets, which is the problem of some fast simulation methods based on the error event simulation method. Additionally, we show some numerical examples to demonstrate the effectiveness of the proposed method. The simulation time of the proposed method is reduced to almost less than 1/10 of that of Cole et al.'s method under the condition of the same accuracy of the estimator.

On the Dynamics of the Error Floor Behavior in (Regular) LDPC Codes

It is shown that dominant trapping sets of regular low-density parity-check (LDPC) codes, so-called absorption sets, undergo a two-phased dynamic behavior in the iterative message-passing decoding algorithm. Using a linear dynamic model for the iteration behavior of these sets, it is shown that they undergo an initial geometric growth phase which stabilizes in a final bit-flipping behavior where the algorithm reaches a fixed point. This analysis is shown to lead to very accurate numerical calculations of the error floor bit error rates down to error rates that are inaccessible by simulation. The topology of the dominant absorption sets of an example code, the IEEE 802.3an (2048,1723) regular LDPC code, are identified and tabulated using topological relationships in combination with search algorithms.