Distributed Arithmetic Algorithm Research Articles

"Enhanced DA Algorithm for FIR Filter Design and FPGA Implementation"

Abstract: This study looks into the difficulties of using the Distributed Arithmetic (DA) method for Finite Impulse Response (FIR) filters on Field-Programmable Gate Arrays (FPGAs). It focuses on how coefficients are represented, balancing precision using fixed-point arithmetic and quantization. The research explores ways to optimize memory use, aiming to store data more efficiently within FPGA resources and reduce memory needs. To speed up computations, it examines how to make accessing lookup tables faster and suggests improvements in design. The study also considers how to manage FPGA resources effectively, balancing latency, throughput, and resource use. It looks at specific improvements to the DA method for FIR filters to make better use of resources and enhance performance. Overall, this work provides insights and solutions for algorithm design, memory use, lookup table speed, and FPGA architecture to make DA-based FIR filter implementations on FPGAs more efficient.

The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW

The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW

Design and Implementation of an Area and Power-efficient Reconfigurable Hearing Aid using Interpolated Sub-band Distribution Technique

A hearing aid is a compensatory device that helps in overcoming various hearing disabilities. Since different people possess different hearing problems and the requirement gets changed over time, it is necessary to design a reconfigurable hearing aid which is generic in nature such that it supports various hearing disabilities without modifying the hardware components. The objective of the paper is to implement a reconfigurable digital hearing aid which is hardware efficient and it is auto-adaptable to disabilities ranging from mild to severe intensities. Since multipliers and LUTs are power hungry elements, we have proposed a design which is multiplier less and LUT-less DA Architecture. The prototype filter is a FIR filter which is designed using LUT-less Distributed Arithmetic Algorithm that saves 64% of logic elements & memory and 76% of power utilization. As it is a multiplier-less as well as LUT- less architecture, hence this can be claimed to be area and power efficient design. The delays and matching errors are within the standard limits which are accepted globally. The input audio spectrum is divided into three regions and for each region there are four different filter banks are proposed using interpolated sub-bands distribution. Xilinx System Generator is used to implement the proposed design. The proposed design requires least manual configuration for selection of filter banks for audiogram matching which also minimizes the trial-anderror method to establish the best match with the person’s audiogram.

Design and Implementation of LMS Adaptive FIR Filter Based on OBC Distributed Arithmetic Algorithm with MCSLA

Design and Implementation of LMS Adaptive FIR Filter Based on OBC Distributed Arithmetic Algorithm with MCSLA

A comparative analysis of 1-level multiplier-free discrete wavelet transform implementations on FPGAs

In this article, we investigated the design and implementation aspects of multilevel discrete wavelet transform (DWT) by employing a finite impulse response filter on field programmable gate array platform. We presented two key multiplication-free architectures, namely, the distributed arithmetic algorithm (DAA) and residue number system (RNS). Our goal is to estimate the performance requirements and hardware resources for each approach, allowing for selection of the proper algorithm and implementation of multilevel DAA- and RNS-based DWT. The design has been implemented and synthesized in Xilinx Virtex 6 ML605, taking advantage of Virtex 6?s embedded block RAMs. The results reveal that the DAA-based approach is appropriate for a small number of filter taps, while the RNS-based approach would be more appropriate for more than 10 filter taps, yet both DAA- and RNS-based approaches offer high signal quality with peak signal-to-noise ratio as 73.5 and 56.5 dB, respectively.

FPGA Implementation of FFT Architecture using Modified Radix-4 Algorithm

This paper presents an area efficient multiplier less parallel radix 4 Decimation In Frequency-Fast Fourier Transform (DIF-FFT) processor using Distributed Arithmetic Algorithm (DAA). Many numbers of complex computations involved in the radix-2 algorithm have driven to the usage of higher radix algorithms such as radix 4 and radix 8. DAA is an appropriate technique for eliminating the complex multiplications in FFT/IFFT processor by using look-up tables (LUTs) and shift-accumulators. Higher radix FFT algorithm along with DAA provides low area high-speed FFT/IFFT processor. The proposed multiplier less 64 point radix 4 FFT/IFFT processor using DAA algorithm is designed, implemented and simulated in Altera DE2 EP2C35F672C6 device. Hardware implementation of the proposed DAA based 64 point FFT processor has a total of 2.77% FPGA utilization which is 36.62% lesser than conventional FFT/IFFT processors and it operates at 46.30Gbps.

Multiplier Design and Performance Estimation with Distributed Arithmetic Algorithm

A new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1’scomplement- based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. Moreover, depending on data switching activity statistically reduce the power consumption.

Implementation of High Speed Operating FIR Filter with DA Algorithm Comparing Results with MAC Algorithm and Simple FIR Filter Result

Recent years there has been a increasing trend to implement digital signal processing functions in Field ProgrammableGate Array (FPGA). therefor, we need to put great effort in designing efficient architectures for digital signal processing functionssuch as FIR filters, which are widely used in audio and video signal processing, telecommunications etc. We are going to present amethod for implementing high speed Finite Impulse Response (FIR) filters using MAC (MULTIPLY AND ACCUMULATE) andDistributed Arithmetic (DA) method. MAC is a conventional FIR filter In these method adders, multipliers and delay elements areused. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general symmetric version of an FIR filter dueto its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performanceof the DA technique for FIR filter design is analyzed and the results are compared to the MAC design technique.

Implementation of High Speed Operating FIR Filter with DA Algorithm Comparing Results with MAC Algorithm and Simple FIR Filter Result

Recent years there has been a increasing trend to implement digital signal processing functions in Field Programmable Gate Array (FPGA). therefor, we need to put great effort in designing efficient architectures for digital signal processing functions such as FIR filters, which are widely used in audio and video signal processing, telecommunications etc. We are going to present a method for implementing high speed Finite Impulse Response (FIR) filters using MAC (MULTIPLY AND ACCUMULATE) and Distributed Arithmetic (DA) method. MAC is a conventional FIR filter In these method adders, multipliers and delay elements are used. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general symmetric version of an FIR filter due to its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performance of the DA technique for FIR filter design is analyzed and the results are compared to the MAC design technique.

Fast Fourier Transformation Realistion with Distributed Arithmetic Algorithm

Fast Fourier Transformation Realistion with Distributed Arithmetic Algorithm

Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm

In this Paper, we propose a low-power multiplier design methodology which has multiplier-andaccumulator for high speed and by adopting the new Shift and adds implementation approach. This multiplier is designed by equipping the Power Suppression Technique on DA (distributed arithmetic) algorithm. The Shift and adder will avoid the unwanted addition and thus minimize the switching power dissipation, the performance was improved. When the DA algorithm is directly applied in FPGA (field programmable gate array) to realize FIR (finite impulse response) filter, it is easy to achieve the best configuration in the coefficient of FIR filter, the storage resources and the computing speed. The parallel FIR structures can lead to significant hardware savings for symmetric convolution in odd length from the existing FFA parallel FIR filter, particularly when the length of the filter is large. According to this, the paper provides the detailed analysis and discussion in the algorithm, the memory size and the look up table speed. Also, the corresponding optimization and improvement measures are discussed. The design results of simulation and test show that this method greatly reduces the FPGA hardware resource and the high speed filtering is achieved. The design has a big breakthrough compared to the traditional FPGA realization.

Design of High Performance Modified Wave pipelined DAA Filter with Critical Path Approach

In this paper, a new high speed control circuit is proposed which will act as a critical path for the data which will go from input to output to improve the performance of wave pipelining circuits The wave pipelining is a method of high performance circuit designs which implements pipelining in logic without the use of intermediate registers. Wave pipelining has been widely used in the past few years with a great deal of significant features in technology and applications. It has the ability to improve speed, efficiency, economy in every aspect which it presents. Wave pipelining is being used in wide range of applications like digital filters, network routers, multipliers, fast convolvers, MODEMs, image processing, control systems, radars and many others. In previous work, the operating speed of the wave-pipelined circuit can be increased by the following three tasks: adjustment of the clock period, clock skew and equalization of path delays. The path-delay equalization task can be done theoretically, but the real challenge is to accomplish it in the presence of various different delays. So, the main objective of this paper is to solve the path delay equalization problem by inserting the control circuit in wave pipelined based circuit which will act as critical path for the data that moves from input to output. The proposed technique is evaluated for DSP applications by designing 4- tap FIR filter using Distributed arithmetic algorithm (DAA). Then comparison of this design is done with 4-tap FIR filter designs using conventional pipelining and non pipelining. The synthesis and simulation results based on Xilinx ISE Navigator 12.3 shows that wave pipelined DAA based filter is faster by a factor of 1.43 compared to non pipelined one and the conventional pipelined filter is faster than non pipelined by factor of 1.61 but at the cost of increased logic utilization by 200 %. So, the wave-pipelined DA filters designed with the proposed control circuit can operate at higher frequency than that of non-pipelined but less than that of pipelined. The gain in speed in pipelined compared to that of wavepipelined is at the cost of increased area and more dissipated power. When latency is considered, wavepipelined design filters with the proposed scheme are having the lowest latency among three schemes designed.

Implementation of High Speed FIR Filter using Serial and Parallel Distributed Arithmetic Algorithm

This paper describes the implementation of highly efficient multiplierless serial and parallel distributed arithmetic algorithm for FIR filters. Distributed Arithmetic (DA) had been used to implement a bit-serial scheme of a general symmetric version of an FIR filter due to its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performance of the bitserial and bit-parallel DA technique for FIR filter design is analyzed and the results are compared to the conventional FIR filter design techniques. The proposed algorithm has been synthesized with Xilinx ISE 10.1i and implemented as a target device of Spartan3E FPGA.

Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits

Operating frequencies of combinational logic circuits can be increased using Wave-Pipelining (WP), by adjusting the clock periods and clock skews. In this article, Built-In Self-Test (BIST) and System-on-Chip (SOC) approaches are proposed for automating this adjustment and they are evaluated by implementation of filters using a Distributed Arithmetic Algorithm (DAA) and sinewave generator using the COordinate Rotation DIgital Computer (CORDIC). Both the circuits are studied by adopting three schemes: wave-pipelining, pipelining, and nonpipelining. Xilinx Spartan II and Altera Cyclone II FPGAs with Nios II soft-core processor are used for implementation of the circuits with the BIST and SOC approaches, respectively. The proposed schemes increase the speed of the WP circuits by a factor of 1.19--2.6 compared to nonpipelined circuits. The pipelined circuits achieve higher speed than the WP circuits by a factor of 1.13--3.27 at the cost of increase in area and power. When both pipelined and WP circuits are operated at the same frequency, the former dissipates more power for circuits with higher word sizes and for moderate logic depths. The observation regarding the dependence of the superiority of the WP circuits with regard to power dissipation on the logic depth is one of the major contributions of this article.

Design and FPGA Implementation of Self-Tuned Wave-Pipelined Filters with Distributed Arithmetic Algorithm

Wave-pipelining enables a digital circuit to be operated at a higher frequency. In the literature, only trial-and-error and manual procedures are adopted for the choice of the optimum value of clock frequency and clock skew between the input and output registers of wave-pipelined circuits. One of the major contributions of this paper is the proposal for automating the above procedure. A second contribution is the study of how logic depths determine the superiority of wave-pipelining over pipelining with regard to power dissipation. For the study and implementation of wave-pipelined circuits, filters using the distributed arithmetic algorithm are considered. In this paper, two automation schemes are proposed for the implementation of the wave-pipelined filters on both Xilinx and Altera field programmable gate arrays (FPGAs). In the first scheme, a self-tuning finite state machine (FSM) is used to choose the clock skew and clock period for I/O registers between the wave-pipelined blocks. In the second approach, an on-chip soft-core processor is used to choose the clock skew and clock period. To test the efficacy of the schemes proposed, filters with different taps are implemented using three schemes: synchronous pipelining, sub-optimal wave-pipelining and no pipelining (i.e. using neither synchronous pipelining nor wave-pipelining). From the implementation results, it is observed that wave-pipelined distributed arithmetic (DA) filters are faster by a factor of 1.31–1.61 compared to non-pipelined DA filters. The synchronous pipelined DA filters are in turn faster by a factor of 1.73–3.27 compared to the wave-pipelined DA filters. The increased speeds are achieved in the pipelined filters at the cost of an increase in the number of slices by 15–33% and in the number of registers by 350–530%. To compare the power dissipation, both pipelined and wave-pipelined DA filters are tested by operating them at the same frequency. For medium logic depths, the wave-pipelined DA filters dissipate less power than pipelined filters.

Design of Digital FIR Filter Based on Dynamic Distributed Arithmetic Algorithm

Design of Digital FIR Filter Based on Dynamic Distributed Arithmetic Algorithm

Design and FPGA Implementation of Self Tuned Wavepipelined Filters

In this paper, a novel scheme is proposed for FPGA implementation of a wavepipelined filter using Distributed Arithmetic Algorithm (DAA). To make the circuit independent of fabrication variations in the parameters, a sub-optimal wavepipelined scheme is proposed for the various combinational blocks of the DA filter. A self tuning FSM is in-built to choose the clock skew and clock period for I/O registers between the wavepipelined blocks. To test the efficacy of the scheme proposed, three filters with 4, 8 and 10 taps respectively are implemented using DAA approach on Xilinx Spartan II XC2S100-5PQ208 device. The filters are implemented using three schemes: synchronous pipelining, sub-optimal wavepipelining and no pipelining (i.e., using neither synchronous pipelining nor wavepipelining). From the implementation results, it is observed that wavepipelined DA filters are faster by a factor of 1.31–1.61 compared to non-pipelined DA filters. The synchronous pipelined DA filters are in turn faster by a factor of 1.73-2.06 compared to the wavepipelined DA filters. The increased speeds are achieved by increasing the number of slices by 25%-33%, the number of registers by 350-530% and power dissipation by 107-167%. The delay-register product of the wavepipelined DA filters are reduced by a factor of 2.64-3.06 compared to the pipelined DA filters. The technique proposed in this paper is also applicable for ASICs and FPGAs from other vendors.

An efficient serial distributed arithmetic algorithm for FPGA implementation of digital up conversion

This article deals with a computationally efficient serial distributed arithmetic algorithm producing a device efficient field programmable gate array implementation. The proposed algorithm takes half the computations time as compared to the conventional symmetric algorithms. The algorithm is analyzed for a direct conversion transmitter of ionospheric radar. Matching and buffering criterion are used to reduce the arithmetic process. The algorithm can be extended to applications with similar characteristics, particularly for System On Chip (SOC) techniques. © 2005 Wiley Periodicals, Inc. Complexity 11: 24–29, 2005

New Distributed Arithmetic Algorithm for Low-Power FIR Filter Implementation

This letter proposes a new distributed arithmetic (DA) algorithm for low-power finite-impulse response (FIR) filter implementation. The characteristic of the proposed algorithm is that the FIR filters using the proposed algorithm do not need to employ two's complement representation in lookup tables as well as multiply-and-accumulation blocks. Thus, the proposed algorithm can minimize the dynamic power consumption of the FIR filters. The experimental results show that the lowpass FIR filter using the proposed algorithm achieves 29% and 26% power consumption reduction compared to that using the conventional algorithm for zero-mean random inputs and speech inputs, respectively.

New distributed arithmetic algorithm and its application to IDCT

Distributed arithmetic (DA) has been widely used to implement inner product computations with a fixed input. Conventional ROM-based DA suffers from large ROM requirements. A new DA algorithm is proposed that expands the fixed input instead of the variable input into bit level as in ROM-based DA. Thus the new DA algorithm can take advantage of shared partial sum-of-products and sparse nonzero bits in the fixed input to reduce the number of computations. Unlike ROM-based DA that stores the precomputed results the new DA algorithm uses a predefined structure to compute results. When applied to a 1-D eight-point DCT system the new DA algorithm only needs 30% of hardware area and has faster speed as compared with ROM based DA. To illustrate the efficiency of the proposed algorithm a 2-D IDCT chip was implemented using 0.8 /spl mu/m SPDM CMOS technology. The chip with size 4575/spl times/5525 /spl mu/m can deliver a processing rate of 50 Mpixels per second.