Discrete-time Cellular Neural Networks Research Articles

A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing

For real-time image-processing applications, a highly parallel system that exploits parallelism is desirable. A content addressable memory (CAM), or an associative processor, that can perform various types of parallel processing with words as the basic unit is a promising component for creating such a system because of its suitability for LSI implementation. Conventional CAM LSI's, however, have neither efficient function nor enough capacity for pixel-parallel processing. This paper describes a fully parallel 1-Mb CAM LSI. It has advanced functions for processing various pixel-parallel algorithms, such as mathematical morphology and discrete-time cellular neural networks. Moreover, since it has 16-K words, or processing elements (PEs), which can process 128/spl times/128 pixels in parallel, a board-sized pixel-parallel image-processing system can be implemented using several chips. A chip capable of operating at 56 MHz and 2.5 V was fabricated using 0.25-/spl mu/m full-custom CMOS technology with five aluminum layers. A total of 15.5 million transistors have been integrated into a 16.1/spl times/17.0 mm chip. Typical power dissipation is 0.25 W. Processing performance of various update and data transfer operations is 3-640 GOPS. This CAM LSI will make a significant contribution to the development of compact, high-performance image-processing systems.

On the design of discrete-time cellular neural networks with circulant matrices

On the design of discrete-time cellular neural networks with circulant matrices

Convergence of discrete-time cellular neural networks with interlaced block-sequential dynamics

Some interlaced block-sequential modes of operation are introduced for discrete-time cellular neural networks (DTCNN), and the corresponding convergence conditions are investigated. It is proved that DTCNNs, under some block-sequential updating rules, result to be convergent when the feedback templates satisfy some restrictions rather milder than reciprocity or dominance, as required in synchronous mode. Moreover, the set of fixed points of the network results to be independent of the particular updating rule adopted. The drawback of desynchronization is a reduced speed of convergence, which however is tolerable in the usual case when the neighbourhood radius is small. Copyright © 1999 John Wiley & Sons, Ltd.

A DTCNN universal machine based on highly parallel 2-D cellular automata CAM/sup 2/

The discrete-time cellular neural network (DTCNN) is a promising computer paradigm that fuses artificial neural networks with the concept of cellular automaton (CA) and has many applications to pixel-level image processing. Although some architectures have been proposed for processing DTCNN, there are no compact, practical computers that can process real-world images of several hundred thousand pixels at video rates. So, in spite of its great potential, DTCNNs are not being used for image processing outside the laboratory. This paper proposes a DTCNN processing method based on a highly parallel two-dimensional (2-D) cellular automata called CAM/sup 2/. CAM/sup 2/ can attain pixel-order parallelism on a single PC board because it is composed of a content addressable memory (CAM), which makes it possible to embed enormous numbers of processing elements, corresponding to CA cells, onto one VLSI chip. A new mapping method utilizes maskable search and parallel and partial write commands of CAM/sup 2/ to enable high-performance DTCNN processing. Evaluation results show that, on average, CAM/sup 2/ can perform one transition for various DTCNN templates in about 12 microseconds. Also it can perform practical image processing through a combination of DTCNNs and other CA-based algorithms. CAM/sup 2/ is a promising platform for processing DTCNN.

Transformational DT-CNN design from morphological specifications

Morphology provides the algebraic means to specify operations on images. Discrete-time cellular neural networks (DT-CNNs) mechanize the execution of operations on images. The paper first shows the equivalence between morphological functions and DT-CNNs. Then, the argument is extended to the synthesis of optimal DT-CNN structures from complex morphological expressions. It is shown that morphological specifications may be freely derived, to be subsequently transformed and adopted to the needs of a specific target terminology. This process of technology mapping can be automated along the well-trodden path in CAD for microelectronics.

Linguistic flow in fuzzy discrete-time cellular neural networks and its stability

A type-III fuzzy discrete-time cellular neural network (FDTCNN) structure is presented to implement local linguistic dynamic systems. The theoretical results of equilibrium points and stability of this FDTCNN are presented. The state transient process of this FDTCNN is analyzed by using fuzzy mathematics, Markov chain, and graph theory. An efficient algorithm is presented to check the existence of globally stable equilibrium point. Examples in a two-cell FDTCNN are used to demonstrate theoretical results, Finally, designing examples of a 1-D FDTCNN are presented to simulate the traffic flow of a highway system. Computer simulation results are given.

Implementations of artificial neural networks using current-mode pulse width modulation technique

The use of a current-mode pulse width modulation (CM-PWM) technique to implement analog artificial neural networks (ANNs) is presented. This technique can be used to efficiently implement the weighted summation operation (WSO) that are required in the realization of a general ANN. The sigmoidal transformation is inherently performed by the nonlinear transconductance amplifier, which is a key component in the current integrator used in the realization of WSO. The CM-PWM implementation results in a minimum silicon area, and therefore is suitable for very large scale neural systems. Other pronounced features of the CM-PWM implementation are its easy programmability, electronically adjustable gains of neurons, and modular structures. In this paper, all the current-mode CMOS circuits (building blocks) required for the realization of CM-PWM ANNs are presented and simulated. Four modules for modular design of ANNs are introduced. Also, it is shown that the CM-PWM technique is an efficient method for implementing discrete-time cellular neural networks (DT-CNNs). Two application examples are given: a winner-take-all circuit and a connected component detector.

Virtual template expansion in cellular neural networksusingbackpropagation through time

A design method is proposed which allows the implementation of a discrete-time cellular neural network (CNN) with a virtual neighbourhood radius r > 1, using recursively r nearest-neighbour physical templates. The proposed approach, based on the idea of the unfolding of time and the backpropagation through the time learning algorithm, presents some advantages over existing methods which are illustrated by an example concerning a feature detector.

A global approach to the design of discrete-time cellular neural networks for associative memories

In this paper a global design method for associative memories using discrete-time cellular neural networks (DTCNNs) is presented. The proposed synthesis technique enables to realize associative memories with several advantageous features. First of all, grey-level as well as bipolar images can be stored. Moreover, the proposed approach generates networks with learning and forgetting capabilities. Finally, it is possible to design networks with any kind of predetermined interconnection structure. In particular, neighbourhoods without line crossings can be chosen, greatly simplifying the VLSI implementation of the designed DTCNNs. In the first part of this work a model of a multilevel threshold network is presented and a stability analysis is carried out using basic notions deriving from non-linear dynamical system theory. The synthesis procedure is then developed by means of a pseudoinversion technique, assuring learning and forgetting capabilities of the designed DTCNN. The use of a neighbourhood without line crossings is also discussed. Simulation results are reported to show the capability of the proposed approach.

Cellular neural networks as a general massively parallel computational paradigm

In this paper is presented the use of the discrete-time cellular neural network (DTCNN) paradigm to develop algorithms devised for general-purpose massively parallel processing (MPP) systems. This paradigm is defined in discrete N-dimensional spaces (lattices) and is characterized by the locality of the direct information transmission between the space points (cells) and by continuous values of data and parameters; the DTCNN paradigm is thus able to express most of the typical MPP applications. A general version of a DTCNN has been implemented and optimized for three MPP architectures, namely the Connection Machines CM-2 and CM-5 and the Cray T3D. The comparison between the three machine performances with those achieved by a standard SPARC-20 workstation shows that, particularly with large lattices, the speed-up allowed in the computational times is significant and the range of solvable problem sizes is widely extended.

Cellular neural networks as a general massively parallel computational paradigm

In this paper is presented the use of the discrete-time cellular neural network (DTCNN) paradigm to develop algorithms devised for general-purpose massively parallel processing (MPP) systems. This paradigm is defined in discrete N-dimensional spaces (lattices) and is characterized by the locality of the direct information transmission between the space points (cells) and by continuous values of data and parameters; the DTCNN paradigm is thus able to express most of the typical MPP applications. A general version of a DTCNN has been implemented and optimized for three MPP architectures, namely the Connection Machines CM-2 and CM-5 and the Cray T3D. The comparison between the three machine performances with those achieved by a standard SPARC-20 workstation shows that, particularly with large lattices, the speed-up allowed in the computational times is significant and the range of solvable problem sizes is widely extended.

Discrete-time cellular neural networks using distributedarithmetic

An efficient digital architecture for the discrete-time cellular neural networks (DTCNNs) is proposed that employs the distributed arithmetic (DA). It consumes little silicon area because of the bit serial computation of DA, and offers higher speed operation than the analogue implementations of DTCNN. The proposed architecture has been implemented in a 0.8 µm CMOS technology.

Discrete-time cellular neural networks for associative memories with learning and forgetting capabilities

A synthesis procedure for associative memories using Discrete-Time Cellular Neural Networks (DTCNN's) with learning and forgetting capabilities is presented. The proposed design technique generates networks with the capability of learning new patterns and forgetting old ones without recomputing the whole interconnection matrix and the input vector.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Image coding and decoding by discrete‐time cellular neural networks

AbstractWhen the original signal to be encoded has a strong correlation in the neighborhood, as in the case of the natural image, it can be expected that the original signal is represented by a smaller number of bits.This paper proposes the following low‐bit coding system. the analog image is converted into the digital image by A‐D conversion in the transmitter based on the dynamics of the locally interconnected discrete‐time cellular neural network (DTCNN). the digital image is passed through a lowpass filter in the receiver so that the original analog image is restored. In this method, the coding of the static image is reduced to the optimization problem where the error between the original image and the decoded image is minimized. the distortion function is defined so that the noise generated by encoding is suppressed from the viewpoint of the whole image.A high‐quality image is reconstructed by the dynamics of the multivalued neuron, which is an extension of the output of the neuron to multiple values. In this method, a parallel processing dynamics is employed, where a complex function can be realized from simple devices, and it is expected to realize the digital conversion in real‐time of the analog information which is input in parallel, as in the case of the light input to the retina.

Estimating the storage capacity of space-varyingcellular neural networks

The capacity of associative memories based on space-varying, nonreciprocal, discrete-time cellular neural networks (CNNs) is investigated. The capacity is defined as the maximum number of random bipolar prototypes which can be stored with probability larger than a suitable threshold. It is shown that the capacity of the CNN is actually determined by the cells with the smallest number of connections, i.e. those located at the corners of the rectangular array. A simple empirical formula is presented which enables a prediction to be made as to the capacity of the CNN associative memory as a function of the neighbourhood radius and of the stability margin.

An optimized synthesis of a discrete-time cellular neural network for parallel thinning

The paper describes a systematic synthesizing method to realize the parallel binary image-thinning algorithm by a discrete-time cellular neural network. In contrast with previous studies, this paper starts from very basic local rules (algorithm) and the required cloning templates are calculated step-by-step. Mathematical techniques of combining compatible templates are proposed and optimization of the total number of cloning templates, the operating speed and sensitivity is addressed. Finally, the speed and circuit performances are compared with other studies.

A geometric approach to properties of the discrete-time cellular neural network

Using the available theory on linear threshold logic, the Discrete-Time Cellular Neural Network (DTCNN) is studied from a geometrical point of view, Different modes of operation are specified. A bound on the number of possible mappings is given for the case of binary inputs. The mapping process in a cell of the network is interpreted in the input space and the parameter space. Worst-case and average-case accuracy conditions are given, and a sufficient worst-case bound on the number of bits required to store the network parameters for the case of binary input signals is derived. Methods for optimizing the robustness of DTCNN parameters for certain regions of the parameter space are discussed. >

On the convergence of reciprocal discrete-time cellular neural networks

Two results are proved concerning the global convergence of reciprocal discrete-time cellular neural networks (DTCNNs). The first result regards DTCNNs with a piecewise-linear nonlinearity and is an extension of a theorem by N. Fruehauf et al. (1992). The second result regards DTCNNs with threshold-type nonlinearity. Here, convergence is proved under mild conditions assuming a semiparallel operation, that is, only noninteracting cells are updated all at once. >

Current-mode techniques for the implementation of continuous- and discrete-time cellular neural networks

A unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNNs) using CMOS current-mode analog techniques is presented. The net input signals are currents instead of voltages, which avoids the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploiting current mirror properties for the efficient implementation of both linear and nonlinear analog operators. Basic design issues, the influence of nonidealities and advanced circuit design issues, and design for manufacturability considerations associated with statistical analysis are discussed. Experimental results are given for three prototypes designed for 1.6- mu m n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. >

Analog CMOS implementation of a discrete time CNN with programmable cloning templates

An analog CMOS implementation of cells for building discrete-time cellular neural networks (DT-CNNs), based on current-mode multipliers and capacitive storage for the analog initial states and cloning templates, is presented. Since the cloning templates are programmable, the circuit could be used for several applications, or it could be reconfigured to perform different tasks on the initial input data sequentially. A chip prototype containing to DT-CNN cells has been designed and manufactured, and some experimental results showing the functionality of the circuit are provided.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>