Direct Memory Access Operations Research Articles

WCET-Aware Function-Level Dynamic Code Management on Scratchpad Memory

Scratchpad memory (SPM) is a promising on-chip memory choice in real-time and cyber-physical systems where timing is of the utmost importance. SPM has time-predictable characteristics since its data movement between the SPM and the main memory is entirely managed by software. One way of such management is dynamic management. In dynamic management of instruction SPMs, code blocks are dynamically copied from the main memory to the SPM at runtime by executing direct memory access (DMA) instructions. Code management techniques try to minimize the overhead of DMA operations by finding an allocation scheme that leads to efficient utilization. In this article, we present three function-level code management techniques. These techniques perform allocation at the granularity of functions, with the objective of minimizing the impact of DMA overhead to the worst-case execution time (WCET) of a given program. The first technique finds an optimal mapping of each function to a region using integer linear programming (ILP), whereas the second technique is a polynomial-time heuristic that is suboptimal. The third technique maps functions directly to SPM addresses, not using regions, which can further reduce the WCET. Based on ILP, it can also find an optimal mapping. We evaluate our techniques using the Mälardalen WCET suite, MiBench suite, and proprietary automotive applications from industry. The results show that our techniques can significantly reduce the WCET estimates compared to caches with the state-of-the-art cache analysis.

A New Method to Enhance Performance of Digital Frequency Measurement and Minimize the Clock Skew

There are different ways to measure frequency. But in most of the methods the systems are failed to provide good sensitivity or to maintain constant relative errors. This paper presents a new wide-range speed measurement method, using the direct memory access (DMA) terminal count register. The measure ends are interfaced with DMA channels through pipelines to improve hit ratio. Here hit ratio indicates the exact identification of encoder pulses without any fail or miss. The DMA method is based on pulses counting in the constant sampling time at terminal count stop pin of a DMA controller. A pipe line technology is built in the system to reduce the data losses during not ready sequence of DMA operations. But the conventional pipeline system is facing problems due to improper synchronization of clock pulses. This is a universal problem in all the digital systems mostly called jitter or skew. In most of the digital systems the propagation of information mainly controlled on the basis of clock pulses. In most of the digital systems the clock skew decreases the performance of the digital systems. Here a new system is implemented in the path of the clock to remove or reduce the clock skew.

Automatic analysis of DMA races using model checking and k-induction

Modern multicore processors, such as the Cell Broadband Engine, achieve high performance by equipping accelerator cores with small “scratch-pad” memories. The price for increased performance is higher programming complexity – the programmer must manually orchestrate data movement using direct memory access (DMA) operations. Programming using asynchronous DMA operations is error-prone, and DMA races can lead to nondeterministic bugs which are hard to reproduce and fix. We present a method for DMA race analysis in C programs. Our method works by automatically instrumenting a program with assertions modeling the semantics of a memory flow controller. The instrumented program can then be analyzed using state-of-the-art software model checkers. We show that bounded model checking is effective for detecting DMA races in buggy programs. To enable automatic verification of the correctness of instrumented programs, we present a new formulation of k-induction geared towards software, as a proof rule operating on loops. Our techniques are implemented as a tool, Scratch, which we apply to a large set of programs supplied with the IBM Cell SDK, in which we discover a previously unknown bug. Our experimental results indicate that our k-induction method performs extremely well on this problem class. To our knowledge, this marks both the first application of k-induction to software verification, and the first example of software model checking in the context of heterogeneous multicore processors.

Compiler‐assisted dynamic scratch‐pad memory management with space overlapping for embedded systems

AbstractScratch‐pad memory (SPM), a small, fast, software‐managed on‐chip SRAM (Static Random Access Memory) is widely used in embedded systems. With the ever‐widening performance gap between processors and main memory, it is very important to reduce the serious off‐chip memory access overheads caused by transferring data between SPM and off‐chip memory. In this paper, we propose a novel compiler‐assisted technique, ISOS (Iteration‐access‐pattern‐based Space Overlapping SPM management), for dynamic SPM management with DMA (Direct Memory Access). In ISOS, we combine both SPM and DMA for performance optimization by exploiting the chance to overlap SPM space so as to further utilize the limited SPM space and reduce the number of DMA operations. We implement our technique based on IMPACT and conduct experiments using a set of benchmarks from DSPstone and Mediabench on the cycle‐accurate VLIW simulator of Trimaran. The experimental results show that our technique achieves run‐time performance improvement compared with the previous work. The average improvements are 13.15, 19.05, and 25.52% when the SPM sizes are 1KB, 512 bytes, and 256 bytes, respectively. Copyright © 2010 John Wiley & Sons, Ltd.

Special issue: advanced topics on scalable computing

Special issue: advanced topics on scalable computing

Dynamic scratch‐pad memory management with data pipelining for embedded systems

AbstractIn this paper, we propose an effective data pipelining technique, SPDP (Scratch‐Pad Data Pipelining), for dynamic scratch‐pad memory (SPM) management with DMA (Direct Memory Access). Our basic idea is to overlap the execution of CPU instructions and DMA operations. In SPDP, based on the iteration access patterns of arrays, we group multiple iterations into a block to improve the data locality of regular array accesses. We allocate the data of multiple iterations into different portions of the SPM. In this way, when the CPU executes instructions and accesses data from one portion of the SPM, DMA operations can be performed to transfer data between the off‐chip memory and another portion of SPM simultaneously. We perform code transformation to insert DMA instructions to achieve the data pipelining. We have implemented our SPDP technique with the IMPACT compiler, and conduct experiments using a set of loop kernels from DSPstone, Mibench, and Mediabench on the cycle‐accurate VLIW simulator of Trimaran. The experimental results show that our technique achieves performance improvement compared with the previous work. Copyright © 2010 John Wiley & Sons, Ltd.