Diode-connected Load Research Articles

Fine-Tunable Emission Pulse Generation Circuit Based on p-Type Low-Temperature Poly-Si Thin-Film Transistors for Active Matrix Organic Light-Emitting Diode Displays

Active matrix organic light-emitting diode (AMOLED) displays have deployed the compensation techniques to cope with the luminance non-uniformity issues caused by variations on electrical characteristics of thin-film transistors (TFTs). While some compensation circuits require control signals of longer pulse widths than a line time, the luminance control as well as the higher bit depth representation have been also accomplished by adjusting the pulse widths. A proposed EM pulse generation circuit consists of 11 p-type low-temperature poly-Si (LTPS) TFTs and a one coupling capacitor. While previous tunable circuits could address pulse widths of either even or odd multiples of a line time, the proposed circuit can generate any multiples by changing phases of additional clock signals. In particular, the internal inverter is implemented with a load connected to the output of a previous stage’s inverter to reduce the power consumption over pulse widths. The coupling capacitor is also connected between two adjacent stages through one TFT, eliminating coupling noises on the output pulses. The proposed EM circuit is simulated at a line time of 3.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> s for a 120 Hz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{3840}$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{2160}$</tex-math> </inline-formula> display. The results ensure that pulse widths from three to 2160 lines are generated successfully without coupling noises and the small variation on power consumption from 1.23 to 0.33 mW is achieved at 30 stages for the whole range of pulse widths, compared to the large range from 1.26 to 76.91 mW with the inverter of a diode-connected load.

A Single-Transistor Amplifier With Back-Gate Feedback in 22-nm FD-SOI

Fully-depleted silicon-on-insulator (FD-SOI) technology provides an additional degree of circuit design freedom due to its fourth terminal, the back-gate. In this letter, we present a single-transistor common-source amplifier exploiting the FD-SOI back-gate as a feedback injection point. This negative back-gate feedback improves linearity and reduces device-to-device gain variation without increasing noise or power and with no added components. A prototype amplifier, implemented in 22-nm FD-SOI, operates from weak to moderate inversion and achieves 5&#x2013;10&#x00D7; lower gain variation and 6&#x2013;20-dB higher VIP3 compared to a reference two-transistor amplifier with a diode-connected load.

A Broadband PVT-Insensitive All-nMOS Noise-Canceling Balun-LNA for Subgigahertz Wireless Communication Applications

A broadband process, voltage, and temperature (PVT)-insensitive noise-canceling balun-low-noise amplifier (LNA) was implemented in the 0.13-μm CMOS process for subgigahertz wireless communication applications. The proposed LNA is based on the traditional common-gate common-source (CGCS) balun-LNA topology, and it adopts the diode-connected loads to reduce the noise contribution originated from CGCS transistors and enhance the linearity due to post linearization. The auxiliary common-source (CS) amplifier with a diode-connected is added to reduce the overall noise figure (NF) of the LNA by sharing an input signal with CGCS transistors and applying its output signal to the diode-connected load of CS transistor. Because the voltage gain of the LNA is determined by the transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) ratio of the same types of nMOS transistors, its power gain (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> ) and NF are quite roust over PVT variations. In experiments, it showed S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> of 14 dB and NF of 4 dB with an input return loss (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> ) of greater than 10 dB at 450 MHz. Concerning voltage variation (1.08-1.32 V) and temperature variation (-20 °C ~ +80 °C), the worst variations in S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> and NF were approximately 1.4 and 1.1 dB, respectively.

An Active Multielectrode Array for Collecting Surface Electromyogram Signals Using a-IGZO TFT Technology on Polyimide Substrate

The surface electromyogram (sEMG) signals produced by living bodies play a significant role in biological applications. However, an active multielectrode array (MEA) having a high spatiotemporal resolution, flexibility, and high gain is still an enormous challenge for accurate sEMG detection. Here, a flexible active MEA based on the diode-connected load inverter is proposed and fabricated for collecting sEMG signals using amorphous indium&#x2013;gallium&#x2013;zinc oxide (a-IGZO) thin-film transistors (TFTs) technology on the polyimide (PI) substrate. To obtain the good gain effect and low-noise active MEA, the width&#x2013;length ratio of the transistors and the suitable impedances are systemically designed. Moreover, the optimized circuit exhibits good bias stability, excellent uniformity in electrical performance, and outstanding mechanical durability, which can ensure reliable sEMG detection. With the combination of the a-IGZO TFTs, the active MEA has an approximate 15-dB signal gain under a low driving voltage of 5 V. Measuring the sEMG of the muscle groups below the thumb with our developed flexible active MEA, the amplitude value of sEMG signals is successfully amplified and the noise fluctuation is obviously reduced. Thus, the active MEA has certain advantages in large-area preparation, stability, flexibility, and high gain, which opens a new avenue for the accurate sEMG signal measurements.

A RF PVT Compensated Negative Resistance Circuit for Q-factor Improvement of Passive Elements in CMOS

A RF process, voltage and temperature (PVT) compensated negative resistance (NR) circuit is proposed to improve the quality factor (Q-factor) of CMOS passive devices while ensuring stability over PVT variations. It is implemented in the form of a grounded NR circuit to support single-ended RF circuit applications. Various circuit techniques such as a diode-connected load, a proportional-to-absolutetemperature (PTAT) current source and an adaptive body-biasing based threshold voltage compensation have been adopted to obtain a stable negative resistance value. Simulation results show that the Qfactor of on-chip spiral inductors loaded by the proposed NR circuit is improved from 6 to 60 at 1 ㎓ under typical corner conditions (tt, 1.2V, 27 ℃). The simulated Q-factor variation in corner conditions is approximately 37, which is approximately 6.5 times more stable than conventional NR circuit without compensation.

An Ultra-Low Power Subthreshold CMOS RSSI for Wake-Up Receiver

This paper reports an ultra-low power received signal strength indicator (RSSI) for low frequency (LF) wake-up receiver. Topology theory analysis and subthreshold operation are performed to lower power consumption. Each gain stage of the subthreshold limiting amplifier (LA) employs cascade diode-connected loads to obtain high output impedance while maintaining low power. An offset cancelation circuit with different tail currents, which also operates in the subthreshold region, is employed to reduce the DC offset voltage. Unbalanced source-coupled pairs of subthreshold devices adopted in the full-wave rectification are optimized. A 45[Formula: see text]dB input dynamic range and [Formula: see text][Formula: see text]dB indicating error are achieved at 125[Formula: see text]KHz frequency. The prototype occupies an active area of 0.39[Formula: see text][Formula: see text][Formula: see text]0.28[Formula: see text]mm using CSMC 0.153-[Formula: see text]m complementary metal-oxide-semiconductor (CMOS) technology. With a 1.8[Formula: see text]V supply voltage, the overall current consumption is only 6[Formula: see text][Formula: see text]A.

InGaZnO Thin-Film-Transistor-Based Four-Quadrant High-Gain Analog Multiplier on Glass

This letter presents a novel high-gain four-quadrant analog multiplier using only n-type enhancement indium-gallium-zinc-oxide thin-film-transistors. The proposed circuit improves the gain by using an active load with positive feedback. A Gilbert cell with a diode-connected load is also presented for comparison purposes. Both circuits were fabricated on glass at low temperature (200°C) and were successfully characterized at room temperature under normal ambient conditions, with a power supply of 15 V and 4-pF capacitive load. The novel circuit has shown a gain improvement of 7.2 dB over the Gilbert cell with the diode-connected load. Static linearity response, total harmonic distortion, frequency response, and power consumption are reported. This circuit is an important signal processing building block in large-area sensing and readout systems, specially if data communication is involved.

Stable organic static random access memory from a roll-to-roll compatible vacuum evaporation process

An organic Static Random Access Memory (SRAM) based on p-type, six-transistor cells is demonstrated. The bottom-gate top-contact thin film transistors composing the memory were fabricated on flexible polyethylene naphthalate substrates. All metallization layers and the p-type semiconductor dinaphtho[2,3-b:2',3'-f] thieno[3,2-b]thiophene were deposited by thermal evaporation. The gate dielectric was deposited in a vacuum roll-to-roll environment at a web speed of 25 m/min by flash-evaporation and subsequent plasma polymerisation of tripropyleneglycol diacrylate (TPGDA). Buffering the TPGDA with a polystyrene layer yields hysteresis-free transistor characteristics with turn-on voltage close to zero. The static transfer characteristic of diode-connected load inverters were also hysteresis-free with maximum gain >2 and noise margin ∼2.5 V. When incorporated into SRAM cells the time-constant for writing data into individual SRAM cells was less than 0.4 ms. Little change occurred in the magnitude of the stored voltages, when the SRAM was powered continuously from a −40 V rail for over 27 h testifying to the electrical stability of the threshold voltage of the individual transistors. Unencapsulated SRAM cells measured two months after fabrication showed no significant degradation after storage in a clear plastic container in normal laboratory ambient.

External pressure responsive device based on tunable organic inverter using soft contact lamination

A voltage tunable device which operates by external pressure based on a diode-connected load inverter is successfully fabricated by connecting two transistors adopting bridge-structured polymeric stamps with gold electrodes. When pressure is applied to the polymeric stamp in the drive transistor, the effective channel length between the source–drain electrodes decreases such that the source–drain current is increased and the voltage transfer curves of the inverter are shifted in the positive direction. Thus, a voltage tunable device (or a pressure sensitive inverter) is achieved, because the output voltage of the load inverter comes to have a corresponding relation with the applied pressure. In addition, the sensitivity of this pressure responsive device can be improved by changing the thickness of the polymeric stamp.

A binary-weighted 64-dB programmable gain amplifier with a DCOC and AB-class buffer

This paper designs a binary-weighted programmable gain amplifier (PGA) with a DC offset cancellation (DCOC) circuit and an AB-class out put buffer. The PGA adopts the circuit topology of a differential amplifier with diode-connected loads. Simulation shows that the performance of the PGA is not sensitive to temperature and process variation. According to test results, controlled by a digital signal of six bits, the PGA can realize a dynamic gain of −2 to 61 dB, and a gain step of 1 dB with a step error within ±0.38 dB. The minimum 3 dB bandwidth is 92 MHz. At low-gain mode, IIP3 is 17 dBm, and a 1 dB compression point can reach 5.7 dBm. The DCOC circuit enables the amplifier to be used in a direct-conversion receiver and the AB-class output buffer circuit reduces the overall static power consumption.

Bootstrapped inverter using a pentacene thin-film transistor with a poly(methyl methacrylate) gate dielectric

A bootstrapped inverter incorporating pentacene organic thin-film transistors (OTFTs), with poly(methyl methacrylate) as the gate dielectric, has been designed, fabricated and tested. The inverter uses capacitive coupling and bootstrapping effects, and exhibits superior performance to the normal diode-connected load inverter. The pentacene OTFTs used for the inverter possess a field-effect mobility of 0.32 cm2/V/s, a threshold voltage of −10.0 V, a subthreshold slope of 1.5 V per decade and an on/off current ratio of 2.2×106. The inverter has a 30 µs rise time and a 450 µs fall time, at an operating frequency of 1 kHz and 30 V drive voltage.