Diode-clamped Multilevel Converters Research Articles

Modified Approach for Harmonic Reduction in Transmission System Using 48-pulse UPFC Employing Series Zig-Zag Primary and Y-Y Secondary Transformer

In this paper THD (Total Harmonic Distortion) is analysed and compared by using UPFC in a multi-line transmission system of 500 KV having 5- buses in two different arrangements. The UPFC converters are arranged as a Diode Clamped multilevel Converter (DCMLC) that leads to the cost reduction as compared with other multi-level converters. The comparison has been done by both series zig-zag/2Y- 2Δ and series zig-zag/4Y transformer configuration for 48-pulses GTO based diode clamped converter. The THD is reduced to 42.59% and 58.82% of input waveform at bus B2 by using series zig-zag/4Y transformer configuration. This transformer converter configuration also reduces the difficulty of designing the transformer winding ratio. For calculation of THD, FFT analysis is carried out using MATLAB.

One‐inductor‐based auxiliary circuit for dc‐link capacitor voltage equalisation of diode‐clamped multilevel converter

The one-inductor-based auxiliary balancing circuit is proposed to equalise dc-link capacitor voltages of diode-clamped multilevel converters (DCMC) in this study. After theoretical analysis of balancing unit in traditional one-level-based balancing schemes, one-inductance-based schemes are designed according to the same operating principle. Via some conducted diodes and switches by simple control, this circuit provides energy exchange paths of all the dc-link capacitors by only one inductor. Firstly, the inductor absorbs energy from the capacitor with the highest voltage. Then, this capacitor is discharged and its voltage will decrease. Secondly, the inductor releases energy to the capacitor with the lowest voltage. Then, this capacitor is charged and its voltage will increase. After performing this operation a number of times, all the voltages of the dc-link capacitors will finally reach the same value. The circuit configurations, conducting paths and control strategies of one-inductor-based scheme for five-level DCMC are analysed, respectively. Owing to small equivalent resistances of capacitor and inductor, the small power loss could be achieved. Simulations and experiments have been carried out. The steady-state and dynamic results verify the effective balancing performance of this circuit.

Multilevel SVPWM With DC-Link Capacitor Voltage Balancing Control for Diode-Clamped Multilevel Converter Based STATCOM

In this paper, a space vector pulsewidth modulation (PWM) (SVPWM) algorithm is proposed, which is in α'β' frame with dc-link capacitor voltage equalization for diode-clamped multilevel converters (DCMCs). The α'β' frame is a coordinate system similar to the αβ frame. In this frame, some original complex calculations are substituted by integer additions, integer subtractions, truncations, etc. It brings the time and area efficiency to fixed-point digital realization, particularly for the application in a field-programmable gate array. Meanwhile, a minimum energy property of multiple dc-link capacitors is applied as the basic principle for voltage equalization based on a capacitor current prediction algorithm. By evaluating the redundant vectors in each pulse dwelling period, the balancing algorithm chooses an optimal vector, generates the optimal PWM signals, and sustains the voltage stability. After that, an arbitrary multilevel SVPWM intellectual property core is designed and analyzed in the α'β' frame. At the end of this paper, a five-level DCMC-based static synchronous compensator is built and tested. The experimental results verify the balancing algorithm and the system steady-state and dynamic performances.

Voltage Balancing Approaches for Diode-Clamped Multilevel Converters Using Auxiliary Capacitor-Based Circuits

An auxiliary capacitor-based balancing approach is adopted in this paper to equalize the dc-link capacitor voltages of a diode-clamped multilevel converter (DCMC). Four balancing circuits, including the generalized, one-level-capacitor, one-capacitor, and simplified one-capacitor-based configurations are discussed for a five-level DCMC system. These configurations are different in connection of the auxiliary circuits and numbers of the capacitors and switches, but they work on the same principle called ping-pong operation by utilizing the auxiliary capacitor as an equalizer between the capacitors of different voltages. The unbalance phenomenon, ping-pong principle, circuit configurations, and their switching schemes are analyzed, respectively. The superiorities of the proposed approach include balancing operation regardless of load power factor and modulation index, control simplicity, and independence from main circuits when compared to the traditional approaches. Simulations and experimental results verified the performances using the proposed balancing circuits and control strategies.

Voltage and Frequency Control of Wind Driven Stand-Alone Self-Excited Induction Generator Using DCMLC Based STATCOM

This paper describe the methods employed to control voltage and frequency of a 3-O stand-alone self-excited induction generator (SEIG) driven by a variable speed wind turbine. An attempt made to control the terminal voltage of SEIG by using a 3-O diode clamped multilevel converter (DCMLC) based STATCOM operation. A 3-O diode bridge rectifier with a d.c chopper circuit is employed to control the frequency of generated voltage. The VAr required by the load and the machine owing to changes in magnetizing reactance’s are compensated by DCMLC–STATCOM operate with full load excitation capacitance. To emphasis the controller characteristics, mathematical model of the controller is developed and implemented in MATLAB / SIMULINK software.

HVDC transmission systems: Bipolar back-to-back diode clamped multilevel converter with fast optimum-predictive control and capacitor balancing strategy

Voltage source multilevel power converter structures are being considered for high power high voltage applications where they have well known advantages. Recently, full back-to-back connected multilevel neutral diode clamped converters (NPC) have been used in high voltage direct current (HVDC) transmission systems. Bipolar back-to-back connection of NPCs have advantages in long distance HVDC transmission systems, but highly increased difficulties to balance the dc capacitor voltage dividers on both sending and receiving end NPCs. This paper proposes a fast optimum-predictive controller to balance the dc capacitor voltages and to control the power flow in a long distance HVDC system using bipolar back-to-back connected NPCs. For both converter sides, the control strategy considers active and reactive power to establish ac grid currents on sending and receiving ends, while guaranteeing the balancing of both NPC dc bus capacitor voltages. Furthermore, the fast predictive controller minimizes the semiconductor switching frequency to reduce global switching losses. The performance and robustness of the new fast predictive control strategy and the associated dc capacitors voltage balancing are evaluated.

Generalised pulse width modulation approach for DC capacitor voltage balancing in diode-clamped multilevel converters

This study develops a generalised pulse width modulation (PWM) approach to eliminate both the low-frequency oscillations and imbalances in the dc-link capacitor voltages, which are the main drawbacks of diode clamped converters. The algorithm has been developed within the carrier-based PWM framework to facilitate its implementation in diode clamped converters with four or more levels. In addition, a generalised control strategy for dc voltage control is proposed and its stability is demonstrated. The good performance of the proposed modulation technique is demonstrated from simulation and experimental results for a four-level diode-clamped inverter.

Diode-clamped multi-level power converter with a zero-sequence current loop for three-phase three-wire hybrid power filter

This paper proposes a three-phase three-wire hybrid power filter configured by a three-phase passive power filter and a three-phase diode-clamped multi-level power converter with a small power capacity of zero-sequence current loop connected in series to compensate for the harmonic currents of nonlinear load. The salient feature is that a small power capacity of zero-sequence current loop is applied to overcome the problem of balancing voltages of two DC capacitors for a diode-clamped multi-level power converter applying in the three-phase three-wire hybrid power filter. A laboratory prototype is developed to verify the performance of the proposed three-phase three-wire hybrid power filter. The experimental results have demonstrated the feasibility and practicality of the proposed three-phase three-wire hybrid power filter.

Compensation of Nonlinearities in Diode-Clamped Multilevel Converters

The application of multilevel converters for exciting permanent-magnet machines with low-phase inductance to dc-link voltage ratios facilitates a reduction in high-frequency switching harmonics. However, converter nonlinearities and, in-particular, on-state device voltage drops, create additional low-frequency harmonics. This paper therefore proposes a generic compensation scheme to accommodate the effects of such converter nonlinearities and, in doing so, improve the harmonic quality of the machine phase currents. Experimental results gathered from a prototype five-level diode-clamped converter validate the benefits of the proposed scheme by showing quantitative reductions in low-frequency harmonics.

New approach in back-to-back m -level diode-clamped multilevel converter modelling and direct current bus voltages balancing

Multilevel power converter structures have been introduced as the solution for high-power high-voltage applications and also for grid interface connection of renewable energy sources systems, where they have several advantages, namely low distortion voltages and currents and low switching losses resulting in higher efficiency. As a consequence of increasing interest on the multilevel converter applications, accurate models of these power converters are essential to be used in computer simulation studies. This study presents a new systematic modelling approach suitable to obtain global generalised models for back-to-back m-level diode-clamped multilevel converters connecting AC loads. Using the proposed converter modelling, an advantageous generalised method to balance the (m−1) DC bus capacitors, based on the DC bus average power flow is also presented. The generalised proposed model is particularised to the back-to-back multilevel structure for m=5. This back-to-back converter is studied working with bidirectional power flow, connecting an induction machine (in motor or self-excited generator mode) to the power grid as a flexible AC transmission system.

Frequency reduction schemes for back-to-back connected, diode-clamped multilevel converters

Two new switching schemes for back-to-back connected diode-clamped multilevel converters that reduce the devices switching frequency while maintaining capacitor balancing are presented. Comparisons are made between a previously reported ‘optimal’ balancing strategy and the two proposed switching techniques using data gathered from a prototype five-level, back-to-back connected, diode-clamped multilevel converter. The proposed schemes are shown to allow as much as 35% reduction in switching frequency when compared to the optimal balancing case while also balancing the voltages across the series connected DC-link capacitors. The back-to-back connected, multilevel converter excites a permanent magnet synchronous motor to obtain the experimental data and verify the proposed switching schemes.

Método De Modulação Pwm Para Equilíbrio Das Tensões Dos Capacitores Do Barramento Cc Em Conversores Multiníveis Com Diodos De Grampeamento

Este artigo apresenta uma nova estratégia de modulação para conversores PWM com diodos de grampeamento. Esta estratégia elimina os desequilíbrios de tensão entre os capacitores do barramento CC, que é o principal problema apresentado por esta topologia, bem como as ondulações de baixa frequência que a mesma apresenta operando com altos índices de modulação e baixo fator de potência. Com objetivo de facilitar a extensão dos resultados para um numero qualquer de níveis, a modulação baseada na comparação com portadora foi adotada nesse artigo onde as tensões modulantes são escolhidas de forma a garantir a máxima utilização da tensão do barramento CC na faixa linear de operação do inversor. Para assegurar as adequadas tensões nos capacitores no barramento CC, mesmo na presença de não idealidades no circuito, um método de controle e um controlador são desenvolvidos. Finalmente, o bom desempenho do método de modulação proposto é demonstrado por meio de simulações de um conversor com diodos de grampeamento de quatro níveis.

A Space Vector Modulation Strategy for a Back-to-Back Five-Level HVDC Converter System

The DC-capacitor voltage drift is the main technical drawback of a multilevel diode-clamped converter (DCC) system. This paper proposes a space vector modulation (SVM)-based switching strategy that takes advantage of the redundant switching states of the SVM to counteract the voltage drift phenomenon of a five-level DCC-based back-to-back high-voltage direct-current (HVDC) converter system. The proposed strategy is based on online minimization of a quadratic cost function, associated with the voltage deviations of the dc capacitors. The salient feature of the proposed strategy is that it enables voltage balancing of the DC capacitors with no requirements for offline calculations, additional controls, or auxiliary power circuitry. Performance of the proposed SVM-based balancing strategy for a back-to-back HVDC converter system, based on time-domain simulation studies in the PSCAD/EMTDC environment, is evaluated and experimentally verified. The studies demonstrate capability of the proposed SVM strategy to control and maintain voltage balance of DC capacitors.

Three-Dimensional Feedforward Space Vector Modulation Applied to Multilevel Diode-Clamped Converters

Simplified space vector modulation (SVM) techniques for multilevel converters are being developed to improve factors such as the computational cost, number of commutations, and voltage distortion. The feedforward SVM presented in this paper takes into account the actual DC capacitor voltage unbalance of the multilevel power converter. The resulting technique is a low-cost generalized feedforward 3-D SVM method and is particularized for three-phase multilevel diode-clamped converters. This new modulation technique can be applied to topologies where the gamma component may not be zero. The computational cost of the proposed method is similar to those of comparable methods, and it is independent of the number of levels of the power converter. Experimental results using a three-level diode-clamped converter are presented to validate the proposed modulation technique.

A Simple Voltage Balancing Scheme for m-Level Diode-Clamped Multilevel Converters Based on a Generalized Current Flow Model

This paper presents a simple voltage balancing scheme for m-level diode-clamped multilevel converters (DCMC). This paper first introduces a novel and simple current flow model for general m -level DCMCs. The superiority of the proposed model is its independence from the modulation scheme and its simplicity. It also provides a new perspective for voltage sharing accessibility among the dc link capacitors. The proposed current flow model, a cost function, and a space vector modulation (SVM) switching strategy are then used to balance the capacitors' voltages of the DCMCs in a very simple and optimized manner. Such a voltage balancing scheme was not developed for converters of five levels or greater due to the complexity of the converter and its modeling approaches. To validate the feasibility of the proposed voltage balancing scheme, this paper presents analytical and simulation results obtained from a five-level DCMC. In particular, this paper introduces a stability region within which the voltage balancing strategy converges. The impact of the cost function on the stability margins and converter performance is examined and discussed by means of comparison with different cost functions, and it is shown that the proposed cost function will improve the stability margins. The performance of the strategy for unbalanced and polluted loads shows that, unexpectedly, in some specific cases output current harmonics will improve the stability margin.

Multilevel Diode-Clamped Converter for Photovoltaic Generators With Independent Voltage Control of Each Solar Array

In photovoltaic (PV) power systems where a set of series-connected PV arrays (PVAs) is connected to a conventional two-level inverter, the occurrence of partial shades and/or the mismatching of PVAs leads to a reduction of the power generated from its potential maximum. To overcome these problems, the connection of the PVAs to a multilevel diode-clamped converter is considered in this paper. A control and pulsewidth-modulation scheme is proposed, capable of independently controlling the operating voltage of each PVA. Compared to a conventional two-level inverter system, the proposed system configuration allows one to extract maximum power, to reduce the devices voltage rating (with the subsequent benefits in device-performance characteristics), to reduce the output-voltage distortion, and to increase the system efficiency. Simulation and experimental tests have been conducted with three PVAs connected to a four-level three-phase diode-clamped converter to verify the good performance of the proposed system configuration and control strategy.

Analysis and Control of DC-Capacitor-Voltage-Drift Phenomenon of a Passive Front-End Five-Level Converter

The phenomenon of dc-capacitor-voltage drift is the main technical drawback of a passive front-end multilevel diode-clamped converter (DCC). This paper formulates and analyzes the dc-capacitor-voltage-drift phenomenon of a passive front-end five-level DCC, which operates based on a sinusoidal pulsewidth-modulation (SPWM) switching strategy. The analysis shows dependence of the voltage drift on the modulation index and the ac-side power factor of the DCC. The analysis concludes that an SPWM strategy, without the use of auxiliary power circuitry, is not able to prevent the voltage-drift phenomenon of a five-level DCC. This paper also proposes a space-vector-modulation (SVM)-based switching strategy that takes advantage of redundant switching vectors of the SVM method to counteract the voltage-drift phenomenon. The limit to the range of operation of a five-level DCC, which is based on the proposed SVM strategy, is also presented. The salient feature of the proposed strategy is that it enables voltage balancing of the dc capacitors with no requirements for additional controls or auxiliary-power circuitry, within the specified range of operation. The performance of a DCC under various operating conditions, based on time-domain simulation studies in the MATLAB/SIMULINK environment, is evaluated. This paper demonstrates capability of the proposed SVM strategy to control and maintain voltage balance of dc capacitors.

Design and Comparison of Two Multilevel Converters for Flicker Compensation

The paper is concerned with the design of multilevel converters for compensating the flicker on the medium-voltage distribution networks. Two topologies of converters are considered, namely the Diode Clamped MultiLevel Converter (DCMLC) and the Cascade H-bridge MultiLevel Converter (CMLC). By analytical procedure, the current ratings for the semiconductor devices of the converters are determined, and their passive elements are sized up. The main outcome of the study is that the two topologies substantially require the same overall rating for the semiconductor devices, with the exception of the clamping diodes in the DCMLC-based topology. As a counterpart, the latter topology needs a lower overall capacitance.

Modeling and design of a neutral-point voltage regulator for a three-level diode-clamped inverter using multiple-carrier modulation

The three-level diode-clamped multilevel converter commonly called the neutral-point-clamped converter has become established to be a preferred topology for high-power motor drive applications operating at several kilovolts. Although solutions to the problem of maintaining a stable neutral-point voltage in the converter continue to be the topic of research, a simple solution based on a design-oriented dynamic model of the system is not widely known. This paper presents the design, analysis, and implementation of a simple neutral-point voltage regulator for a three-level diode-clamped multilevel inverter, which uses a multiple-carrier sine-triangle modulator in conjunction with a closed-loop controller for neutral-point regulation. Redundant state choices are controlled via a continuous offset voltage that regulates the dc injection into the midpoint of the dc bus. A small-signal transfer function is developed in closed form, for neutral-point regulation, with the voltage offset as the control variable. Besides maintaining dc-bus voltage balance, the use of the approach leads to a significant reduction in the voltage distortion at the neutral point, allowing a definitive reduction in the required dc bus capacitance. Analytical, computer simulation, and experimental results verifying the approach are presented in this paper.

Voltage-Balance Limits in Four-Level Diode-Clamped Converters With Passive Front Ends

Multilevel diode-clamped converters with more than three levels cannot maintain voltage balance in the dc-link capacitors for some operating conditions due to the existence of dc currents in the middle points. Since capacitors are either completely charged or discharged for those conditions, this circumstance severely limits practical application of these converters. The limit explored in this paper is that the four-level converter cannot achieve voltage balance. Proper redundant vectors are selected in the space-vector diagram so that a quadratic parameter related to the currents in the middle points is minimized.