Digital Single Event Transient Research Articles

A Methodology for Reconstructing DSET Pulses from Heavy-Ion Broad-Beam Measurements

A table-based method for the estimation of heavy-ion-induced Digital Single Event Transient (DSET) voltage pulse-width in a single logic cell has been developed. The estimation method is based on the actual heavy-ion-induced transient current data in a single metal-oxide-semiconductor field effect transistor (MOSFET) used in the logic cell. The DSET pulse waveform in an inverter is obtained from which the pulse-width was estimated to be 420 ps. This DSET pulse-width value (420 ps) falls within the reasonable range of the DSET pulse-width distribution measured by the self-triggering flip-flop latch chain under heavy-ion irradiation test conditions.

Effects of Ionizing Radiation on Digital Single Event Transients in a 180-nm Fully Depleted SOI Process

Effects of ionizing radiation on single event transients are reported for Fully Depleted SOI (FDSOI) technology using experiments and simulations. Logic circuits, i.e. CMOS inverter chains, were irradiated with cobalt-60 gamma radiation. When charge is induced in the n-channel FET with laser-probing techniques, laser-induced transients widen with increased total dose. This is because radiation causes charge to be trapped in the buried oxide, and reduces the p-channel FET drive current. When the p-channel FET drive current is reduced, the time required to restore the output of the laser-probed FET back to its original condition is increased, i.e. the upset transient width is increased. A widening of the transient pulse is also observed when a positive bias is applied to the wafer without any exposure to radiation. This is because a positive wafer bias reproduces the shifts in FET threshold voltages that occur during total dose irradiation. Results were also verified with heavy ion testing and mixed mode simulations.

Heavy-Ion-Induced Digital Single Event Transients in a 180 nm Fully Depleted SOI Process

Heavy- ion-induced single events transients (SETs) in advanced digital circuits are a significant reliability issue for space-based systems. SET pulse widths in silicon-on-insulator (SOI) technologies are often significantly shorter than those in comparable bulk technologies. In this paper, heavy-ion-induced digital single-event transient measurements are presented for a 180-nm fully depleted SOI technology. Upset cross-sections for this technology with and without body-ties are analyzed using 3-D TCAD simulations. Pulse broadening is shown to lengthen the measured SET pulse widths significantly for the circuit without body contacts.

Modeling and Simulation of Single-Event Effects in Digital Devices and ICs

This paper reviews the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits, with a special emphasis on the current challenges concerning the physical modeling of ultra-scaled devices (in the deca-nanometer range) and new device architectures (Silicon-on-insulator, multiple-gate, nanowire MOSFETs). After introducing the classification and the terminology used in this paper, we firstly present the basis of the different transport models used in device-level simulation (drift-diffusion, hydrodynamic, Monte-Carlo and some approximated and exact quantum-mechanical based approaches). We also focus on the main emerging physical phenomena affecting ultra-short MOSFETs (quantum effects, tunneling current, ballistic operation) and the methods envisaged for taking them into account at device simulation level. Several examples of device simulation are given at the end of this first part, including recent results on fully-depleted SOI and multiple-gate devices. In the second part, we briefly survey the different circuit-level modeling approaches (circuit-level simulation, Mixed-Mode, 3-D simulation of portions of circuits) of single-event effects in integrated circuits. The SEU in advanced SRAM and SEE mechanisms in logic circuits are reminded. The production and propagation of digital single-event transients (DSETs) in sequential and combinational logic, as well as the soft error rate trends with scaling are particularly addressed. Recent bibliographical examples of simulation in SRAMs and logic circuits are presented and discussed to illustrate these topics at circuit-level.

Effect of Voltage Fluctuations on the Single Event Transient Response of Deep Submicron Digital Circuits

Heavy ion-induced single events transients (SETs) in advanced digital circuits are becoming a significant reliability issue for space-based systems. In this work, two experiments are performed on devices designed to look specifically at digital single event transients. Small voltage variations, like those that can be found across an integrated circuit, are shown to affect the digital single event transient response significantly. For technologies with supply voltages near 1 V, these potential variations may result in unexpected vulnerability.

Comparison of heavy ion and proton induced combinatorial and sequential logic error rates in a deep submicron process

Digital single event transients induced in combinatorial logic are quickly becoming a significant error source as circuit feature sizes shrink and digital circuits operate faster. In this paper, we are able to compare the combinatorial logic error rate to the sequential logic error rate in both heavy ion and proton environments in a simple digital circuit created in a 0.18 /spl mu/m CMOS technology. We are able to do this by comparing data from two unique test chips.

Variation of digital SET pulse widths and the implications for single event hardening of advanced CMOS processes

Single event transient (SET) pulse widths produced from heavy ion irradiation in digital ICs are measured using a variable-delay temporal-latch test structure. We show for the first time that there is a wide distribution of SET pulse widths created by heavy ion radiation in digital CMOS logic at given linear energy transfer (LET) levels. We were able to measure SET pulse widths from as short as 344 ps to greater than 1.5 ns in 0.18 /spl mu/m CMOS technology at LETs greater than 80 MeV-cm /sup 2//mg. Depending on LET, the cross section of the very long SET pulses were as much as four orders of magnitude smaller than for the shorter pulse widths. This has substantial implications for hardening techniques; specifically, we now know that we can dramatically improve the SET hardness without suffering the speed penalties required to remove the longest transients.