Digital Signal Processing Hardware Research Articles

Novel Spectral Approaches in Mathematical Bioacoustics Based on Real Time Analysis and Modern Computational Mathematical Techniques Using Digital Signal Processing and Analog Signal Processing Hardware (Review Lecture)

This review publication is an expanded version of the 2015 lecture at the III Moscow Seminar on Mathematical Bioacoustics and Analog Signal Processing in Physiology. Unlike the original 2015 version, this version includes developments by E.D. Adamovich and F.K. Orekhov, as well as a number of graphic materials of historical value. The work proposes new principles or approaches for multifactori/multimodal analysis of various bioacoustic signals based on N-dimension complex spectral analysis of different (bio) physical variables - “bioacoustic fingerprinting” and “bioacoustic footprinting”. Hadware-based technical examples of possible uses of this approache are given for the breef annotation in the text of this lecture.

A new conservative chaotic system and its application in image encryption

A new n-dimensional conservative chaotic model is proposed to quickly realise a conservative chaotic system. The validity of this model is verified by generating a five-dimensional conservative chaotic system as an example. This system is dynamically analysed from the perspective of Lyapunov exponents (LEs), complexity and phase diagram, which prove its good chaotic properties. Compared with existing systems, the proposed system has a simple structure, large LEs, continuous chaotic ranges and high complexity. Additionally, the National Institute of Standards and Technology verified that the proposed system demonstrates good randomness and is implemented on a digital signal processor hardware platform. Subsequently, a new image encryption scheme that uses true random numbers, lattice-based public key cryptography and dynamic P- and S-boxes is presented based on the new system. The results show that the algorithm demonstrates the capability of the cryptosystem to achieve quality encryption while resisting quantum computer, statistical, differential and cutting attacks compared with other encryption algorithms.

Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key

This article proposes a robust encrypted protein molecular biometric signature-based hardware security approach to secure hardware accelerators (like digital signal processing (DSP) and multimedia intellectual property (IP) cores) against threats of piracy/IP counterfeiting and ownership abuse. In the proposed approach, protein molecular biometric signature is formulated by taking the protein sequence of 20 different unique amino acid combinations from human body protein sample, followed by robust encryption using facial biometric key and encodings. This IP vendor’s encrypted protein molecular biometric signature is then subsequently converted into its corresponding digital proof, followed by embedding into the design as a covert protein molecular signature security constraint, thus producing a secured hardware accelerator design. The proposed approach is more robust than recent hardware security approaches proposed in the literature in terms of stronger proof of ownership (authorship) as well as tamper tolerance (TT) ability. The results present the following analysis of the proposed protein molecular biometric signature approach: 1) very low probability of coincidence (Pc) metric (signifying strength of digital proof) for different DSP hardware accelerators in the range of 3.40E-13–6.33E-2 and 2) stronger TT ability in the range of 5.39E <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 67–1.0E <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 421 for different DSP hardware accelerators.

Cost-Efficient RIS-Assisted Transmitter Design With Discrete Phase Shifts for Wireless Communication

In this letter, in order to achieve higher spectral and energy efficiency, we propose a novel cost-efficient transmitter conceptual design based on reconfigurable intelligent surface (RIS) with discrete phase shifts. The key idea is to directly utilize the digital signal to adjust the discrete reflection coefficients of RIS, resulting that the phases of the reflected carrier signal being modulated without the need for complex digital signal processing (DSP) hardware and costly radio frequency (RF) chains. Furthermore, a joint digital modulation and beamforming method is developed to enable information transmission as well as enhance signal strength. Based on the proposed transmitter, we derive the closed-form expressions of the signal-to-noise ratio (SNR) and bit error rate (BER) of the received signal and analyze the impact of hardware constraints on communication performance. Extensive simulation results validate that the novel design of RIS-assisted transmitter provides a cost-effective and power-efficient solution for wireless communications.

Prospects for using soft processors in systems-on-a-chip based on field-programmable gate arrays

Objectives. Developing the element base of field-programmable gate arrays (FPGA) may significantly affect the design of electronic devices due to the enhanced logical capacity of such chips and the general tendency towards increased subsystem integration. The system-on-a-chip (SoC) concept is aimed at combining receiving, processing, and exchange subsystems onto a single chip, as well as at implementing control, diagnostic, and other auxiliary subsystems. The study aimed at developing a method for soft processor applications, i.e., processors based on configurable logical resources, for implementing control functions in an FPGA-based SoC.Methods. A digital system design methodology was used.Results. For soft processors, a unified design route based on selecting architectural parameters qualitatively corresponding to control tasks was considered. In particular, such parameters as instruction set addressness, number of pipeline cycles, and arithmetic logic unit configuration are adjustable at the design stage to allow the optimization of the soft processor in the discrete parameter space. An approach to rapid prototyping of the assembler based on stack-oriented programming language with regular grammar was also considered. The control of digital signal processing hardware as part of an SoC is the promising application area for soft processors. An implementation is considered on the example of an SoC based on Xilinx Virtex-7 FPGA containing several processor cores developed using the proposed methodology.Conclusions. The considered approaches to soft processor design allow the rapid prototyping of the control processor core for operation as part of an FPGA-based SoC.

A digital signal processor‐efficient accelerator for depthwise separable convolution

Recent researches on deep convolution neural networks have proposed some compact networks, such as MobileNet, but its main computation, depthwise separable convolution (DWC), which reduces the reusable data and improves the requirement of data loading efficiency. Although DWC can effectively reduce the amount of network computation, it needs a special accelerator to enhance the inference speed. This paper proposes a high-performance accelerator for DWC based on the commonly used acceleration platform field-programmable gate array. The proposed accelerator supports the computation of both standard convolutions (SCs) and DWC as well as two activation functions. In addition, two data storage formats are used to maintain the data loading efficiency for different input requirements of SC and DWC under high parallelism. Furthermore, a processing unit that can execute two 8 × 8-bit multiplications inside one digital signal processor (DSP) is designed to make the best use of the DSP hardware resources. Finally, the accelerator is implemented on ZYNQ ZC706 at 200 MHz. Consuming only 392 DSPs, the accelerator achieves 134.5 giga operations per second (GOPS) and 209.4 frames per second (FPS) on MobileNet V1 as well as 96.4 GOPS and 250.4 FPS on MobileNet V2. Experimental results demonstrate that this design provides a better DSP efficiency than previous works.

БАГАТОКАНАЛЬНИЙ РАДІОПРИЙМАЛЬНИЙ ПРИСТРІЙ ІЗ РОЗШИРЕНИМ ЧАСТОТНИМ ДІАПАЗОНОМ ПРИЙМАННЯ

In the context of the crisis situation on the territory of Ukraine in the eastern regions of the country, monitoring the situation and its changes is of key importance. As a result, monitoring systems and tools are subject to new requirements for speed and efficiency. Currently, in the field of development and design of modern radio receivers there is a rapid increase in requirements for their speed, cost, power supply and spectral efficiency [1]. In the practice of radio monitoring, there is a contradiction between the need to ensure strict requirements for the power consumption of the radio receiver and the expansion of the frequency reception range. The use of tunable digital-to-digital converters (ADCs) with a maximum sampling rate insufficient to accommodate the entire center frequency range of the main reception channel in the zero band of Nyquist [2]. Changing the sampling rate according to the frequency of the main reception channel functionally limits the multichannel reception path due to the need to use different sampling frequencies for reception at different frequencies. Most of the requirements for radio monitoring systems and means are met by radio receiving paths based on SDR technology [3], which is based on digitization of the radio signal in the time scale close to real and further digital signal processing (DOS) software or hardware digital - digital digital signal processors or specialized systems on the chip. This technology allows you to replace the huge variety of existing and developed designs of radios and transceivers, both serial and, above all, amateur, built on a complex superheterodyne scheme, a limited number of available hardware units operating under control. This will simplify and reduce the cost of design, significantly improve performance, support all kinds of modulation, the emergence of a large number of service functions, as well as speed up development. SDR technology can be used in radio frequency recognition (RFID) systems that operate at different frequencies and use different protocols. The article considers the method of reception and processing of radio signals to ensure the effective cost and power consumption of multi-channel radio communication in the extended frequency range. The effectiveness of such an approach is substantiated. The block diagram that implements the proposed method is presented.

Robust Continuous Model Predictive Speed and Current Control for PMSM With Adaptive Integral Sliding-Mode Approach

Model predictive control has been considered as a potential alternative method in electrical drives. High reliable predictive model design is a research hotspot. To further improve the performance, a robust continuous model predictive speed and current control for PMSM with an adaptive integral sliding-mode approach are put forward. The prediction model is directly derived from the integral slinging-mode surface. By using the self-regulation method control and the amplitude of the sliding-mode function, an adaptive integral sliding-mode predictive control (AISMPC) is designed. The proposed strategy solves the chattering problem of sliding-mode control and improves the dynamics of the system. AISMPC has been carried out on a digital signal processing hardware system. The experimental results validate the excellent tracking performance of the proposed strategy.

A silicon photonic–electronic neural network for fibre nonlinearity compensation

In optical communication systems, fibre nonlinearity is the major obstacle in increasing the transmission capacity. Typically, digital signal processing techniques and hardware are used to deal with optical communication signals, but increasing speed and computational complexity create challenges for such approaches. Highly parallel, ultrafast neural networks using photonic devices have the potential to ease the requirements placed on the digital signal processing circuits by processing the optical signals in the analogue domain. Here we report a silicon photonice-lectronic neural network for solving fibre nonlinearity compensation of submarine optical fibre transmission systems. Our approach uses a photonic neural network based on wavelength-division multiplexing built on a CMOS-compatible silicon photonic platform. We show that the platform can be used to compensate optical fibre nonlinearities and improve the signal quality (Q)-factor in a 10,080 km submarine fibre communication system. The Q-factor improvement is comparable to that of a software-based neural network implemented on a 32-bit graphic processing unit-assisted workstation. Our reconfigurable photonic-electronic integrated neural network promises to address pressing challenges in high-speed intelligent signal processing.

Double memristors oscillator with hidden stacked attractors and its multi-transient and multistability analysis

Abstract In this paper, by replacing the two linear resistors in the RLC oscillator with flux-controlled and charge-controlled memristors, a novel double memristors nonlinear circuit system is proposed. From the oscillator circuit, we established the mathematical model of the system and proved that it is a hidden system without equilibrium. The numerical simulation results of the mathematical model are consistent with the circuit. What is more, we also find that one state variable of the system has the typical slow change behavior, which is reflected in the form of step-like or square-like waves, thus forming a novel stacked attractor. Then, through studying the Poincare map, phase diagram, bifurcation diagram, Lyapunov exponents (LEs), it was proved that the system has multi-transient behaviors such as chaos to another chaos, chaos to period, chaos to quasi-period, quasi-period to period. Besides, the memristive oscillator has quasi-periodic multistability when changing the initial values, which is a rare phenomenon for a chaotic system. These findings indicate that the proposed memristive hidden oscillator has complex nonlinear dynamic characteristics. Finally, the Digital Signal Processing (DSP) hardware platform confirms the physical realizability of the oscillator, offering the possibility of engineering applications.

On the advancements of digital signal processing hardware and algorithms enabling the Origins Space Telescope

On August 22, 2019, the Origins Space Telescope (OST) Study Team delivered the OST Mission Concept Study Report and the OST Technology Development Plan to NASA Headquarters. A key component of this study report includes the technology roadmap for detector readout and how new radio frequency-system-on-chip (RFSoC)-based technology would be used to advance the far-infrared polarimeter instrument concept for a spaceflight mission. We present our current results as they pertain to the implementation of algorithms, hardware, and architecture for instrument signal processing of this proposed observatory using RFSoC technology. We also present a small case study, comparing a more conventional readout system with one based on the RFSoC and show a trade of system complexity versus technology readiness level.

Fast Processing of UAV Remote Sensing Image Based on DSP Hardware Simulation Platform

The traditional unmanned aerial vehicle (UAV) remote sensing image processing algorithm is difficult to guarantee both accuracy and speed when dealing with massive data of UAV network. This paper designs an on-the-spot processing system based on portable digital signal processor (DSP) hardware simulation platform. The bilinear interpolation algorithm is optimized and improved for the adaptability of the DSP platform with the reference of the bicubic interpolation algorithm, which is long time-consuming but high accuracy. The nearest neighbor interpolation is merged in the bilinear interpolation algorithm, which improves the edge blurring problem of bilinear interpolation algorithm. In the loop calculation of the multiplication and addition iteration calculation segment of the algorithm, the parallelism of the instruction level is increased by increasing the instruction level parallelism between the loop bodies. Experiments show that, on the basis of ensuring the accuracy of the bilinear interpolation algorithm, the execution speed of the processing algorithm is improved, which can meet the requirements of fast real-time processing of remote sensing images of complex unmanned aerial vehicles.

Design and Study UAV Data Link Terminal with One Station Controls Several Vehicles Dynamic Networking

Considering that there are UAVdynamic networking and collaborative communication requirements under complex mission planning conditions, this paper designs a UAV data link communication terminal with One Station Controls Several Vehicles dynamic networking. Firstly, this paper analyzes the structure of One Station Controls Several Vehicles dynamic networking and cooperative communication system in UAV data link, and combines the characteristics of dynamic networking and task cooperative communication to design a One Station Controls Several Vehicles dynamic networking communication protocol stack and design the structure and function of the man-machine data link, the terminal device hardware is realized by the FPGA chip. This paper focuses on digital zero-IF signal processing unit design and hardware implementation process. Finally, combined with the terminal to build an indoor test environment, this paper tests the network function and performance. The test results prove that the UAV data link terminal in One Station Controls Several Vehicles dynamic networking is effective, and it is practical.

Towed Acoustic Countermeasures for Defending Acoustic Homing Torpedoes

The growing torpedo threat to ships and submarines demands effective countermeasures for defence. Detection, classification and localisation of an attacking torpedo is the first step towards launching effective countermeasures. Studies are on the rise to use the existing sonar systems to detect torpedoes and subsequently use countermeasures. The use of towed array sonar systems for torpedo detection and acoustic counter measures are the most recent and not reported much in open literature. This paper presents a modular acoustic counter measure approach using towed decoy against acoustic homing torpedoes. Describes the technologies and algorithms required for different modes of towed decoy, which is effective against both active and passive acoustic homing torpedoes. Towed decoy signal generation schemes and their realisation using digital signal processing hardware are outlined in this paper.

Hardware-Based Sobel Gradient Computations for Sharpness Enhancement

The majority of imaging systems are software based; they require some kind of microprocessor or microcontroller for the imaging algorithms to run. As the speed requirements of imaging and communications systems increase, the need for more hardware-based imaging systems arises. These fully hardware systems solve the fundamental problem inherent in software-based solutions, in which the speed of the algorithms depend on the instruction cycle speed of the processor. Once an algorithm is designed directly on hardware, the speed of the algorithm depends on the system clock frequency and the propagation delays of the logic cells (or standard cells) used in the design, usually measured in nanoseconds per cell. Therefore, such systems no longer depend on any instruction cycle delays, as there is no microprocessor involved. Most modern imaging and communications systems rely on digital signal processing (DSP) to compute complex mathematical operations. The emergence of powerful and low-cost field-programmable gate array (FPGA) devices with hundreds of arithmetic multipliers has enabled the development of many such DSP hardware applications, traditionally implemented only as software solutions.

Low-cost didactic platform for real-time adaptive filtering: Application on noise cancellation

Didactic platforms, used in real-time digital signal processing courses, are generally dedicated digital signal processors or field-programmable gate arrays. These devices are expensive and difficult to program, preventing their widespread use in signal processing courses. On the other hand, the new technology of digital signal controllers, microcontrollers with floating point and mathematical operations, can reduce the cost of dedicated platforms for real-time digital signal processors, facilitating the development of digital signal processors projects and educational applications, such as teaching adaptive filters. Here, we present a low-cost didactic platform for developing real-time adaptive filters using the digital signal processors hardware based on the ARM Cortex-M7 processor. We present the theoretical aspects of the least mean squares and normalized least mean squares algorithms and an experimental script to help students learn real-time adaptive filters. We also describe the platform structure and the performance measurement, in terms of mean square error, signal-to-noise ratio, and computational efficiency. Finally, we present a brief discussion on the use of this platform in classes and the improvement in the student engagement and attendance.

LUT-Free Carrier Recovery for Intradyne Optical DPSK Receivers in udWDM-PON

We present a lookup table (LUT)-free carrier recovery architecture for intradyne optical DPSK receivers that reduce the required digital signal processing hardware resources, power consumption as well as total process clocks, aimed at cost-effective transceivers for access networks applications. The proposed architecture simplifies frequency compensation algorithm to avoid using m th-power operation and LUTs. We prototyped the proposed carrier recovery on a commercial FPGA for real-time evaluation with data at 1.25 Gb/s. The optical transmission system is implemented by direct-phase modulation of commercial DFB lasers, 25 km of single-mode fiber, and a coherent receiver with low-cost optical front-end based on 3 × 3 coupler and three photodiodes providing phase-diversity operation. Results show high performance in real-time, achieving –54 dBm sensitivity at BER = 10–3 as well as feed-forward frequency error correction, high robustness against the fast frequency laser drifts, and high tolerance to optical phase noise in a 6.25 GHz spaced ultradense wavelength division multiplexing grid.

Optimizing time-pickup algorithms in radiation detectors with a genetic algorithm

Pulse digitization at high rates has paved the way for the use of complex, non-standard algorithms, beyond the conventional constant fraction discriminator (CFD) option to obtain the time-stamps of gamma photons arriving to nuclear detectors. Detector pulses can be shaped with digital filters in digital signal processing (DSP) hardware or software, and timestamps can be derived by interpolating or extrapolating the acquired samples. Digitized pulses can be stored in a computer for off-line analysis allowing for many different algorithm variations to be tried on the same data. One difficulty is that the number of filters and parameters to be tuned in order to optimize the timing performance may become too large to be done by hand. For this, in this work we use a genetic algorithm to tune in-silico digital filters, digital time pickup algorithms and their associated parameters. The data set consisted of 500,000 pulses obtained from the last dynode of two ultrafast photomultiplier tubes (model R9779 by Hamamatsu) coupled to monolithic fast inorganic LaBr3(Ce) scintillators, in a truncated cone geometry 1.5×1×1.5” . With finely tuned conventional (CFD+TAC) timing electronics, a CRT of 155 ps (FWHM) for a 60Co source has been measured by our group, within the state of the art for detectors of this size. Our alternate digital, in-silico implementation of CFD+TAC, fine-tuned with the same parameters obtained during manual adjustment of the conventional DAQ and applied to pulses digitized at 5 GS/s and 14 bits of vertical resolution, reproduces the performance of the conventional DAQ. On the other hand, a genetic algorithm (GA) is employed to optimize digital recursive filters with up to 8 parameters, and different time-pickup strategies (upper level thresholding, CFD, time extrapolation). The same 500,000 pulses are employed for which the GA finds several families of filters outperforming the manually tuned algorithm by more than 10%.

Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

A Brief Review on Acoustic Analysis in Quality Evaluation and a New Method for Determining Bulk Density of Aggregate

The purpose of this study is to provide a brief review on acoustic analysis in quality evaluation and a new method for determining bulk density of aggregate. An acoustical system was developed to measure aggregate density. The system includes three microphones, a steel plate, a sinker, an isolated body and digital signal processing hardware. The steel plate was placed on aggregate, followed by releasing the sinker on the steel plate. Then, the acoustic impact was analyzed using speech recognition technology. Aggregate samples at different densities were prepared using ASTM Standard C29. Next, using the acoustical system, audio signals were collected. A neural network was developed for sound data classification into three aggregate densities (good density, medium density, and low density). The classification accuracy was 77.1% on the test set and 96.5% on all data sets. The other neural network was developed for sound data classification into two aggregate densities (good density and low density). The classification accuracy was 90.6% on the test set and 89.6% on all datasets.