Digital Signal Processing Block Research Articles

Parallel architecture of power‐of‐two multipliers for FPGAs

This research work presents a novel approach to design efficient power-of-two multipliers on modern field-programmable gate arrays (FPGA) devices. Several ways of exploiting fixed-point power-of-two multiplications have been recently demonstrated to reduce the computational complexity of several computationally intensive applications, such as computer vision, deep learning, and many others. Modern FPGA devices provide speed-optimised intellectual property (IP) cores based on embedded modules, such as digital signal processing blocks, and area-optimised IP cores based on reconfigurable logic resources, such as look-up tables and flip-flops. Unfortunately, due either to their limited available amount or to their limited running frequency, these IP cores do not allow the overall computational capability offered by an FPGA device to be completely exploited. While the speed-optimised version of the multiplier proposed here is fast enough to increase the number of operations performed per second by up to 4.3 times, with respect to the conventional designs, its area-optimised implementation reduces resources requirements and energy consumption by up to 22 and 40%.

Electrocardiogram and Phonocardiogram Monitoring System for Cardiac Auscultation

Heart-sound auscultation is a rapid and fundamental technique used for examining the cardiovascular system. The main components of heart sounds are the first and second heart sounds. Discriminating these heart sounds under the presence of additional heart sounds and murmurs will be difficult. To recognize these signals efficiently, this study proposes a monitoring system with phonocardiogram and electrocardiogram. This system has two key points. The first is chip implementation, including capacitor coupled amplifier, transimpedance amplifier, high-pass sigma-delta modulator, and digital signal processing block. The chip in the system is fabricated in 0.18 μm standard complementary metal-oxide-semiconductor process. The second is a software application on smartphones for heart-related physiological signal recording, display, and identification. A wavelet-based QRS complex detection algorithm verified by MIT/BIH Arrhythmia Database is also proposed. The overall measured positive prediction, sensitivity, and error rate of the proposed algorithm are 99.90%, 99.82%, and 0.28%, respectively. During auscultation, doctors may refer to these physiological signals displayed on the smartphone and simultaneously listen to the heart sounds to diagnose the potential heart disease. By taking advantage of signal visualization and keeping the original diagnosis procedure, the uncertainty existing in heart sounds can be eliminated, and the training period to acquire auscultation skills can be reduced.

Design and Implementation of a High-Performance and High-Speed Architecture for Wideband Spectrum Sensing in Cognitive Radio Networks

One of the key functions of the cognitive radio (CR) is to detect free bandwidths in a radio frequency spectrum. High-speed and energy-inefficient analog-to-digital converters (ADCs) are generally employed for spectrum sensing in sideband signals. The high-rate ADCs provide a large volume of raw data for digital signal processing blocks, resulting in complex and energy-inefficient circuits and hardware resources in digital blocks. In many applications, the frequency spectrum is sparsely occupied by different users. In other words, only a few active frequency bands exist at the same time. This feature enables the CR application to employ sub-sampling approaches in order to design a system with a significant reduction in cost and power consumption and improvement in processing speed. This paper presents a novel real-valued sparse spread spectrum sensing algorithm (CR4S) based on a sub-sampling solution, which uses the sparsity of the frequency spectrum and the real-valued properties of the RF signal to detect free bandwidths with minimum computations. The CR4S algorithm utilizes techniques such as sparse fast Fourier transform, real-valued FFT, and collaborative spectrum sensing to improve spectrum sensing in the CR. The analysis and simulation of the proposed algorithm confirm it achieves above 95% detection performance. Furthermore, a high-throughput architecture with minimum resource utilization is suggested to implement the CR4S algorithm in the field-programmable gate array (FPGA). When implementing the CR4S algorithm, we reached 25% speed improvement and 30% increase in FPGA recourse utilization efficiency, in comparison with a similar study in the literature. The capabilities of the CR4S algorithm in performance enhancement and low hardware resource utilization are an emerging approach, which would be fascinating in portable CR devices.

Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs

Deep learning workloads, such as convolutional neural networks (CNNs) are important due to increasingly demanding high-performance hardware acceleration. One distinguishing feature of a deep learning workload is that it is inherently resilient to small numerical errors and thus works very well with low precision hardware. We propose a novel method called double multiply-and-accumulate (MAC) to theoretically double the computation rate of CNN accelerators by packing two MAC operations into one digital signal processing block of off-the-shelf field-programmable gate arrays (FPGAs). We overcame several technical challenges by exploiting the mode of operation in the CNN accelerator. We have validated our method through FPGA synthesis and Verilog simulation, and evaluated our method by applying it to the state-of-the-art CNN accelerator. The double MAC approach used can double the computation throughput of a CNN layer. On the network level (all convolution layers combined), the performance improvement varies depending on the CNN application and FPGA size, from 14% to more than 80% over a highly optimized state-of-the-art accelerator solution, without sacrificing the output quality significantly.

A Theoretical Framework for Quality Estimation and Optimization of DSP Applications Using Low-Power Approximate Adders

In this paper, we present a framework for analytically estimating the output quality of common digital signal processing (DSP) blocks that utilize approximate adders. The framework is based on considering the error of approximate adders as an additive noise (approximation noise) that disturbs the output of the DSP block in question. A signal processing theoretical modeling approach for describing the power of the approximation noise which is the integral of error spectral density over the bandwidth, is developed. The output qualities of DSP blocks, such as finite impulse response filter, discrete cosine transform, and fast Fourier transform, which utilize approximate adders, are thus estimated. The accuracy of the proposed framework is evaluated by comparing mathematical model predictions to simulation results by using the signal-to-noise ratio (SNR) metric. The inaccuracy of the SNRs predicted by the framework was, on average, less than 2.5dB compared with that obtained from simulations. Therefore, a mathematical optimization approach based on Lagrange Multipliers for optimizing design parameters is also presented. The optimization is realized by choosing a proper configuration of the target block, such as determining the data width of the inexact computation part for each approximate adder in the design.

Border Handling for 2D Transpose Filter Structures on an FPGA

It is sometimes desirable to implement filters using a transpose-form filter structure. However, managing image borders is generally considered more complex than it is with the more commonly used direct-form structure. This paper explores border handling for transpose-form filters, and proposes two novel mechanisms: transformation coalescing, and combination chain modification. For linear filters, coefficient coalescing can effectively exploit the digital signal processing blocks, resulting in the smallest resources requirements. Combination chain modification requires similar resources to direct-form border handling. It is demonstrated that the combination chain multiplexing can be split into two stages, consisting of a combination network followed by the transpose-form combination chain. The resulting transpose-form border handling networks are of similar complexity to the direct-form networks, enabling the transpose-form filter structure to be used where required. The transpose form is also significantly faster, being automatically pipelined by the filter structure. Of the border extension methods, zero-extension requires the least resources.

Hardware Design and Implementation of Adaptive Multiple Transforms for the Versatile Video Coding Standard

Versatile video coding is the next generation video coding standard expected by the end of 2020. Several new contributions have been proposed to enhance the coding efficiency beyond the high efficiency video coding standard. One of these tools is the adaptive multiple transform (AMT) as a new approach of the transform core design. The AMT involves five discrete cosine transform/discrete sine transform types with larger and more flexible partitioning block sizes. However, the AMT coding efficiency comes with the cost of higher computational complexity, especially at the encoder side. In this paper, a efficient pipelined hardware implementation of the AMT including the five types of sizes $4\times 4$ , $8\times 8$ , $16\times 16$ and $32\times 32$ is proposed. The architecture design takes advantage of the internal software/hardware resources of the target field-programmable gate array device such as library of parametrized modules core intellectual properties and digital signal processing blocks. The proposed 1-D 32-point AMT design allows to process 4K video at 44 frames/s. A unified 2-D implementation of the 4, 8, 16, and 32-point AMT design is also presented.The implementation takes into account all the asymmetric 2-D block size combinations from 4 to 32. The 2-D architecture design is able to sustain 2K video coding at 50 frames/s with an operational frequency up to 147 MHz.

A Hardware-Efficient Synchronization in L-DACS1 for Aeronautical Communications

L-band digital aeronautical communication system type-1 (L-DACS1) is an emerging standard that aims at enhancing air traffic management by transitioning the traditional analog aeronautical communication systems to the superior and highly efficient digital domain. L-DACS1 employs modern and efficient orthogonal frequency-division multiplexing (OFDM) modulation technique to achieve more efficient and higher data rate in comparison to the existing aeronautical communication systems. However, the performance of OFDM systems is very sensitive to synchronization errors such as symbol timing offset (STO) and carrier frequency offset (CFO). STO and CFO estimations are extremely important for maintaining orthogonality among the subcarriers for the retrieval of information. This paper proposes a novel efficient hardware synchronizer for L-DACS1 systems that offers robust performance at low power and low hardware resource usage. Monte Carlo simulations show that the proposed synchronization algorithm provides accurate STO estimation as well as fractional CFO estimation. Implementation of the proposed synchronizer on a widely used field-programmable gate array (FPGA) (Xilinx xc7z020clg484-1) results in a very low hardware usage which consumed 6.5%, 3.7%, and 6.4% of the total number of lookup tables, flip-flops, and digital signal processing blocks, respectively. The dynamic power of the proposed synchronizer is below 1 mW.

Statistically Reconstructed Multiplexing for Very Dense, High-Channel-Count Acquisition Systems.

Multiplexing is an important strategy in multichannel acquisition systems. The per-channel antialiasing filters needed in the traditional multiplexing architecture limit its scalability for applications requiring high channel density, high channel count, and low noise. A particularly challenging example is multielectrode arrays for recording from neural systems. We show that conventional approaches must tradeoff recording density and noise performance, at a scale far from the ideal goal of one-to-one mapping between neurons and sensors. We present a multiplexing architecture without per-channel antialiasing filters. The sparsely sampled data are recovered through a compressed sensing strategy, involving statistical reconstruction and removal of the undersampled thermal noise. In doing so, we replace large analog components with digital signal processing blocks, which are much more amenable to scaled CMOS implementation. The resulting statistically reconstructed multiplexing architecture recovers input signals at significantly improved signal-to-noise ratios when compared to conventional multiplexing with antialiasing filters at the same per-channel area. We implement the new architecture in a 65536-channel neural recording system and show that it is able to recover signals with performance comparable to conventional high-performance, single-channel systems, despite a more than four-orders-of-magnitude increase in channel density.

Multipumping Flexible DSP Blocks for Resource Reduction on Xilinx FPGAs

For complex datapaths, resource sharing can help reduce area consumption. Traditionally, resource sharing is applied when the same resource can be scheduled for different uses in different cycles, often resulting in a longer schedule. Multipumping is a method whereby a resource is clocked at a frequency that is a multiple of the surrounding circuit, thereby offering multiple executions per global clock cycle. This allows a single resource to be shared among multiple uses in the same cycle. This concept maps well to modern field-programmable gate arrays (FPGAs), where hard macro blocks are typically capable of running at higher frequencies than most designs implemented in the logic fabric. While this technique has been demonstrated for static resources, modern digital signal processing (DSP) blocks are flexible, supporting varied operations at runtime. In this paper, we demonstrate multipumping for resource sharing of the flexible DSP48E1 macros in Xilinx FPGAs. We exploit their dynamic programmability to enable resource sharing for the full set of supported DSP block operations, and compare this to multipumping only multipliers and DSP blocks with fixed configurations. The proposed approach saves on average 48% DSP blocks at a cost of 74% more LUTs, effectively saving 30% equivalent LUT area and is feasible for the majority of designs, in which clock frequency is typically below half the maximum supported by the DSP blocks.

Area‐ and power‐efficient iterative single/double‐precision merged floating‐point multiplier on FPGA

In this study, an area and power-efficient iterative floating-point (FP) multiplier architecture is designed and implemented on FPGA devices with pipelined architecture. The proposed multiplier supports both single-precision (SP) and double-precision (DP) operations. The operation mode can be switched during run time by changing the precision selection signal. The Karatsuba algorithm is applied when mapping the mantissa multiplier in order to reduce the number of digital signal processing (DSP) blocks required. For DP operations, the iterative method is applied which require much less hardware than a fully pipelined DP multiplier and thus reduces the power consumption. To further reduce the power consumption, the unused logic blocks for a specific operation mode are disabled. Compared to previous work, the proposed multiplier can achieve 33% reduction of DSP blocks, 4.3% less look-up tables (LUTs), and 31.2% less flip-flops while having 4% faster clock frequency on Virtex-5 devices. Compared to the intellectual property core DP multiplier provided by the FPGA vendors, the proposed multiplier required less DSP blocks and achieves lower-power consumption. The mapping solutions and implementation results of the proposed multiplier on Xilinx Virtex-7 and Altera Arria-10 devices are also presented. In addition, the results of a direct implementation of the proposed architecture on STM-90 nm ASIC platform are reported.

Design of retimed digital filters using MCM methodology for noise removal in EEG

High level synthesis of digital signal processing (DSP) systems converts the abstract behavioural specification in to register transfer level (RTL) description. The main objective of high level synthesis algorithms is to generate structure that satisfies various design constraints such as area, power and operating frequency. A modified MCM-based retiming algorithm is designed in this paper for DSP block optimisation. This is achieved by two ways in the present work. Firstly, pipelining and retiming is used as a high level synthesis optimisation methodology which can increase the operating frequency in sequential circuits such as digital filters. As the next step, MCM can be used to find the optimal solution for digital filters that gives implementation consisting of minimal number of shifters and adders/subtractors for a given constant co-efficient set. Electro-encephalography (EEG) is considered as an application in this work which requires sophisticated filters in removing the power noise and random noise introduced during the recording process.

Design of retimed digital filters using MCM methodology for noise removal in EEG

High level synthesis of digital signal processing (DSP) systems converts the abstract behavioural specification in to register transfer level (RTL) description. The main objective of high level synthesis algorithms is to generate structure that satisfies various design constraints such as area, power and operating frequency. A modified MCM-based retiming algorithm is designed in this paper for DSP block optimisation. This is achieved by two ways in the present work. Firstly, pipelining and retiming is used as a high level synthesis optimisation methodology which can increase the operating frequency in sequential circuits such as digital filters. As the next step, MCM can be used to find the optimal solution for digital filters that gives implementation consisting of minimal number of shifters and adders/subtractors for a given constant co-efficient set. Electro-encephalography (EEG) is considered as an application in this work which requires sophisticated filters in removing the power noise and random noise introduced during the recording process.

Recognization of Delay Faults in Cluster based FPGA using BIST

This paper discussed about the increasing complexity of Field-Programmable Gate Array (FPGA) in finding delay faults using BIST technique. It is a major challenge for FPGA for highest troubles shoot text and delay circuit quickly. Built-in-self-test method is a simple solution compared with expensive test equipment for the automatic transmission. Herein, the erection designed for the detection of delay faults in the second coefficient of FPGA resources Digital Signal Processing (DSP) block, FPGA board interconnects, Look-Up-Tables (LUT) and etc. The authors suggest comprehensive plan diagnose Bister to improve the effectiveness of the control logic, which diagnose all CLB 2 x 3 BIST are faulty. The overall process for the simulation has been done by tool Xilinx FPGA Vertex FPGA. The results show a significant improvement over previous methods.

Development of a new automatic control system for the harmonics analysis of distribution transformers

This paper presents a new automatic control system that can precisely and automatically analyze complex harmonics occurring from the power distribution transformers. The proposed system consists of pre-amplification block, digital signal processing block, and real-time monitoring block. It can be applied to a development board with a microcontroller connected to a PC to monitor harmonics in real time because it can be individually affixed to a transformer. The existing expensive harmonics measurement systems take a lot of time to analyze complex harmonics. Unlike the conventional systems, since this system is accurate and automatic in measurement, it provides very low measurement errors and very small test overhead. The proposed system showed very low measurement errors of less than 0.8% as well as fast real-time measurements of approximately 23sec. for harmonics analysis as compared to external expensive equipment measurements. We hope that this new system will provide industry with a simple and inexpensive technique to control and analyze complex harmonics occurring from the distribution transformers.

A power supply error correction method for single-ended digital audio class D amplifiers

ABSTRACTIn single-ended digital audio class D amplifiers (CDAs), the errors caused by power supply noise in the power stages degrade the output performance seriously. In this article, a novel power supply error correction method is proposed. This method introduces the power supply noise of the power stage into the digital signal processing block and builds a power supply error corrector between the interpolation filter and the uniform-sampling pulse width modulation (UPWM) lineariser to pre-correct the power supply error in the single-ended digital audio CDA. The theoretical analysis and implementation of the method are also presented. To verify the effectiveness of the method, a two-channel single-ended digital audio CDA with different power supply error correction methods is designed, simulated, implemented and tested. The simulation and test results obtained show that the method can greatly reduce the error caused by the power supply noise with low hardware cost, and that the CDA with the proposed method can achieve a total harmonic distortion + noise (THD + N) of 0.058% for a –3 dBFS, 1 kHz input when a 55 V linear unregulated direct current (DC) power supply (with the –51 dBFS, 100 Hz power supply noise) is used in the power stages.

Mapping for Maximum Performance on FPGA DSP Blocks

The digital signal processing (DSP) blocks on modern field programmable gate arrays (FPGAs) are highly capable and support a variety of different datapath configurations. Unfortunately, inference in synthesis tools can fail to result in circuits that reach maximum DSP block throughput. We have developed a tool that maps graphs of add/sub/mult nodes to DSP blocks on Xilinx FPGAs, ensuring maximum throughput. This is done by delaying scheduling until after the graph has been partitioned onto DSP blocks and scheduled based on their pipeline structure, resulting in a throughput optimized implementation. Our tool prepares equivalent implementations in a variety of other methods, including high-level synthesis (HLS) for comparison. We show that the proposed approach offers an improvement in frequency of 100% over standard pipelined code, and 23% over Vivado HLS synthesis implementation, while retaining code portability, at the cost of a modest increase in logic resource usage.

Design and Implementation of Booth Multiplier using Approximate Adders

Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. Keyword: Approximate computing, low power, mirror adder. Booths multiplier, Wallace tree multiplier I. INTRODUCTION Digital signal processing (DSP) blocks form the backbone of various multimedia applications used in portable devices. Most of these DSP blocks implement image and video processing algorithms, where the ultimate output is either an image or a video for human consumption. Human beings have limited perceptual abilities when interpreting an image or a video. This allows the outputs of these algorithms to be numerically approximate rather than accurate. This relaxation on numerical exactness provides some freedom to carry out imprecise or approximate computation. We can use this freedom to come up with low-power designs at different levels of design abstraction, namely, logic, architecture, and algorithm. The paradigm of approximate computing is specific to select hardware implementations of DSP blocks. It is shown in (1) that an embedded reduced instruction set computing processor consumes 70% of the energy in supplying data and instructions, and 6% of the energy while performing arithmetic only. Therefore, using approximate arithmetic in such a scenario will not provide much energy benefit when considering the complete processor. Programmable processors are designed for general-purpose applications with no application-specific specialization. Therefore, there may not be many applications that will be able to tolerate errors due to approximate computing. This also makes general-purpose processors not suited for using approximate building blocks. This issue has already been discussed in (13). Therefore, in this paper, we consider application-specific integrated circuit implementations of error-resilient applications like image and video compression.

Multiplierless Design of Folded DSP Blocks

This article addresses the problem of minimizing the implementation cost of the time-multiplexed constant multiplication (TMCM) operation that realizes the multiplication of an input variable by a single constant selected from a set of multiple constants at a time. It presents an efficient algorithm, called orpheus , that finds a multiplierless TMCM design by sharing logic operators, namely adders, subtractors, adders/subtractors, and multiplexors (MUXes). Moreover, this article introduces folded design architectures for the digital signal processing (DSP) blocks, such as finite impulse response (FIR) filters and linear DSP transforms, and describes how these folded DSP blocks can be efficiently realized using TMCM operations optimized by orpheus . Experimental results indicate that orpheus can find better solutions than existing TMCM algorithms, yielding TMCM designs requiring less area. They also show that the folded architectures lead to alternative designs with significantly less area, but incurring an increase in latency and energy consumption, compared to the parallel architecture.

Low‐precision DSP‐based floating‐point multiply‐add fused for Field Programmable Gate Arrays

Floating-point (FP) multiply-add fused ( F 1 * F 2 ±F 3 ) and multiply-accumulate represent the most common arithmetic operation in a wide range of applications, such as graphic processing, multimedia or FP digital signal processing (DSP). This study proposes FP multiply-add fused units for low-precision formats (IEEE 16-bit half precision or the 32-bit single precision) which rely on modern Field Programmable Gate Array (FPGA) features such as the available integer multiply-accumulate-based support built-in the FPGA DSP blocks. These are employed as building-blocks within the mantissa data-path processing for the multiplication and the add/subtract operations. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply-add stage: a right shift on the addend, and, a right shift for one of the multiplicands. This results in efficient DSP usage; thus both cost savings and higher performance (high working frequencies and low latencies) are obtained for the multiply-add fused operation.