Digital Intermediate Frequency Research Articles

A custom digital intermediate frequency filter for the American mobile telephone system

A digital filter for intermediate frequency filtering in mobile communication systems is presented. The purpose of the work is to show an alternative to the analog filters which are used in most of today's heterodyne receivers. Bit-serial arithmetic is applied on a twelfth-order wave digital lattice filter algorithm. The paper also shows a method for retiming such algorithms. The power consumption in two fabricated prototypes is compared. By customizing the library cells, the power consumption has been reduced significantly. In the low power prototype, the power dissipation is 8 mW using 3 V supply voltage. The prototype is a 10 MIPS design fabricated in a 0.8-/spl mu/m standard two-metal-layer CMOS process.

A two-path bandpass ΣΔ modulator for digital IF extraction at 20 MHz

Oversampled bandpass A/D converters based on sigma-delta (/spl Sigma//spl Delta/) modulation can be used to robustly digitize the types of narrowband intermediate frequency (IF) signals that arise in radios and cellular systems. This paper proposes a two-path architecture for a fourth-order, bandpass modulator that is more tolerant of analog circuit limitations at high sampling speeds than conventional implementations based on the use of switched-capacitor biquadratic filters. An experimental prototype employing the two-path topology has been integrated in a 0.6-/spl mu/m, single-poly, triple-metal CMOS technology with capacitors synthesized from a stacked metal structure. Two interleaved paths clocked at 40 MHz digitize a 200-kHz bandwidth signal centered at 20 MHz with 75 dB of dynamic range while suppressing the undesired mirror image signal by 42 dB. At low input signal levels, the mixing of spurious tones at DC and f/sub s//2 with the input appears to degrade the performance of the modulator; out-of-band sinusoidal dither is shown to be an effective means of avoiding this degradation. The experimental modulator dissipates 72 mW from a 3.3 V supply.

Computer-aided design of a BPSK spread-spectrum chip set

The design of a binary-phase shift-keyed (BPSK) spread-spectrum chip set with an integrated CAD environment called VANDA is described. VANDA uses the functional compiler concept to integrate system and physical designs, thus allowing complex high-performance integrated circuit chips to be implemented easily. Three functional compilers have been designed and implemented for the design of a spread-spectrum transceiver: a pseudonoise (PN) generator compiler, a direct digital frequency synthesizer (DDFS) compiler, and a Costas loop compiler. Three test chips for a BPSK digital intermediate frequency (IF) spread-spectrum system generated by these compilers have been fabricated and tested. Details of each of the functional compilers and the test chips are described. In addition, the measurement results for digital IF transceiver test boards constructed using these chips are presented. >