Digital Delta-sigma Modulator Research Articles

Hardware‐efficient multi‐channel digital sigma‐delta modulator

A method for implementing a hardware-efficient multi-channel digital sigma-delta modulator is presented for processing field sequential multiple inputs. Compared to a conventional one, which processes the inputs in a time-multiplexed manner without sharing integrator memory for the multiple sequential inputs, the proposed method significantly reduces the number of storage bits in the integrator memory by partially sharing the integrator memory for the inputs. Simulation results on modulator noise power spectral density and overall signal-to-noise ratio match well with those based on quantitative noise analysis.

Masked Dithering of MASH Digital Delta-Sigma Modulators With Constant Inputs Using Multiple Linear Feedback Shift Registers

The output signal of a digital delta-sigma modulator (DDSM) with a constant input may has a small fundamental period and therefore its spectrum may be characterized by a small number of strong periodic tones. Pseudorandom dither can be used to break up the tones, but it is indistinguishable from signal. The dither signal can be masked by using short sequence lengths but this may result in ineffective dithering and consequent tonal behavior. This paper shows how to use multiple shaped dither signals which are masked by the shaped quantization noise of the DDSM and yield a long fundamental output period.

A 1–3 GHz Delta–Sigma-Based Closed-Loop Fully Digital Phase Modulator in 45-nm CMOS SOI

This paper presents a new fully digital architecture for an RF phase modulator with significantly improved phase resolution. The modulator utilizes 32 variable delay-lines in a delay-locked loop (DLL) configuration to provide 1–3 GHz operation with coarse 5-bit resolution. A 5-bit low-glitch multiplexer with accurate delay control on the control lines is used to select different taps of the DLL according to the baseband digital phase data to generate the desired phase modulated signal at the output. To further increase the effective resolution, a high speed 10-bit input, 5-bit output digital delta–sigma modulator (DSM) is added in front of the multiplexer. The DSM compensates for the phase truncation occurring in the 5-bit DLL. The impact of delay mismatch and phase offset in the DLL on the phase modulator output performance are studied. The phase modulator IC is implemented in 45-nm CMOS SOI and achieves <2% rms EVM together with 55-dB rejection of close-to-carrier emissions for an 8-Mb/s GMSK signal at 2.3 GHz, with power consumption below 35 mW.

Influence of Initial Conditions on the Fundamental Periods of LFSR-Dithered MASH Digital Delta–Sigma Modulators With Constant Inputs

A digital delta–sigma modulator (DDSM) with a constant input may produce a periodic output with a small fundamental period, resulting in strong tonal output behavior instead of the expected shaped white quantization noise. In practice, the problem is alleviated by dithering the DDSM. Pseudorandom dither generators based on linear feedback shift registers (LFSRs) are widely used to “break up” periodic cycles in DDSMs with constant inputs. Pseudorandom dither signals are themselves periodic and can lead to relatively short output sequences from dithered DDSMs. It is known that the fundamental period of the output signal depends not only on the input and the initial condition of the DDSM but also on the initial state of the LFSR. This brief shows that bad LFSR initial conditions can lead to ineffective dithering, producing short cycles and strong tonal behavior. Furthermore, it explains how to set the initial state of the DDSM as a function of the initial state of the LFSR in order to obtain a maximum-length dithered output.

Masked Dithering of MASH Digital Delta-Sigma Modulators with Constant Inputs Using Linear Feedback Shift Registers

Digital delta-sigma modulators (DDSMs) are finite state machines; their spectra are characterized by strong periodic tones (so-called spurs) when they cycle repeatedly in time through a small number of states. This is particularly likely to happen when the input is constant or periodic. Dither generators based on linear feedback shift registers (LFSRs) are widely used to break up periodic cycles in DDSMs in order to eliminate spurs produced by underlying periodic behavior. Unfortunately, pseudorandom dither signals produced by LFSRs are themselves periodic and therefore may have limited effectiveness. This paper presents a rigorous mathematical analysis of DDSMs with LFSR-based pseudorandom dither, and a design methodology to achieve effectively masked dithering.

A Novel Architecture of Pseudorandom Dithered MASH Digital Delta-Sigma Modulator with Lower Spur

A Digital Delta Sigma Modulator (DDSM) is a Finite State Machine (FSM); it is implemented using finite precision arithmetic units and the number of available states is finite. The DDSM always produces a periodic output signal when the input is constant. This paper proposes a novel method of applying periodic dither to a DDSM in order to obtain minimized spurious tones. The effects of adding the pseudorandom dither signal in different stages within the proposed Multi-Stage noise Shaping (MASH) modulator are expressed in the equations, and the results are compared. We present results regarding the periodicity of the quantization noise produced by a MASH modulator with a constant input and a pseudorandom dither signal. The performance is confirmed mathematically, and by simulation.

A fast automatic frequency and amplitude control LC-VCO circuit with noise filtering technique for a fractional-N PLL frequency synthesizer

This work presents the design of an automatic frequency and amplitude control LC VCO circuit with noise filtering technique for fractional-N PLL frequency synthesizers. The LC VCO frequency of operation is from 2.158GHz to 5.133GHz. Phase noise of the LC VCO at 1MHz offset frequency is −123.0dBc/Hz and −116.8dBc/Hz for carrier signal frequency of 2.158GHz and 5.133GHz, respectively. The power consumption of the LC VCO without buffer circuit is 5.14mW from a 1.2V power supply and the fractional-N PLL has been implemented in 0.13μm standard CMOS process. A binary search fast frequency calibration process greatly reduces the overall locking time of the fractional-N PLL frequency synthesizers along with proposed PFD and a CP switching circuit and an efficient pulse swallow based fractional divider circuits, fractional bits are controlled by the HK-MASH 111 Digital Delta Sigma Modulator (DDSM). The fractional-N PLL is coarsely tuned within the maximum time of 1.825μs and the fractional-N PLL is locked within 4μs considering the worst case coarse tuning condition.

A novel structure of dithered nested digital delta sigma modulator with low-complexity low-spur for fractional frequency synthesizers

Purpose – Digital Delta Sigma Modulator (DDSM) is used widely in electronic circuits including Radars, class-D power amplifiers and fractional frequency synthesizers. The purpose of this paper is to propose an implementation for MASH DDSMs named as Multi Modulus Reduced Complexity (MMRC) architecture. Design/methodology/approach – This architecture will use a very simple pseudorandom Linear Feedback Shift Register (LFSR) dither signal with period N_d to randomize the digital MMRC modulator used for fractional frequency synthesizers. Using error masking methodology, the MMRC modulator can decrease the hardware consumption and increase accuracy of the fractional frequency synthesizer. Rules for selecting the appropriate word lengths of the constituent MMRC modulator are derived. Findings – This paper contains three modulators. The first stage modulator is a variable modulus First Order Error Feedback Modulator and has a programmable modulus M1 that is not a power of two. The second and third stage modulators are the first order pseudorandom LFSR dithered MASH 1-1 and modified MASH 1-1-1, which have conventional modulo M2, M3, respectively. With optimum selection modulus M1, the new structure can synthesize the desired frequency exactly. Simulation results confirm the theoretical predictions. Also the results of circuit implementation proposed method reports 13 per cent reduction in hardware. Originality/value – This paper for the first time proposes a nested sigma delta modulator with a pseudorandom shaped dither signal which reduced hardware complexity and increased the period of output signal. This modulator is exploited in the fractional frequency synthesizer to the output frequency can be set more accurately.

Delta-Sigma Digital-to-Time Converter for Band-Select Spread Spectrum Clock

This paper proposes an innovative method of converting digital signal to time-domain analog signal, which fully enjoys robustness and digital circuit friendliness. This technique utilizes a digital delta-sigma ( ) modulator following a digital-to-time converter (DTC) circuit with various modulation methods. As an application of the proposed method, novel spreadspectrum clock generation (SSCG) algorithms (such as for DC-DC converters) have been investigated which can select the noise spectrum spread bands; e.g., they can exclude the noisespectrum spread in AM, FM radio bands. The proposed circuit takes advantage of digital technology, which is simple, fast (reachable at high clock frequency) and flexible (programmable).

Design and implementation of novel FPGA based time-interleaved variable centre-frequency digital Σ−Δ modulators

Multiresolution analog-to-digital converters (MRADC) are usually used in Time Domain ElectroMagnetic Interference (TDEMI) measuring systems for very fast signal sampling with a sufficient dynamic range. The properties of the spectrum measured by the TDEMI system influenced by imperfections in the MRADC are analyzed in this paper. Errors are caused by imperfect matching of the offset and gain and phase of the circuits used in parallel input channels typical for the MRADC. For deep analyses of MRADC behavior, a precise mathematical model has been created using the concept of additive error pulses. Furthermore, a dedicated process of the identification of discrepancy parameters from experimental data is proposed. Identified parameters enter the expressions of the model and enable side to side comparison of experimental and theoretical results.Novel, multi-path, time-interleaved digital sigma-delta modulators that can operate at any arbitrary frequency from DC to Nyquist are designed, analysed and synthesized in this study. Dual- and quadruple-path fourth-order Butterworth, Chebyshev, Inverse Chebyshev and Elliptical based digital sigma-delta modulators, which offer designers the flexibility of specifying the centre-frequency, pass-band/stop-band attenuation as well as the signal bandwidth are presented. These topologies are compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity to non-idealities. Detailed simulations performed at the behavioural-level in MATLAB are compared with the experimental results of the FPGA implementation of the designed modulators. The signal-to-noise ratios between the simulated and empirical results are shown to be different by not more than 3-5 dBs. Furthermore, this paper presents the mathematical modelling and evaluation of the tones caused by the finite wordlengths of these digital multi-path sigma-delta modulators when excited by sinusoidal input signals.

Spurious tones in digital delta-sigma modulators resulting from pseudorandom dither

Digital delta-sigma modulators (DDSMs) are finite state machines; their spectra are characterized by strong periodic tones (so-called spurs) when they cycle repeatedly in time through a small number of states. This happens when the input is constant or periodic. Pseudorandom dither generators are widely used to break up periodic cycles in DDSMs in order to eliminate spurs produced by underlying periodic behavior. Unfortunately, pseudorandom dither signals are themselves periodic and therefore can have limited effectiveness. This paper addresses the fundamental limitations of using pseudorandom dither signals that are inherently periodic. We clarify some common misunderstandings in the DDSM literature. We present rigorous mathematical analysis, case studies to illustrate the issues, and insights which can prove useful in design.

A Self-Sustaining Integrated CMOS Regulator for Solar and HF RFID Energy Harvesting Systems

This paper presents a self-sustaining integrated regulator for ultralow power two-input energy harvesting systems. The energy sources include photovoltaic panels and high frequency radio-frequency identification tags. An input-powered charge pump utilizing dynamic charge transfer switches with tunable voltages at the bottom of the pumping capacitors is proposed. No external pulse signal is required. An output-powered digitally controlled dc-dc switching converter with a low-complexity oversampling analog-to-digital converter is also proposed to analyze the error signal between the dc-dc switching converter output and the reference voltage. In order to avoid limit-cycle oscillation, a digital sigma-delta modulator is adopted to increase the equivalent resolution of the digital pulsewidth modulator. The system is completely implemented and fully integrated in a standard 0.18-μm CMOS process with a die area of 2.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The system output voltage is successfully regulated at 1 V and the measured maximum end-to-end conversion efficiency is ~57%, when the loading current is 65 μA.

0.3–4.3 GHz Frequency-Accurate Fractional-$N$ Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital $\Delta$-$\Sigma$ Modulator-Based Divider Controller

If the modulus of the digital delta-sigma modulator (DΔΣM) in a fractional- N frequency synthesizer is a power of two, then the output frequency is constrained to be a rational multiple of the phase detector frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PD</sub> ), where the denominator of the rational multiplier is a power of two. If the required output frequency is not related to f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PD</sub> in this way, one is forced to approximate the ratio by using a small programmable modulus DΔΣM or a very large power-of-two modulus. Both of these solutions involve additional hardware. Furthermore, the programmable modulus solution can suffer from spurs, while the large power of two lacks accuracy. This paper presents a new solution, based on mixed-radix algebra, where the required ratio is formed by combining two different moduli. The programmable modulus solves the accuracy problem, while the large power-of-two modulus minimizes the spur content. In addition, the phase detector can be clocked at high speed. This paper explains the theoretical foundations of the method, elaborates a design methodology, and presents measured results for an 0.18 μm SiGe BiCMOS prototype.

Low-Power and High-Efficiency Class-D Audio Amplifier Using Composite Interpolation Filter for Digital Modulators

This paper presents a high-efficiency digital class-D audio amplifier using a composite interpolation filter for portable audio devices. The proposed audio amplifier is composed of an interpolation filter, a delta-sigma modulator, and a class-D output stage. To reduce power consumption, the designed interpolation filter has an optimized composite structure that uses a direct-form symmetric and Lagrange FIR filters. Compared to the filters with homogeneous structures, the hardware cost and complexity are reduced by about half by the optimization. The coefficients of the digital deltasigma modulator are also optimized for low power consumption. The class-D output stage has gate driver circuits to reduce shoot-through current. The implemented class-D audio amplifier exhibited a high efficiency of 87.8 % with an output power of 57 mW at a load impedance of 16 6 and a power supply voltage of 1.8 V. An outstanding signal-to-noise ratio of 90 dB and a total harmonic distortion plus noise of 0.03 % are achieved for a single-tone input signal with a frequency of 1 kHz.

Observations concerning PFD/CP operating point offset strategies for combatting static charge pump mismatch in fractional-&lt;I&gt;N&lt;/I&gt; frequency synthesizers with digital delta-sigma modulators

Observations concerning PFD/CP operating point offset strategies for combatting static charge pump mismatch in fractional-&lt;I&gt;N&lt;/I&gt; frequency synthesizers with digital delta-sigma modulators

Reducing Complexity and Power of Digital Multibit Error–Feedback $\Delta\Sigma$ Modulators

In this brief, we propose how the hardware complexity of arbitrary-order digital multibit error-feedback delta-sigma modulators can be reduced. This is achieved by splitting the combinatorial circu ...

The Role of Charge Pump Mismatch in the Generation of Integer Boundary Spurs in Fractional-N Frequency Synthesizers: Why Worse Can Be Better

Fractional-N frequency synthesizers exhibit spurious tones (spurs). Spurs outside the loop bandwidth can be attenuated by the loop filter. By contrast, in-band spurs cannot be removed by filtering and are therefore a major cause for concern. The frequency-to-phase conversion of the output of a digital sigma-delta modulator followed by charge-pump mismatch is known to cause in-band spurs; larger mismatch is thought to make the problem worse. By considering a simplified nonlinear model of the mechanism, we show how larger mismatch can paradoxically make the spur problem disappear. We illustrate our predictions using a simplified MATLAB model and confirm them by simulation using the CppSim behavioral simulator.

A Class-D Amplifier for a Digital Hearing Aid with 0.015% Total Harmonic Distortion Plus Noise

A class-D audio amplifier for a digital hearing aid is described. The class-D amplifier operates with a pulsecode modulated (PCM) digital input and consists of an interpolation filter, a digital sigma-delta modulator (SDM), and an analog SDM, along with an H-bridge power switch. The noise of the power switch is suppressed by feeding it back to the input of the analog SDM. The interpolation filter removes the unwanted image tones of the PCM input, improving the linearity and power efficiency. The class-D amplifier is implemented in a 0.13-μm CMOS process. The maximum output power delivered to the receiver (speaker) is 1.19 mW. The measured total harmonic distortion plus noise is 0.015%, and the dynamic range is 86.0 dB. The class-D amplifier consumes 304 μW from a 1.2-V power supply.

A Class-D Amplifier With Pulse Code Modulated (PCM) Digital Input for Digital Hearing Aid

A class-D amplifier with pulse code modulated (PCM) digital input is developed for a low-power digital hearing aid. A 16-bit 40-kbps PCM digital input is noise-shaped by a third-order digital sigma-delta modulator (SDM) which provides 1.5-bit digital output. The 1.5-bit digital output of the digital SDM is converted to a three-level analog signal by a simple digital-to-analog converter (DAC) and then applied to an analog SDM. The analog SDM provides pulse density modulated (PDM) signal to drive a power switch. The PDM output is fed back to the input of the analog SDM in order to suppress the noise of the power switch. While the integrators of the analog SDM are implemented with switched-capacitor (SC) circuits for a well-defined frequency response of the modulator loop filter, the feedback path from the power switch output is realized with a continuous-time (CT) integrator for effective noise suppression. The class-D amplifier with PCM digital input has been implemented in a standard 0.13-μm CMOS process. With 160-Ω load of speaker, the maximum output power delivered to the load is 1.14-mW while the efficiency of the power switch is 97-%. The signal\mathchar702D to\mathchar702D noise+distortionnratio (SNDR) and dynamic range (DR) of the class-D amplifier are measured to be 80.6-dB and 87-dB, respectively. The class-D amplifier consumes 0.38-mW from a 1.2-V power supply including the driving power of the power switch.

오디오 D/A 컨버터를 위한 인터폴레이티드 디지털 델타-시그마 변조기

디지털 입력 D급 증폭기는 보청기에서 사용되고 있으며 D급 증폭기는 디지털 회로와 아날로그 회로로 구성되어진다. 아날로그 회로는 가청 주파수 대역에서 잡음을 억제하고 디지털 입력을 아날로그 신호로 변환한다. 본 논문에서 제안한 인터폴레이티드 디지털 델타-시그마 변조기는 디지털 신호 처리기의 출력 신호를 D/A 변조기 입력에 적합하도록 데이터를 변조시킨다. 디지털 필터는 16-bit, 25-kbps 펄스 코드 변조 신호를 16-bit, 50-kbps 신호로 보간 작업을 한다. 이 보간 필터 출력은 3차 디지털 델타-시그마 변조기를 통하여 노이즈 쉐이핑(noise shaping) 처리된다. 최종적으로, 1.5-bit, 3.2-Mbps 신호가 D/A변조기 입력으로 인가된다.