Digitally Controlled Oscillator Research Articles

Modification over Dithered DPLL to reduce the effect of narrowband channel interference

Digital signal processing based digital phase locked loop (DSP DPLL) are most commonly used for carrier phase tracking in the recent times. Phase locked loop (PLL) behaves in nonlinear fashion at the time of signal acquisition. The linearity is restored in the PLL behavior once acquisition is over and signal tracking is taking place. But the same PLL or DSP-DPLL shows non-linearity both during acquisition and tracking when narrowband channel interference is present in the received signal. In this paper, a single tone signal is introduced as channel interference to study the effect on DPLL and its modified versions. To overcome the effect of channel interference, a single tone dither signal is included in the loop of DPLL. Although an improvement in acquisition and tracking performance is observed, but addition of dither signal contributes to the phase error variance and consequently output noise to increase. Therefore, a further modification is proposed by incorporating an additional phase control in the digital control oscillator (DCO) of the loop to improve the output SNR. The proposed loop is implemented on reconfigurable logic platform using System Generator, a tool from Xilinx used to design real time DSP application. The hardware simulation results demonstrate a comparison among traditional DPLL, dithered DPLL and phase controlled dithered DPLL where the proposed version of the loop outperforms others in terms of acquisition and noise rejection. Keywords DSP Digital Phase Locked Loop, Phase Controlled DPLL, Channel Interference, Dither DPLL, VHDL System Design, Modified DCO

A 5.5–7.5‐GHz band‐configurable wake‐up receiver fully integrated in 45‐nm RF‐SOI CMOS

This work investigates a 5.5–7.5-GHz band-configurable duty-cycled wake-up receiver (WuRX) fully implemented in a 45-nm radio-frequency (RF) silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) technology. Based on an uncertain intermediate frequency (IF) super-heterodyne receiver (RX) topology, the WuRX analogue front-end (AFE) incorporates a 5.5–7.5-GHz band-tunable low-power low-noise amplifier, a low-power Gilbert mixer, a digitally controlled oscillator (DCO), a 100-MHz IF band-pass filter (BPF), an envelope detector, a comparator, a pulse generator and a current reference. By application of duty cycling with a low duty cycle below 1%, the power consumption of the AFE was significantly reduced. In addition, the on-chip digital bank-end consists of a frequency divider, a phase corrector, a 31-bit correlator and a serial peripheral interface. A proof-of-concept WuRX circuit occupying an area of 1200 μm by 900 μm has been fabricated in a GlobalFoundries 45-nm RF-SOI CMOS technology. Measurement results show that at a data rate of 64 bps, the entire WuRX consumes only 2.3 μW. Tested at 8 operation bands covering 5.5–7.7 GHz, the WuRX has a measured sensitivity between −67.5 dBm and −72.4 dBm at a wake-up error rate of 10−3. With the sensitivity unchanged, the data rate of the WuRX can be scaled up to 8.2 kbps. To the authors' best knowledge, this work offers the largest RF bandwidth from 5.5 to 7.5 GHz, the most operation channels (≥8) and the fastest settling time (<115 ns) among the WuRXs reported to date.

A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for Wireline Applications

This article presents a 23.9–29.4 GHz digital <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -phase-locked loop (PLL) architecture with a low phase noise (PN) and power-efficient coupled frequency doubler for 224 Gb/s PAM-4 transmitter clocking. The proposed frequency doubler is designed with two oscillators running at 14 and 28 GHz which are coupled by a transformer. Compared to a conventional frequency doubler or a two-way coupled oscillator, the coupling between the 14 and 28 GHz oscillators provides extra PN reduction as the 14 GHz oscillator can achieve lower PN than the 28 GHz one. In addition, by stacking the two oscillators through the transformer, the current is reused and hence power consumption is reduced. To optimize the PN performance across process, voltage, and temperature (PVT), a compact and power-efficient frequency-tracking loop (FTL) is implemented. The 14 GHz oscillator output is fed to the PLL feedback divider rather than the doubled output, which enables power saving in the prescaler divider in the feedback path. The proposed PLL is fabricated in 10 nm FinFET technology and the PLL achieves a 65 fs random jitter at the transmitter output after a 1st-order 4 MHz-BW CDR filtering which enables the industry’s first 224 Gb/s PAM-4 transmitter. Compared with a reference NMOS-GM <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -digitally controlled oscillator (DCO) implemented on the same die, the proposed coupled frequency doubler achieves 4.75 dB lower PN with only a 25% power consumption increase. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -PLL consumes 17.1 mW from a 0.8/1.0 V regulated supply and occupies an area of 0.088 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Time-domain modelling and performance research of millimeter-wave all-digital phase-locked loop

In this paper, a modified time-domain model of millimeter-wave all-digital phase-locked loop (ADPLL) is implemented. In order to reflect the true behaviour of ADPLL, a quantified output digitally controlled-oscillator (DCO) with time domain jitter is proposed. In this ADPLL time-domain model, the DCO model can only output discrete frequency points to imitate the quantization effect of true DCO, and the overlap of different level tuning band is added into this model to imitate the true situation. In addition, the DCO time domain jitter and wander are also added into this model by using the Box-Muller method. Finally, a period estimation method is used to calculate the phase power spectrum density of the output signal, and then the phase noise is obtained through subsequent processing.

A Compact 0.2–0.3-V Inverse-Class-F23 Oscillator for Low 1/f 3 Noise Over Wide Tuning Range

We introduce a new mode of oscillation in an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -tank: an inverse class-F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">23</sub> . In contrast to the conventional class-F oscillators, in which a high value of the real impedance (i.e., resistance) is presented to the third (in class-F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) or/and to the second (in class-F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /class-F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">23</sub> ) oscillator harmonics via an auxiliary resonance, here low resistive impedances (resembling a non-ideal short) are presented at both the second and third harmonics. This is made possible by tight magnetic coupling in the differential and common modes, respectively, afforded by a new compact 2:3 transformer. Being largely free from the harmonics in the voltage waveform and their possible deleterious phase shift effects on the flicker noise up-conversion, the phase noise performance in the flicker and thermal regions is further improved by narrowing the conduction angle. The 2:3 step-up transformer also provides a high passive gain to help with the startup in face of low supply. The switched-capacitor banks and cross-coupled transistor pair are carefully integrated under the transformer with a special arrangement of native (high-resistivity) substrate layer to mitigate their effect on the oscillation while reducing the area by 30%. The proposed digitally controlled oscillator (DCO) is implemented in 28-nm CMOS and achieves −95 dBc/Hz and −118 dBc/Hz at 100 kHz and 1 MHz offsets, respectively, while operating at a 0.3 V supply. The measured <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1/f^{3}$ </tex-math></inline-formula> corner stays within 60 to 100 kHz over the 35% tuning range (TR) (from 2.02 to 2.87 GHz). This results in a figure-of-merit (FoM) with normalized TR (FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of −196 and −199 dB at 100 kHz and 1 MHz offsets, respectively, is a record in the space of ≤0.5 V and ≤1 mW.

A Fast-Settling Frequency Synthesizer Using Statistical Frequency Measurement Method

This work presents a reconfigurable RF frequency synthesizer implemented with the field programmable gate array (FPGA) and the digital-controlled oscillator (DCO) fabricated in 0.18-&#x03BC;m CMOS technology. The frequency synthesizer uses a fractional frequency ratio calculator (FRC) to measure the DCO output frequency and realize frequency locking. Thanks to the FRC, the correlation of the DCO frequencies and its control codes can be characterized and stored in a look-up table (LUT) of the FPGA without the need of external measurement instruments. When requested to settle at a new frequency, the synthesizer looks for the DCO control code from the LUT and performs the frequency locking routine. The synthesizer covers a wide frequency output range from 496 MHz to 2470 MHz with the resolution of 195 kHz and achieves a settling time of 32.5 - 45 nanoseconds.

A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems

An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digital multiplying delay-locked loop (MDLL) to provide fast locking time and multiplied output clock frequency. The proposed MDLL has two operation modes: TDC tracking and sequential tracking. At the beginning of the operation, the MDLL utilizes a cyclic Vernier time-to-digital converter (TDC) to detect the initial phase error between the reference clock and the output clock. Then the TDC generates a digital code word (DCW) for controlling the digitally controlled oscillator (DCO) to achieve a fast lock time. The gains of TDC and DCO are designed to match well with each other, enabling phase and frequency locking in only two searches in the TDC tracking mode. After locking, the TDC is turned off, and the MDLL performs the sequential tracking mode and minimizes jitter by using the delta-sigma modulator (DSM)-based dithering jitter reduction scheme. The prototype all-digital MDLL is fabricated in a 40-nm CMOS process and achieves a fast lock time of less than six reference clock cycles at 1.6 GHz from a 100 MHz reference clock. Even when the 100 MHz reference clock has a relatively high RMS jitter of 2.19 ps (peak-to-peak jitter =15.74 ps), the measured RMS and peak-to-peak jitter values of the 1.6 GHz MDLL output clock are only 2.75 ps and 23.01 ps, respectively. The proposed all-digital MDLL occupies an active area of only 0.024 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 3.56 mW at 1.6 GHz.

A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS

This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed hybrid time-to-digital converter (TDC) extends the vernier-TDC input range with little power overhead in order to overcome the stability issue in the conventional architectures. The hybrid TDC also facilitates a background gain calibration to achieve a stable in-band phase noise insensitive to process, voltage, and temperature (PVT) variations. The implementation of a buffer-cascaded DTC simplifies the design complexity of the fractional-N operation. The ADPLL also features a 200<inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> low-phase-noise inverse-class-F (class-F^&#x2212;1) digitally controlled oscillator (DCO) without the need of two-dimensional (2-D) capacitor tuning for frequency alignment of the fundamental and 2^nd-harmonic. Fabricated in 65-nm CMOS, the ULP ADPLL prototype achieves 868fs_rms jitter in a fractional-N channel when consuming only 529<inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula>, corresponding to a figure-of-merit (FoM) of &#x2212;244dB.

A Spurious and Oscillator Pulling Free CMOS Quadrature LO-Generator for Cellular NB-IoT

A reconfigurable LO-generator (LOG) using an integer divider and a mixed-mode fractional divide-by-2.5 (Div2.5) is presented to generate a spurious and oscillator pulling free output spectrum without additional digital calibration for cellular narrowband Internet of Things (NB-IoT). The proposed LOG includes a fractional divider to mitigate the pulling effect between the oscillator and the power amplifier. The designed fractional Div2.5 consists of a digital Div2.5 core, a duty cycle corrector (DCC), and an I/Q generator (I/Q-GEN). An adaptive bias circuit (ADB) is applied to compensate for process, voltage, and temperature (PVT) variations on delay circuits of the DCC and the I/Q-GEN by adjusting the supply voltage. The designed LOG is fabricated in the 28-nm CMOS process while consuming 40 mW, including ADPLL, digitally controlled oscillator (DCO), local oscillator (LO) distribution buffers, and dividers at 2 GHz. The measured phase noise of the Div2.5 LOG generating 2-GHz carrier frequency is −146.3 dBc/Hz at a 10-MHz offset. The measured fractional spurious tones are below −90 dBc without oscillator pulling effects for the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.6\sim 2.1$ </tex-math></inline-formula> -GHz output frequency.

ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) TOPOLOGIES FOR RFID SYSTEM APPLICATION: A REVIEW

An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. This paper reviews some state-of-art of the ADPLL structures based on their applications and analyses its major implementation block, which is the digital-controlled oscillator (DCO). The DCO is evaluated based on its CMOS scaling and its performance in ADPLL, such as the power consumption, the chip area, the frequency range, the supply voltage, and the phase noise. Based on the review, the reduction in CMOS scaling decreases the transistor size in ADPLL design which leads to a smaller area and a low power dissipation. The combination of the time-to-digital (TDC) and the digital-to-time converter (DTC) that is used as the phase-frequency detector (PFD) in ADPLL is proposed to reduce the power and phase noise performance due to their high linearity design. The delay cell oscillator is found to consume more power at higher operating frequency, but it has an advantage of having less complexity and consuming less power and area in the circuit compared to the LC tank oscillator. For future work, it is recommended that an ADPLL-based LO of RFID transceiver with lowest voltage supply implementation is chosen and the use of the TDC-less as the PFD is selected due to its small area. While for the DCO, the delay cell will be designed due to its simpler implementation and occupy small area.

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5 MeV cm2 mg−1 as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40 MHz to 320 MHz or at data rates from 40 Mbps to 320 Mbps and displays a jitter performance of 520 fs with a power dissipation of only 11 mW and an FOM of −235 dB.

Spectral Breathing and Its Mitigation in Digital Fractional-N PLLs

Although digital phase-locked loops (PLLs) offer several advantages over their analog counterparts, they suffer from a major disadvantage that is rarely mentioned in published articles. The disadvantage, known as spectral breathing, is caused by component mismatches among the frequency control elements within a PLL’s digitally controlled oscillator (DCO). The mismatches introduce DCO frequency modulation nonlinearity which fluctuates and, therefore, causes erratic variations in the PLL’s measured phase noise spectrum as the DCO’s free-running frequency drifts. The phenomenon is called spectral breathing because the measured phase noise spectrum tends to slowly swell and contract over time as if taking breaths of air. During these breaths, the PLL’s phase noise often becomes severely degraded. This article presents an experimental demonstration of the spectral breathing phenomenon and its solution in a digital fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> PLL. The demonstrated solution is a multi-rate dynamic element matching technique and a mismatch-noise cancellation technique that together eliminate spectral breathing.

Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur

This article presents a low jitter, low power, low reference spur LC oscillator-based reference oversampling digital phase locked loop (OSPLL). The proposed reference oversampling architecture simultaneously offers a low in-band phase noise, a wide-bandwidth, and a low spur. In addition, this article proposes an LC digitally controlled oscillator (DCO) for the proposed OSPLL to achieve a fast frequency update and fine frequency resolution, while its varactor switching timing is set optimally for low jitter using the proposed DCO tuning pulse timing control scheme. The proposed OSPLL was fabricated in a 28-nm CMOS process. The integrated rms jitter of the PLL was measured at 67.1 fs for an output frequency of 4 GHz. The in-band phase noise of the PLL was −129.2 and −132.5 dBc/Hz at 1- and 5-MHz offset frequencies. The measured reference spur of the PLL was −78.1 dBc. Total PLL power consumption was 5.2 mW, resulting in −256.3-dB PLL jitter-power FoM, while occupying 0.17-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area.

A Flexible Digitally Controlled Oscillator Structure to Reconfigure the Frequency Band in Multi-band RF AD-PLL System

Reconfigurable architectures are more prominent in modern-day multi-band radio systems. This work has been conceptualized for a flexible 8-bit digitally controlled oscillator (DCO) design to suit reconfigurable RF all-digital phase-locked loop applications. To efficiently utilize the area, power consumption and attend to several operating frequencies, an optimal design of LC-tank based DCO topology with both L and C components contributing to the coarse and fine-tuning of the DCO’s frequency of oscillation has been proposed. The design has been carried out in the Cadence Spectre RF tool with UMC180 nm technology. The proposed 8-bit DCO exhibits wide bandwidth, generating 240 oscillating frequencies in the LTE frequency band and occupies less area of 70 × 18 µm. The frequency of oscillation varies from 491.5 MHz to 3.392 GHz designed for an 8-bit digital control word with a tuning range percentage of 149%. The maximum phase noise obtained is −103.57 dBc/Hz @ 10 MHz offset causing a figure of merit (FOM) of −144.167 dBc/Hz. The total power consumed by the DCO ranges from 1.05 to 9.5 mW approximately.

Power-Optimized Digitally Controlled Oscillator in 28-nm CMOS for Low-Power FMCW Radars

This work presents the design of a 24-GHz digitally controlled oscillator (DCO) in an advanced 28-nm bulk CMOS technology for short-range frequency-modulated continuous-wave radar system-on-chip for mobile and Internet-of-Things devices. The power minimization is therefore the primary focus. The oscillator consumes a record low power of 1.2 mW at a 0.65-V supply voltage. It achieves a very large frequency tuning range (TR) of 5.8 GHz (27%) and a 150 kHz resolution without significantly degrading the phase noise (PN). The proposed design methodology results in a state-of-the-art -193 dBc/Hz FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> .

A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs

This work introduces an accurate linearized model and phase noise spectral analysis of digital bang-bang PLLs, that includes both the reference and the digitally-controlled oscillator (DCO) noise contributions. A time-domain analysis of bang-bang PLLs is leveraged to derive closed-form expressions for the integrated jitter, leading to a precise estimation of the binary phase detector (BPD) equivalent gain. The theoretical predictions differ by less than 1% from the simulation results obtained using a behavioral model, in all typical cases: dominant reference noise, dominant DCO noise, and comparable contributions. An accurate discrete-time model that takes into account the time-variant effect arising from the multirate nature of a digital phase-locked loop (DPLL) is used, along with the provided estimation of the jitter, to predict the output and input-referred phase noise spectra. An excellent match with the simulated spectra is achieved for all the different operating conditions.

A Novel Fast-Locking ADPLL Based on Bisection Method

Based on the idea of bisection method, a new structure of All-Digital Phased-Locked Loop (ADPLL) with fast-locking is proposed. The structure and locking method are different from the traditional ADPLLs. The Control Circuit consists of frequency compare module, mode-adjust module and control module, which is responsible for adjusting the frequency control word of digital-controlled-oscillator (DCO) by Bisection method according to the result of the frequency compare between reference clock and restructure clock. With a high frequency cascade structure, the DCO achieves wide tuning range and high resolution. The proposed ADPLL was designed in SMIC 180 nm CMOS process. The measured results show a lock range of 640-to-1920 MHz with a 40 MHz reference frequency. The ADPLL core occupies 0.04 mm2, and the power consumption is 29.48 mW, with a 1.8 V supply. The longest locking time is 23 reference cycles, 575 ns, at 1.92 GHz. When the ADPLL operates at 1.28 GHz–1.6 GHz, the locking time is the shortest, only 9 reference cycles, 225 ns. Compared with the recent high-performance ADPLLs, our design shows advantages of small area, short locking time, and wide tuning range.

Capacitive Boosted Ring Oscillators for All-Digital Phase-Locked Loops (ADPLLs)

Ring oscillator (RO)-based digital phase-locked loops (DPLLs) are very attractive for system-on-chip applications due to their tuning range, good phase noise property but suffer from compactness and power requirements. In this work, the concept of capacitive boosting as one of the key solutions which enhances the amplitude of oscillations of the RO is proposed, making it a suitable solution to the biomedical applications, specifically for medical implant communication system (MICS) band of operation ranging from 400[Formula: see text]MHz to 405[Formula: see text]MHz. With coarse and fine-tuning blocks, this digitally controlled oscillator (DCO) promises a good resolution. The coarse tuning is achieved using conventional MOS capacitors and the fine-tuning is achieved by controlling the fractional metal oxide semiconductor (MOS) capacitances. To benchmark the performance metrics of the single-stage RO in this work, simulations were performed for 680[Formula: see text]mV supply voltage in 45[Formula: see text]nm complementary metal oxide semiconductor (CMOS) technology. The output varies in the range from [Formula: see text]0.422[Formula: see text]V to [Formula: see text][Formula: see text]V, indicating about 224% amplitude enhancement. Despite process voltage temperature (PVT) variations, we can see little impact on the boosted output levels. The designed DCO operates up to a maximum frequency of 495[Formula: see text]MHz at 0.68[Formula: see text]V. The proposed RO has lesser power consumption than any conventional RO, operating at a center frequency of 402[Formula: see text]MHz, thus making it better suitable for the MICS band of applications. Phase noise of [Formula: see text][Formula: see text]dBc/Hz at an offset of 200[Formula: see text]kHz was obtained. The proposed differential DCO consumed power was 95.26[Formula: see text][Formula: see text]W. The figure of merit (FoM) for this DCO is [Formula: see text] (dBc/Hz). The area consumed by the DCO is 0.01872[Formula: see text]mm2.

Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator

This paper presents a comparative study between two different implementations of digitally-controlled-oscillators (DCOs), whcih is the DAC-based and the digital controller-based DCO in TSMC 65 nm CMOS technology. This paper focuses on ring-oscillator architectures due to their high stability against PVT. The DAC-based oscillator implements a differential architecture, and the digital controller-based architecture operates in a single-ended signal. The SFDR of the DAC-based DCO is 77.2 dBc and controller-based DCO is 56.8 dBc at 125 MHz offset. The Monte-Carlo simulation gives a deviation of 7.4% and 8.5% for the DAC-based and controller-based DCO, respectively. The phase noise performance of the DAC-based DCO and controller-based DCO is −78.9 dBc/Hz and −81.3 dBc/Hz at 1 MHz offset, respectively. The implementations are given and compared according to their performance based on post-layout simulation results.

Hybrid Cross Coupled Differential Pair and Colpitts Quadrature Digitally Controlled Oscillator Architecture

Growing importance of wireless communication systems forces reduction of power consumption of the designed integrated circuits. The paper focuses on minimization of power consumption in a digitally controlled oscillator (DCO) that can be employed as oscillator in GPS/Galileo receiver. The new hybrid architecture of DCO combines good phase noise performance of a Colpitts oscillator and relaxed startup conditions of a cross-coupled differential pair oscillator. The proposed new DCO generates a quadrature signal in a current reused frequency divider. Such solution allows of the dissipated power to be reduced. The DCO has been implemented in 110 nm CMOS technology. It generates output signal in frequency range from 1.52 GHz to 1.6 GHz and consumes 1.1 mW from 1.5 V supply voltage. The measured phase noise equals −116 dBc/Hz at 1 MHz offset from 1.575 GHz output signal.