Digital Complementary Metal-oxide-semiconductor Research Articles

Digital Modulator using Digitally Programmable Complementary metal–oxide–semiconductor Differential Voltage Current Conveyor

This study aims to Developing a digital modulation system using a new technology and idea, which is the digitally programmable CMOS (Complementary metal–oxide–semiconductor), Integrate the CMOS DVCC circuit as a modulator in the communication systems, as will be explained in chapter 3, Finally, simulate this new idea in communication by using a simulation program, which is PSpice software, and analyzing the results. By focusing on How to use digital programmable CMOS (Complementary Metal–Oxide–Semiconductor) in a communication system as a digital modulator, Verifying the effectiveness of the study using simulation software such as PSpice and MATLAB, and Analyzing and verifying the effectiveness of the three modified modulation techniques. Digitally programmable Binary Amplitude shift keying (DP BASK), Digitally programmable Binary Phase shift keying (DP BPSK), And Digitally programmable Binary Frequency shift keying (DP BFSK). This study adopts an applied research approach. The study demonstrated that the CMOS DVCC circuit could be successfully integrated into communication systems as a digital modulator. The study recommended to conduct further research on the noise resistance capabilities of the DP modulation techniques, and explore additional modulation techniques that could benefit from digitally programmable CMOS technology, such as Quadrature Amplitude Modulation (QAM) or Orthogonal Frequency-Division Multiplexing (OFDM).

Memristor-CMOS Hybrid Circuits Implementing Event-Driven Neural Networks for Dynamic Vision Sensor Camera.

For processing streaming events from a Dynamic Vision Sensor camera, two types of neural networks can be considered. One are spiking neural networks, where simple spike-based computation is suitable for low-power consumption, but the discontinuity in spikes can make the training complicated in terms of hardware. The other one are digital Complementary Metal Oxide Semiconductor (CMOS)-based neural networks that can be trained directly using the normal backpropagation algorithm. However, the hardware and energy overhead can be significantly large, because all streaming events must be accumulated and converted into histogram data, which requires a large amount of memory such as SRAM. In this paper, to combine the spike-based operation with the normal backpropagation algorithm, memristor-CMOS hybrid circuits are proposed for implementing event-driven neural networks in hardware. The proposed hybrid circuits are composed of input neurons, synaptic crossbars, hidden/output neurons, and a neural network's controller. Firstly, the input neurons perform preprocessing for the DVS camera's events. The events are converted to histogram data using very simple memristor-based latches in the input neurons. After preprocessing the events, the converted histogram data are delivered to an ANN implemented using synaptic memristor crossbars. The memristor crossbars can perform low-power Multiply-Accumulate (MAC) calculations according to the memristor's current-voltage relationship. The hidden and output neurons can convert the crossbar's column currents to the output voltages according to the Rectified Linear Unit (ReLU) activation function. The neural network's controller adjusts the MAC calculation frequency according to the workload of the event computation. Moreover, the controller can disable the MAC calculation clock automatically to minimize unnecessary power consumption. The proposed hybrid circuits have been verified by circuit simulation for several event-based datasets such as POKER-DVS and MNIST-DVS. The circuit simulation results indicate that the neural network's performance proposed in this paper is degraded by as low as 0.5% while saving as much as 79% in power consumption for POKER-DVS. The recognition rate of the proposed scheme is lower by 0.75% compared to the conventional one, for the MNIST-DVS dataset. In spite of this little loss, the power consumption can be reduced by as much as 75% for the proposed scheme.

A 1.8 V 25 Mbps CMOS single-phase, phase-locked loop-based BPSK, QPSK demodulator

A single-phase binary/quadrature phase-shift keying (BPSK/QPSK) demodulator basing on a phase-locked loop (PLL) is described. The demodulator relies on a linear characteristic a rising-edge RESET/SET flip-flop (RSFF) employed as a phase detector. The phase controller takes the average output from the RSFF and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for a multiple-PSK (m-PSK) signal. Symbol-error rate analysis has also been extensively carried out. The proposed BPSK and QPSK demodulators have been fabricated in a 0.18<em>-</em>mm digital complementary metal–oxide–semiconductor (CMOS) process where they operate from a single supply of 1.8 V. At a carrier frequency of 60 MHz, the BPSK and QPSK demodulators achieved maximum symbol rates of 25 and 12.5 Msymb/s while consuming 0.68 and 0.79 mW, respectively. At these maximum symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 7.9×10<sup>-10</sup> and 9.8×10<sup>-10</sup>, respectively where their corresponding energy per bit figures were at 27.2 and 31.7 pJ.

Controllable Oxidation of ZrS2 to Prepare High-κ, Single-crystal m-ZrO2 for 2D Electronics.

High-κ materials that exhibit large permittivity and band gaps are needed as gate dielectrics to enhance capacitance and prevent leakage current in downsized technology nodes. Among these, monoclinic ZrO2 (m-ZrO2 ) shows good potential because of its inertness and high-κ with respect to SiO2 , but a method to produce ultrathin single crystal is lacking. Here, the controllable preparation of ultrathin m-ZrO2 single crystals via the in situ thermal oxidation of ZrS2 is achieved. As-grown m-ZrO2 presents an equivalent oxide thickness of ≈0.29nm, a high dielectric constant of ≈19, and a breakdown voltage (EBD ) of ≈7.22 MV cm-1 . MoS2 field effect transistor (FET) by using m-ZrO2 as a dielectric layer shows comparable mobility to that using SiO2 dielectric. The ultraclean interface of m-ZrO2 /MoS2 and high crystalline quality of m-ZrO2 lead to negligible hysteresis in transfer curves. Single crystal m-ZrO2 dielectric shows potential application in digital complementary metal oxidesemiconductor (CMOS) logic FET.

Materials for emergent silicon-integrated optical computing.

Progress in computing architectures is approaching a paradigm shift: traditional computing based on digital complementary metal-oxide semiconductor technology is nearing physical limits in terms of miniaturization, speed, and, especially, power consumption. Consequently, alternative approaches are under investigation. One of the most promising is based on a "brain-like" or neuromorphic computation scheme. Another approach is quantum computing using photons. Both of these approaches can be realized using silicon photonics, and at the heart of both technologies is an efficient, ultra-low power broad band optical modulator. As silicon modulators suffer from relatively high power consumption, materials other than silicon itself have to be considered for the modulator. In this Perspective, we present our view on such materials. We focus on oxides showing a strong linear electro-optic effect that can also be integrated with Si, thus capitalizing on new materials to enable the devices and circuit architectures that exploit shifting computational machine learning paradigms, while leveraging current manufacturing infrastructure. This is expected to result in a new generation of computers that consume less power and possess a larger bandwidth.

Basic study on evaluation of X-ray dose distribution using plastic scintillator plate and digital CMOS camera

Evaluation of dose distribution in a phantom is effective for quality control of radiation diagnostic equipment and evaluation of exposure. However, measurements at multiple points using a dosimeter is complicated. An alternative is to combine a plastic scintillator (PS) plate and digital camera to obtain the dose distribution of the entire phantom. In this study, the basic characteristics of this system were examined. A PS was sandwiched between Polymethyl Methacrylate (PMMA) disk phantoms, and irradiation was performed while the tube current was changed from one direction. The tube voltage was set to two values, specifically 60 and 120 kV. During irradiation, the entire phantom was recorded at 0.1 s intervals using a digital Complementary Metal Oxide Semiconductor (CMOS) camera. The lowest dose rate where luminescence could be detected was approximately 1 mGy per 0.1 s. The amount of luminescence increased linearly with the dose rate. The proportional relationship that was confirmed between dose rate and luminescence suggests the possibility of using the system for dose estimation. This proposed dose-evaluation method can enable the dose distribution to be evaluated with a time resolution of 0.1 s and a high spatial resolution.

Microwave functionality of spintronic devices implemented in a hybrid complementary metal oxide semiconductor and magnetic tunnel junction technology

This letter presents magnetic tunnel junction based spintronic devices completely implemented in a hybrid semiconductor process that comprises a complementary metal oxide semiconductor and a magnetic tunnel junction technology. To demonstrate the coexistence of both complementary metal oxide semiconductor circuits and magnetic tunnel junction based spintronic devices, a proof-of-concept circuit prototype comprising 40 spintronic devices and a digital complementary metal oxide semiconductor serial peripheral interface is fabricated. According to measurement results, a selected spintronic device from the magnetic tunnel junction array, when surrounded by an external out-ofplane magnetic field of 1 kOe, emitted microwave signals from 2.235 to 2.464 GHz with an output power from 0.88 to 0.72 nW, when the DC current was increased from 0.6 to 1.0 mA. To the authors' best knowledge, this is the first work demonstrating the functionality of spintronic oscillators fully integrated in complementary metal oxide semiconductor circuit implemented in a hybrid complementary metal oxide semiconductor and magnetic tunnel junction process.

An Energy-Efficient and Approximate Accelerator Design for Real-Time Canny Edge Detection

This paper proposes a dedicated hardware design approach focused on the adoption of state-of-the-art approximate adders (AAs) for the design of CMOS (complementary metal–oxide–semiconductor) Canny edge detection hardware accelerators. The proposed method leverages state-of-the-art AAs in the compute-intensive Gaussian and Gradient filter steps of the Canny edge detection algorithm. The key objectives of our accelerator architecture are: (1) to provide real-time Canny edge operation by proposing an energy-efficient ASIC (application specific integrated circuit) architecture and (2) to further reduce energy consumption when adopting the proposed design-time approach for approximate arithmetic operations. The proposed accelerator architecture considers two methods for the magnitude computation: (1) the square root operator and (2) the absolute operator. All proposed architectures herein developed were described in VHDL and synthesized in a 45 nm digital CMOS ASIC design. Results show that the baseline architecture takes only 0.42 ms to process an 8-bit 512 × 512 pixels image at a maximum VLSI operating frequency of 631 MHz. When considering all the approximate architecture versions and the methods for magnitude computation, the maximum energy reduction achieved is 44.3% when compared to the baseline architecture in an iso-performance analysis. This significant energy reduction is achieved when an average F measure quality metric equal to 0.79 is obtained.

60 pW 20 μm size CMOS implementation of an actual soma membrane

The article presents a 65 nm technology implementation of a low-power artificial spiking neuron intellectual property (IP) core. The concept of the circuit is based on modeling the mechanism of a perikaryon membrane and the propagation of the action potential in an axon. Nerve impulses are generated using a current-controlled oscillator. Thanks to this oscillator, the circuit is implemented exclusively using metal-oxide semiconductor transistors, with the omission of capacitors. The main advantage of the presented implementation is the possibility of implementing the IP-core using nanometer digital complementary metal-oxide semiconductor technologies with the possibility of placing it within a common substrate with a digital processor. The circuit operates in weak-inversion mode with a 0.3 V power supply and does not require additional polarization voltages. The maximum frequency of impulse generation equals 2.5 kHz. The paper describes two operating modes of the circuit: a cortical mode with power consumption of 60 pW and a processing mode with power consumption of 52.2 pW. The power reduction was obtained using a circuit structure in which the power supply current consumption is reduced with the moment the circuit starts processing. The article also contains results of a process–voltage–temperature analysis.

Low-Power, Electrochemically Tunable Graphene Synapses for Neuromorphic Computing.

Brain-inspired neuromorphic computing has the potential to revolutionize the current computing paradigm with its massive parallelism and potentially low power consumption. However, the existing approaches of using digital complementary metal-oxide-semiconductor devices (with "0" and "1" states) to emulate gradual/analog behaviors in the neural network are energy intensive and unsustainable; furthermore, emerging memristor devices still face challenges such as nonlinearities and large write noise. Here, an electrochemical graphene synapse, where the electrical conductance of graphene is reversibly modulated by the concentration of Li ions between the layers of graphene is presented. This fundamentally different mechanism allows to achieve a good energy efficiency (<500 fJ per switching event), analog tunability (>250 nonvolatile states), good endurance, and retention performances, and a linear and symmetric resistance response. Essential neuronal functions such as excitatory and inhibitory synapses, long-term potentiation and depression, and spike timing dependent plasticity with good repeatability are demonstrated. The scaling study suggests that this simple, two-dimensional synapse is scalable in terms of switching energy and speed.

Nano-scale area-efficient Gm–C filters using MOS capacitors

ABSTRACTThe rapid growth of scaling and integration of nano-scale digital circuits is hardly tracked by the analog circuits which require additional passive components for fabrication. Mixed-signal Complementary Metal Oxide Semiconductor (CMOS) technologies are released with some delays after digital CMOS technologies, due to the issues related to integration of analog components. This urges the designers to consider using the same digital CMOS technology for integration of advanced analog circuits like continuous-time filters. As such, this article presents an area-efficient Gm–C filter made from MOS devices only. Instead of classical metal–insulator–metal capacitors, the proposed filter exploits the available compact-size MOS devices as capacitor. This modification makes the filter design compatible to any low-cost digital CMOS process. Besides, the 3-dB cut-off frequency of the filter can now be changed by varying the size of MOS capacitors. The effectiveness of the new design approach is validated through simulation of a fifth-order elliptic low-pass filter with a cut-off frequency of 1 MHz in 90-nm CMOS technology. The new filter dissipates around 115 µW from a 1.0 V power supply, and the sensitivity of its cut-off frequency is kept as low as 6% over various process and temperature corners.

CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs.

A High-Dynamic-Range Optical Remote Sensing Imaging Method for Digital TDI CMOS

The digital time delay integration (digital TDI) technology of the complementary metal-oxide-semiconductor (CMOS) image sensor has been widely adopted and developed in the optical remote sensing field. However, the details of targets that have low illumination or low contrast in scenarios of high contrast are often drowned out because of the superposition of multi-stage images in digital domain multiplies the read noise and the dark noise, thus limiting the imaging dynamic range. Through an in-depth analysis of the information transfer model of digital TDI, this paper attempts to explore effective ways to overcome this issue. Based on the evaluation and analysis of multi-stage images, the entropy-maximized adaptive histogram equalization (EMAHE) algorithm is proposed to improve the ability of images to express the details of dark or low-contrast targets. Furthermore, in this paper, an image fusion method is utilized based on gradient pyramid decomposition and entropy weighting of different TDI stage images, which can improve the detection ability of the digital TDI CMOS for complex scenes with high contrast, and obtain images that are suitable for recognition by the human eye. The experimental results show that the proposed methods can effectively improve the high-dynamic-range imaging (HDRI) capability of the digital TDI CMOS. The obtained images have greater entropy and average gradients.

Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology

A 10‐bit pipelined analogue‐to‐digital converter (ADC) at a sampling rate of 100 MS/s utilising only metal–oxide–semiconductor (MOS) transistors is presented and designed in 1.8 V 0.18 μm standard digital complementary MOS (CMOS) n‐well technology. The internal gain of value 2 of the intermediate stages is achieved by using a charge‐pump‐based concept that avoids the use of power‐area inefficient operational amplifier. All the capacitors are realised by capacitors implemented by metal–oxide–semiconductor field‐effect transistors (MOSCAPs) that allows easy integration with any inexpensive standard digital CMOS technology, and altogether giving low area‐power‐cost solution. A low DC gain CMOS differential amplifier in source follower configuration is used and low gain effects are calibrated digitally in the background. Peak differential non‐linearity (DNL) improves from −1/+0.27 least significant bit (LSB) to −0.43/+0.57 LSB and peak integral non‐linearity (INL) is reduced from −9.56/+9.3 LSB to within range of ±0.5 LSB after calibration. Also signal‐to‐noise plus distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) increase to 65.4 and 72.08 dB, respectively, after calibration.

20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS

The design of an analog frontend including a receiver amplifier (RX) and laser diode driver (LDD) for optical communication system is described. The RX consists of a transimpedance amplifier, a limiting amplifier, and an output buffer (BUF). An offset compensation and common-mode control circuit is designed using switched-capacitor technique to save chip area, provides continuous reduction of the offset in the RX. Active-peaking methods are used to enhance the bandwidth and gain. The very low gate-oxide breakdown voltage of transistors in deep sub-micron technologies is overcome in the LDD by implementing a topology which has the amplifier placed in a floating well. It comprises a level shifter, a pre-amplifier, and the driver stage. The single-chip frontend, fabricated in a 28 nm bulk-digital complementary metal–oxide–semiconductor (CMOS) process has a total active area of 0.003 mm2, is among the smallest optical frontends. Without the BUF, which consumes 8 mW from a separate supply, the RX power consumption is 21 mW, while the LDD consumes 32 mW. Small-signal gain and bandwidth are measured. A photo diode and laser diode are bonded to the chip on a test-printed circuit board. Electro-optical measurements show an error-free detection with a bit error rate of 10−12at 20 Gbit/s of the RX at and a 25 Gbit/s transmission of the LDD.

Pulse quenching induced by multi-collection effects in 45 nm silicon-on-insulator technology

This paper presents the analysis of pulse quenching effects induced in silicon-on-insulator (SOI) technology. Simulation results emphasize the need to consider multi-collection effects in the occurrence mechanisms of single event transients (SET) in very large scaling integration (VLSI) components even with SOI technologies, which is known to be initially less sensitive to soft errors (SE). The impacts of gate-to-gate spacing and voltage scaling on the SET occurrence and characteristics have been highlighted. The simulations have been performed with the soft error prediction tool MUSCA SEP3 developed for digital complementary metal oxide semiconductor (CMOS) technologies (SOI, Bulk).

Design of area and energy-efficient digital CMOS FIR filters with approximate adder circuits

This paper proposes the use of alternative approximate adders for fully parallel energy-efficient complementary metal---oxide---semiconductor (CMOS) finite impulse response (FIR) filters design. The filters to be approximated are first optimized for low power by a state-of-the-art multiplier-less multiple constant multiplication algorithm. We further evaluate magnitude error and accuracy for different state-of-the-art approximate adder techniques plus the truncation of adders, and validate this with 16-bit audio signals histogram analysis. Once the approximation is performed for all the filters, we evaluate the signal-to-noise ratio (SNR) response for ten recorded audio signals. All precise and approximate filters benchmark cases with different SNR targets are synthesized and mapped onto a 45 nm CMOS PDK for full ASIC implementation. Energy-efficiency results show that our proposed approximate filters, subject to a 50 dB Signal to Noise + Distortion Ratio required floor, reduce on average the energy per filtered sample by up to 24.8 and 23.8 % for 100 and 10 MHz circuit operation, respectively.

A 340-GHz Heterodyne Receiver Front End in 40-nm CMOS for THz Biomedical Imaging Applications

A low-power and high-performance 340-GHz heterodyne receiver front end (RFE) optimized for terahertz (THz) biomedical imaging applications is proposed in this paper. The THz RFE consists of an on-chip patch antenna, a single-balanced mixer, and a triple-push harmonic oscillator. The oscillator adopts a proposed harmonic oscillator architecture which can provide differential output by extracting output signals from the same current loop without any additional balun required. The mixer biased in the subthreshold region is designed not only to have high conversion gain and low noise figure by choosing the output intermediate frequency well above the flicker-noise corner frequency, but the required local oscillator (LO) power can also be as low as –11 dBm. Such a low demand on the LO power makes the proposed mixer very suitable for THz applications in which the achievable LO power is very limited. The impact of unavoidable slots for passing design rule checks on the performance of an on-chip patch antenna is also presented. The proposed THz RFE is implemented in a 40-nm digital complementary metal–oxide–semiconductor technology. The measured voltage conversion gain is –1.7 dB at 335.8 GHz, while the mixer and the oscillator only consume 0.3 and 52.8 mW, respectively, from a 1.1 V supply. The proposed THz RFE is employed to set up a THz transmissive imaging system which can provide spatial resolution of 1.4 mm.

Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology

ABSTRACTA simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost.

Electrical behavior of the Diamond layout style for MOSFETs in X-rays ionizing radiation environments

This paper aims to describe some innovative layout styles, which are capable to boost the electrical performance and, in the same time, the Total Ionizing Dose (TID) tolerance of Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), without burdening the current planar Complementary MOS (CMOS) Integrated Circuits (ICs) manufacturing processes. To illustrate the potential use of these new alternative devices in analog and digital CMOS ICs applications, this work focuses on the Diamond layout style for MOSFET that presents hexagonal gate geometry. The new effects associated to this innovative transistor structure and its modeling are presented and discussed in detail. Some experimental results are illustrated to evidence its use mainly in space and medical CMOS ICs applications.